JP2987251B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2987251B2 JP2987251B2 JP4070872A JP7087292A JP2987251B2 JP 2987251 B2 JP2987251 B2 JP 2987251B2 JP 4070872 A JP4070872 A JP 4070872A JP 7087292 A JP7087292 A JP 7087292A JP 2987251 B2 JP2987251 B2 JP 2987251B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor chip
- semiconductor device
- inner lead
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ゲ−トアレイなどの樹
脂封止型半導体装置に関し、特に、多ピンパッケ−ジに
適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device such as a gate array, and more particularly to a technique effective when applied to a multi-pin package.
【０００２】[0002]
【従来の技術】従来、ゲ−トアレイなどの樹脂封止型半
導体装置における多ピンパッケ−ジの場合、半導体チッ
プ上の周辺のみでは電極パッドを配置することができな
いので、半導体チップ上の内側電極パッドと外側電極パ
ッドとを交互に配置している。そして、インナーリード
の先端が前記半導体チップからみて近いリード（以下、
長リードという）と遠いリード（以下、短リードとい
う）とを交互に配置して、それぞれ隣接するワイヤが接
触しないようにするために高低差を付けて半導体チップ
の電極パッドとインナーリードとをワイヤで電気的に接
続している。このとき、前記長リ−ドの位置は、短リ−
ドに接続したワイヤのちょうど中間に来るように設計し
ている。2. Description of the Related Art Conventionally, in the case of a multi-pin package in a resin-encapsulated semiconductor device such as a gate array, an electrode pad cannot be arranged only on the periphery of a semiconductor chip. And the outer electrode pads are alternately arranged. Then, the tip of the inner lead is closer to the semiconductor chip when viewed from the semiconductor chip (hereinafter, referred to as the semiconductor chip).
Long leads) and distant leads (hereinafter referred to as short leads) are alternately arranged, and the electrode pads of the semiconductor chip and the inner leads are wired with a difference in height so that adjacent wires do not come into contact with each other. Is electrically connected. At this time, the position of the long lead is
It is designed to be exactly in the middle of the wire connected to the wire.
【０００３】[0003]
【発明が解決しようとする課題】この設計方法では、ワ
イヤボンディング後のワイヤと長リ−ドのクロスは防止
できるが、モ−ルド時にワイヤが流れた場合には、短リ
−ドに接続されたワイヤと長リ−ドがクロスする場合が
あるという問題点を本発明者が見い出した。According to this design method, it is possible to prevent crossing between a wire after wire bonding and a long lead, but if a wire flows during molding, it is connected to a short lead. The present inventor has found a problem that the long lead may cross the wire.
【０００４】本発明の目的は、モ−ルド時にワイヤが流
れても、隣接する短リ−ドに接続されたワイヤと長リ−
ドがクロスしないようにすることが可能な技術を提供す
ることにある。[0004] It is an object of the present invention to provide a structure in which a wire connected to an adjacent short lead is connected to a long lead even if the wire flows during molding.
It is an object of the present invention to provide a technology capable of preventing a cross from crossing.
【０００５】本願発明の他の目的は、Ｘ線検査で良と不
良の判定を容易に行なうことが可能な技術を提供するこ
とにある。なお、特開平２-１２１３６１号公報には、
チップに内側電極パッドと外側電極パッドを形成し、イ
ンナーリード先端とチップの距離が近いものと遠いもの
を交互に配置しかつボンディングワイヤの高さを変えた
ものが、また、特開平３-２７５６３号公報にはチップ
に一列に配置された電極パッドに特開平２-１２１３６
１号公報記載と同様のインナーリードとワイヤボンディ
ングを施したものが記載されているが、何れもインナー
リードが上下２層になっており、一層のリードフレーム
を用いて、モールド時のワイヤクロスを防止する技術に
ついては記載されていない。 Another object of the present invention is to provide a technique capable of easily determining good or bad by X-ray inspection. In addition, JP-A-2-121361 discloses that
Form inner and outer electrode pads on the chip
The distance between the tip of the inner lead and the tip is short or far
Were alternately arranged and the height of the bonding wire was changed.
And Japanese Patent Application Laid-Open No. 3-27563 discloses a chip.
Japanese Patent Laid-Open No. 2-12136 describes electrode pads arranged in a row.
Inner lead and wire bonder similar to that described in JP-A-1
Is described, but in any case the inner
Leads are in two layers, upper and lower, one-layer lead frame
Technology to prevent wire crossing during molding
It is not described.
【０００６】本発明の前記ならびにその他の目的及び新
規な特徴は、本明細書の記述及び添付図面によって明ら
かになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【０００７】[0007]
【課題を解決するための手段】本願において開示される
発明のうち代表的なものの概要を簡単に説明すれば、下
記のとおりである。The following is a brief description of an outline of typical inventions disclosed in the present application.
【０００８】すなわち、半導体チップ上の周辺部に複数
の電極パッドが形成され、前記複数の電極パッドと複数
のインナーリードとがボンディングワイヤにより夫々電
気的に接続され、封止樹脂によってモールドされた半導
体装置であって、前記半導体装置には第１のインナーリ
ードと、前記第１のインナーリードに隣接し先端部が前
記第１のインナーリードよりも半導体チップから離間し
た第２のインナーリードとが設けられ、前記第１のイン
ナーリードと前記第２のインナーリードの先端部は同じ
高さに位置し、前記第１のインナーリードと前記半導体
チップの一の電極パッドに接続されたワイヤの高さは前
記第２のインナーリードと前記半導体チップの他の電極
パッドに接続されたワイヤの高さよりも低く、前記第１
のインナーリードの先端部は、前記封止樹脂モールドの
流れ方向に曲げられている。[0008] That is, a plurality of peripheral portions on the semiconductor chip
Electrode pads are formed, and the plurality of electrode pads and the plurality of electrode pads are formed.
And the inner leads are electrically connected by bonding wires.
Semiconductor that is connected pneumatically and molded with sealing resin
Body device, wherein the semiconductor device has a first inner line.
And the front end is adjacent to the first inner lead and has a front end.
The first inner lead is more distant from the semiconductor chip than the inner lead.
A second inner lead is provided, and the first inner lead is provided.
The tip of the inner lead is the same as the tip of the second inner lead
The first inner lead and the semiconductor located at a height
The height of the wire connected to one electrode pad of the chip is
The second inner lead and another electrode of the semiconductor chip
Lower than the height of the wire connected to the pad,
The tip of the inner lead of the sealing resin mold
It is bent in the flow direction .
【０００９】また、半導体チップ上の周辺部に内側列と
外側列の２列に交互に配置された電極パッドと、リード
とがボンディングワイヤで電気的に接続された半導体装
置であって、前記リードは先端部の高さが一様で順次隣
接する第１のリードと第２のリードと第３のリードとを
有し、前記第１のリードよりも第２のリードの長さが短
く、前記第２のリードよりも第３のリードの長さが長
く、前記第１のリード及び第３のリードは、夫々樹脂封
止によるワイヤ流れに応じた角度にその先端部を曲げて
形成されている Further , an inner row is provided at a peripheral portion on the semiconductor chip.
Electrode pads and leads alternately arranged in two outer rows
Semiconductor device electrically connected to the
The leads have the same height at the tip and are adjacent to each other in sequence.
The first lead, the second lead, and the third lead
The length of the second lead is shorter than that of the first lead
And the length of the third lead is longer than that of the second lead.
The first lead and the third lead are respectively sealed with resin.
Bend the tip to an angle according to the wire flow
Is formed
【００１０】[0010]
【作用】前述の手段によれば、インナーリードの先端が
半導体チップに近いリードの先端部をモールド時のワイ
ヤ流れに対応する所定の角度だけ曲げているので、モ−
ルド後のワイヤとリ−ドのクロスを防止することができ
る。その結果、Ｘ線検査時に良品と不良品の判別を容易
することができる。According to the above-mentioned means, the tip of the inner lead bends the tip of the lead close to the semiconductor chip by a predetermined angle corresponding to the wire flow during molding.
After the soldering, the wire and the lead can be prevented from crossing each other. As a result, at the time of X-ray inspection, it is possible to easily discriminate a good product from a defective product.
【００１１】[0011]
【実施例１】以下、本発明の実施例を図面を用いて詳細
に説明する。Embodiment 1 Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
【００１２】実施例を説明する全図において、同一機能
を有するものは同一符号を付け、その繰り返しの説明は
省略する。In all the drawings for explaining the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
【００１３】図１は、本発明の樹脂封止型半導体装置の
一実施例の２０８ピンのリ−ドフレ−ムと半導体チップ
上の電極パッドのレイアウトを示す平面図、図２は、図
１の要部断面図である。FIG. 1 is a plan view showing the layout of a 208-pin lead frame and electrode pads on a semiconductor chip according to an embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. It is principal part sectional drawing.
【００１４】図１及び図２において、１はタブ、２はタ
ブ１上に搭載されている半導体チップ、３は半導体チッ
プ２上に配置されている電極パッド、４は長リード、５
は短リード、６はタブ吊りリード、７はボンディングワ
イヤ、８はモールドレジン(封止樹脂）、９はレジン流
入ゲート、１０はレジン流出ゲート、１１はタブ２に設
けられているスリットであり、このスリット１１はレジ
ン（樹脂）モールドの時に発生する水蒸気を逃がすため
のもである。1 and 2, 1 is a tab, 2 is a semiconductor chip mounted on the tab 1, 3 is an electrode pad arranged on the semiconductor chip 2, 4 is a long lead,
Is a short lead, 6 is a tab suspension lead, 7 is a bonding wire, 8 is a mold resin (sealing resin), 9 is a resin inflow gate, 10 is a resin outflow gate, 11 is a slit provided in the tab 2, The slit 11 is for releasing water vapor generated at the time of resin (resin) molding.
【００１５】前記半導体チップ２上の電極パッド３は、
図３に示すように、内側電極パッド３Ｂと外側電極パッ
ド３Ａが交互に配置されている。また、前記長リード４
は、そのインナーリード４Ａの先端部４Ａ1 が前記半導
体チップ２からみて短リード５のインナーリード５Ｂの
先端部より近い位置に配置され、かつ、長リード４と短
リード５とは交互に配置されている。そして、それぞれ
隣接する半導体チップ２の電極パッド３Ａと長リード４
のインナーリード４Ａとが、電極パッド３Ｂと短リード
５のインナーリード５Ｂとがそれぞれ高低差を付けてワ
イヤ７Ａ，７Ｂで電気的に接続され、モールドレジン
（封止樹脂）８でモールド（封止）されている。The electrode pads 3 on the semiconductor chip 2
As shown in FIG. 3, the inner electrode pads 3B and the outer electrode pads 3A are alternately arranged. In addition, the long lead 4
, The inner lead 4A tip 4A 1 of is located closer than the distal end portion of the inner lead 5B of the semiconductor chip 2 as viewed from the short lead 5, and the long lead 4 and the short leads 5 are arranged alternately ing. The electrode pads 3A and the long leads 4 of the adjacent semiconductor chips 2 are respectively provided.
The inner lead 4A is electrically connected to the electrode pad 3B and the inner lead 5B of the short lead 5 with wires 7A and 7B with a difference in height, respectively, and is molded (sealed) with a molding resin (sealing resin) 8. ) Has been.
【００１６】前記長リード４のインナーリード４Ａの先
端４Ａ1 は、図４に示すように、レジンのモールド時の
隣の短リード５のワイヤ７Ｂの流れに応じて所定の角度
θだけ曲げられている。この曲げ角度θは、短リード５
のワイヤ７Ｂの長さをＬ、長リード４の曲げ量をｘ、曲
り率（Ｌ／ｘ）×１００（％）とすると、次式（１）で
表すことができる。[0016] The long inner leads 4A tip 4A 1 of the lead 4, as shown in FIG. 4, bent by a predetermined angle θ in accordance with the flow of the wire 7B short lead 5 next to during molding of the resin I have. This bending angle θ is the short lead 5
If the length of the wire 7B is L, the amount of bending of the long lead 4 is x, and the bending rate (L / x) × 100 (%), the following equation (1) can be obtained.
【００１７】[0017]
【数１】 ｔａｎθ＝ｘ／（Ｌ／２）＝２ｘ／Ｌ ・・・・・・・（１） 前記レジンによるワイヤ流れに応じてリード曲げ角度θ
を５ブロックに分けて、前記式（１）により各ブロック
のインナーリード４Ａの先端４Ａ1の曲げ角度θを計算
して決める。それらの計算結果を表１に示す。Tan θ = x / (L / 2) = 2x / L (1) The lead bending angle θ according to the wire flow by the resin.
The divided into 5 blocks, determined by calculating the bending angle θ of the tip 4A 1 of the inner lead 4A of each block by the formula (1). Table 1 shows the calculation results.
【００１８】[0018]
【表１】 [Table 1]
【００１９】また、前記各ブロックに対する曲り率（Ｌ
／ｘ）×１００（％）をグラフにすると、図５のように
なる。The curvature ratio (L) for each block is
FIG. 5 is a graph of (/ x) × 100 (%).
【００２０】つまり、レジンは、図１の左上コ−ナ−に
設けられているレージン流入ゲート９から流入し、ワイ
ヤ７を押し流しながら右下コ−ナ−に設けられているレ
ジン流出ゲート１０方向に流れる。ワイヤ７の流れ量
は、左上コ−ナ−及び右下コ−ナ−が最も小さく、左下
及び右上のコ−ナ−が最も大きい。ワイヤ７の流れ量
は、最も小さいコ−ナ−から、最も大きいコ−ナ−に向
かって順次大きくなる。したがって、リ−ド先端の曲げ
量もワイヤ７の流れ量に合わせて順次大きくする。本実
施例では、各辺を５ブロックに分けてブロックごとに、
リ−ド先端の曲げ量を決めたが、本発明は、これに限定
されるものではない。That is, the resin flows from the resin inflow gate 9 provided in the upper left corner of FIG. 1, and flows toward the resin outflow gate 10 provided in the lower right corner while flushing the wire 7. Flows to The flow rate of the wire 7 is smallest at the upper left corner and the lower right corner, and is largest at the lower left and upper right corners. The flow rate of the wire 7 gradually increases from the smallest corner to the largest corner. Therefore, the amount of bending at the tip of the lead is also gradually increased in accordance with the amount of flow of the wire 7. In this embodiment, each side is divided into 5 blocks,
Although the amount of bending of the tip of the lead is determined, the present invention is not limited to this.
【００２１】また、図２に示すように、手前パッド（外
側パッド）３Ａと奥パッド（内側パッド）３Ｂに接続す
るワイヤ７Ａ，７Ｂにル−プの高低差を付け上下のクリ
アランスを確保する。ボンディング直後は長リード４の
インナーリード４Ａの先端４Ａ1 を曲げてあるために、
ワイヤ７Ｂとリ−ド４が上から見た平面ではクロスする
場合があるが、これは問題ない。As shown in FIG. 2, the wires 7A and 7B connected to the front pad (outer pad) 3A and the back pad (inner pad) 3B are provided with a difference in the height of the loop to secure the vertical clearance. For immediately after bonding that is bent tip 4A 1 of the inner lead 4A for long leads 4,
The wire 7B and the lead 4 may cross on a plane viewed from above, but this is not a problem.
【００２２】図６は、本実施例１のレジンモ−ルド後の
Ｘ線検査の結果(透視像又は写真)を示す模式図である。
長リード４のインナーリード４Ａの先端４Ａ1 を曲げた
ことにより、長リード４のインナーリード４Ａと短リ−
ド５のインナーリード５Ｂに接続されるワイヤ７Ｂとの
クロスが防止されていることが明らかである。FIG. 6 is a schematic diagram showing the result (perspective image or photograph) of the X-ray inspection after resin molding in the first embodiment.
By bending the tips 4A 1 of the inner lead 4A for long leads 4, the long lead 4 inner lead 4A and Tanri -
It is clear that crossover of the wire 5 with the wire 7B connected to the inner lead 5B of the wire 5 is prevented.
【００２３】したがって、従来の長リ−ドの先端を曲げ
ないリードでは、短リ−ド５に接続されるワイヤ７Ｂの
流れにより長リ−ド４とワイヤ７Ｂとがクロスして、Ｘ
線による検査において良品と不良品との判断が不可能で
あったが、前述の本実施例１によれば、これを可能にす
ることができる。Therefore, in the conventional lead in which the tip of the long lead is not bent, the flow of the wire 7B connected to the short lead 5 causes the long lead 4 and the wire 7B to cross each other, and X
Although it was impossible to determine a non-defective product and a non-defective product in the inspection using a line, according to the above-described first embodiment, this can be made possible.
【００２４】その結果、長ワイヤの製品を安定に製造す
ることが可能となり、ファインピッチ多ピンの製品化が
可能となる。また、長ワイヤの採用によりリ−ドフレ−
ムの共用化が可能となり、開発期間の短縮及びプレスフ
レ−ム化による原価低減が図られる。As a result, a long wire product can be stably manufactured, and a fine pitch multi-pin product can be commercialized. In addition, the lead wire
The system can be shared, shortening the development period and reducing costs by using a press frame.
【００２５】〔実施例２〕図７及び図８は、本発明の実
施例２の要部断面図である。[Embodiment 2] FIGS. 7 and 8 are sectional views of a main part of Embodiment 2 of the present invention.
【００２６】本実施例２の樹脂封止型半導体装置は、図
７に示すように、前記実施例１の樹脂封止型半導体装置
における半導体チップ２上の電極パッド３を当該チップ
の周辺に一列に配設したものである。これ以外の部分
は、実施例１と同様の構成になっている。この実施例２
の場合には、図７のように、ワイヤ７Ａ，７Ｂに高低差
を付けても良いし、図８のように、ワイヤ７Ａ，７Ｂに
高低差を付けなくても良い。As shown in FIG. 7, in the resin-encapsulated semiconductor device of the second embodiment, the electrode pads 3 on the semiconductor chip 2 in the resin-encapsulated semiconductor device of the first embodiment are arranged in a line around the chip. It is arranged in. The other parts have the same configuration as the first embodiment. Example 2
In this case, the height difference may be given to the wires 7A and 7B as shown in FIG. 7, or the height difference may not be given to the wires 7A and 7B as shown in FIG.
【００２７】以上、本発明を実施例に基づき具体的に説
明したが、本発明は、前記実施例に限定されるものでは
なく、その要旨を逸脱しない範囲において種々変更し得
ることはいうまでもない。Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various changes can be made without departing from the scope of the invention. Absent.
【００２８】[0028]
【発明の効果】以上、説明したように、本発明によれ
ば、長リ−ドのインナーリードの先端をモールド時のワ
イヤ流れに対応した所定の角度だけ曲げることにより、
モ−ルド流れでのワイヤとリ−ドのクロスを防止するこ
とができる。これにより、Ｘ線検査で良、不良の判定が
容易に行うことができる。As described above, according to the present invention, the tip of the long lead inner lead is bent by a predetermined angle corresponding to the wire flow during molding.
The crossing of the wire and the lead in the mold flow can be prevented. This makes it easy to determine good or bad in the X-ray inspection.
【図１】 本発明の実施例１である半導体装置のリ−ド
と半導体チップ上の電極パッドのレイアウトを示す平面
図、FIG. 1 is a plan view showing a lead of a semiconductor device according to a first embodiment of the present invention and a layout of electrode pads on a semiconductor chip;
【図２】 図１の要部断面図、FIG. 2 is a sectional view of a main part of FIG. 1,
【図３】 図１中、電極パッドの配設される周辺部を拡
大して示す部分平面図、FIG. 3 is an enlarged view of a peripheral portion where electrode pads are arranged in FIG. 1 ;
Partial plan view ,
【図４】 図１のリードの先端部の曲げ角度を説明する
ための図、[4] Figure of order <br/> was explaining the bending angle of the lead tip portion 1,
【図５】 図１に示す各ブロック毎の曲り率をグラフ化
した図、FIG. 5 is a graph showing a curvature rate of each block shown in FIG. 1;
【図６】 本発明の実施例１である半導体装置のレジン
モ−ルド後のＸ線検査の結果を示す模式図、FIG. 6 is a schematic diagram showing a result of an X-ray inspection after resin molding of the semiconductor device according to the first embodiment of the present invention ;
【図７】 本発明の実施例２である半導体装置の半導体
チップの周辺部に一列に配置された電極パッドと接続さ
れるワイヤに高低差をつけた場合を示す要部断面図、FIG. 7 is a diagram showing a semiconductor device according to a second embodiment of the present invention, which is connected to electrode pads arranged in a row around a semiconductor chip;
Main part sectional view showing a case where a height difference is given to a wire to be formed ,
【図８】 本発明の実施例２である半導体装置の半導体
チップの周辺部に一列に配置された電極パッドと接続さ
れるワイヤに高低差をつけない場合を示す要部断面図。FIG. 8 is a diagram showing a connection between electrode pads arranged in a row around a semiconductor chip of a semiconductor device according to a second embodiment of the present invention;
FIG. 6 is a cross-sectional view of a main part showing a case where a difference in height is not given to a wire to be formed .
１…タブ、２…半導体チップ、３（３Ａ，３Ｂ）…電極
パッド、４…長リード、４Ａ…長リードのインナーリー
ド、４Ａ1…長リードのインナーリード先端部、５…短
リード、５Ｂ…短リードインナーリード、６…タブ吊り
リード、７…ボンディングワイヤ、８…モールドレジン
（封止樹脂）、９…レージン流入ゲート、１０…レジン
流出ゲート、１１…スリット。1 ... tab, 2 ... semiconductor chip, 3 (3A, 3B) ... electrode pad, 4 ... long lead, 4A ... long lead of the inner lead, the inner lead tip portions of 4A 1 ... long lead, 5 ... short lead, 5B ... Short lead inner lead, 6: tab suspension lead, 7: bonding wire, 8: molded resin (sealing resin), 9: resin inflow gate, 10: resin outflow gate, 11: slit.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭61−154056（ＪＰ，Ａ) 特開 平３−27563（ＪＰ，Ａ) 実開 昭63−187352（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 23/50 H01L 23/28 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-154056 (JP, A) JP-A-3-27563 (JP, A) JP-A-63-187352 (JP, U) (58) Survey Field (Int.Cl. 6 , DB name) H01L 23/50 H01L 23/28
Claims (6)
ッドが形成され、前記複数の電極パッドと複数のインナ
ーリードとがボンディングワイヤにより夫々電気的に接
続され、封止樹脂によってモールドされた半導体装置で
あって、前記半導体装置には第１のインナーリードと、
前記第１のインナーリードに隣接し先端部が前記第１の
インナーリードよりも半導体チップから離間した第２の
インナーリードとが設けられ、前記第１のインナーリー
ドと前記第２のインナーリードの先端部は同じ高さに位
置し、前記第１のインナーリードと前記半導体チップの
一の電極パッドに接続されたワイヤの高さは前記第２の
インナーリードと前記半導体チップの他の電極パッドに
接続されたワイヤの高さよりも低く、前記第１のインナ
ーリードの先端部は、前記封止樹脂モールドの流れ方向
に曲げられていることを特徴とする半導体装置。A plurality of electrode pads are provided on a peripheral portion of a semiconductor chip.
A plurality of electrode pads and a plurality of inner pads.
-Leads are electrically connected to each other by bonding wires.
Semiconductor device molded with sealing resin
And the semiconductor device has a first inner lead;
The tip is adjacent to the first inner lead,
The second separated from the semiconductor chip than the inner lead
An inner lead, wherein the first inner lead is provided.
And the tip of the second inner lead are at the same height.
Between the first inner lead and the semiconductor chip.
The height of the wire connected to one electrode pad is the second height.
To the inner leads and other electrode pads of the semiconductor chip
Lower than the height of the connected wire, the first inner
-The tip of the lead is in the flow direction of the sealing resin mold.
A semiconductor device characterized by being bent .
は、前記半導体チップ周辺部に２列に設けられ、内側列
のパッドと外側列のパッドとは交互に配置されているこ
とを特徴とする請求項１に記載の半導体装置。2. A plurality of electrode pads on the semiconductor chip
Are provided in two rows around the semiconductor chip,
Pads and outer rows of pads should be staggered
The semiconductor device according to claim 1, wherein:
インナーリードに隣接する第３のインナーリードと、前
記第３のインナーリードに隣接する第４のインナーリー
ドとが設けられ、前記第３のインナーリードは先端部が
前記第２のインナーリードよりも前記半導体チップに近
接しており、前記第４のインナーリードは先端部が前記
第２のインナーリードと同程度前記半導体チップに近接
しており、前記第３のインナーリードは前記封止樹脂モ
ールドの流れ方向に曲げられていることを特徴とする請
求項１又は請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, further comprising:
A third inner lead adjacent to the inner lead;
The fourth inner lead adjacent to the third inner lead
And the third inner lead has a tip portion.
Closer to the semiconductor chip than the second inner leads
The fourth inner lead has a tip portion
As close to the semiconductor chip as the second inner lead
And the third inner lead is connected to the sealing resin module.
Characterized by being bent in the flow direction of the
The semiconductor device according to claim 1 or claim 2.
列の２列に交互に配置された電極パッドと、リードとが
ボンディングワイヤで電気的に接続された半導体装置で
あって、 前記リードは先端部の高さが一様で順次隣接する第１の
リードと第２のリードと第３のリードとを有し、前記第
１のリードよりも第２のリードの長さが短く、前記第２
のリードよりも第３のリードの長さが長く、前記第１の
リード及び第３のリードは、夫々樹脂封止によるワイヤ
流れに応じた角度にその先端部を曲げて 形成されている
ことを特徴とする半導体装置。 4. An inner row and an outer row at a peripheral portion on a semiconductor chip.
The electrode pads and the leads, which are alternately arranged in two rows, are
Semiconductor devices electrically connected by bonding wires
The first lead has a uniform height at the tip end and is adjacent to the first lead.
A lead, a second lead, and a third lead;
The length of the second lead is shorter than that of the first lead,
The length of the third lead is longer than that of the first lead,
Each of the lead and the third lead is a wire sealed with resin.
It is formed by bending its tip at an angle according to the flow
A semiconductor device characterized by the above-mentioned.
差を設けてボンディングされていることを特徴とする請
求項４に記載の半導体装置。 5. The bonding wire according to claim 1, wherein said bonding wire is alternately high and low.
Bonding characterized by being provided with a difference
The semiconductor device according to claim 4.
記半導体チップの周辺部に設けられた外側列の電極パッ
ドと電気的に接続されていることを特徴とする請求項４
又は請求項５に記載の半導体装置。Wherein said first lead and the third lead claims, characterized in that it is connected the semiconductor chips and electrically the electrode pads of the outer side row provided in the peripheral portion 4
Or the semiconductor device according to claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4070872A JP2987251B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4070872A JP2987251B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05275596A JPH05275596A (en) | 1993-10-22 |
| JP2987251B2 true JP2987251B2 (en) | 1999-12-06 |
Family
ID=13444085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4070872A Expired - Fee Related JP2987251B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2987251B2 (en) |
-
1992
- 1992-03-27 JP JP4070872A patent/JP2987251B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05275596A (en) | 1993-10-22 |
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