JP2986570B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device such as an EPROM, and more particularly to a circuit for rewriting a defective address storage element of a redundant circuit. Semiconductor storage devices are being developed at an intense pitch where the storage capacity is quadrupled in three years. EPROM is no exception, and recently 4-Mbit products have appeared. With the increase in storage capacity, the chip size has also increased. For this reason, in order to obtain a stable yield, a redundant configuration is essential.

A redundant word / bit line is used in place of a defective word line and / or a defective bit line of a cell array. The address of the defective word / bit line is stored, and the memory access becomes a defective word / bit line. Then, it is known by address comparison, and a redundant word / bit line is used instead of a defective word / bit line. Therefore, if a defective word / bit line occurs within the number of redundant word / bit lines, the memory chip can be made non-defective and the production yield can be improved. The present invention relates to a circuit for rewriting a storage element having a defective address.

[0003]

2. Description of the Related Art FIG. 3 shows a memory cell of an EPROM.
As shown, the memory cell of the EPROM has one MOS transistor.
A transistor (hereinafter referred to as a memory cell transistor). 1 is a P-type silicon (Si) substrate, 2 is FG
(Floating gate), 3 is a CG (control gate) capacitively coupled to FG2, and 4 and 5 are N-type regions, which function as a source or a drain.

The operation of this memory cell transistor is as follows. When the ultraviolet rays are irradiated, the charge escapes from the FG2, and the charge of the FG becomes zero. When an appropriate voltage is applied to CG3 in this state, the transistor is turned on. C
When a high voltage is applied to G3 and the drain, avalanche breakdown occurs, a large number of high-energy electrons and holes are generated near the drain, and a part of the high-energy electrons is F
G2 is trapped, and a negative charge is accumulated in the FG. Then, even if a voltage is applied to CG3, the transistor does not conduct. That is, the ultraviolet irradiation changes the memory cell transistor of the EPROM from a non-conductive state to a conductive state. This is called erasure. The avalanche breakdown causes the memory cells and transistors to change from a conductive state to a non-conductive state. This is called a program.

FIG. 4 shows the structure of an EPROM. EPRO
In M, memory cell transistors MC are arranged in rows and columns. The CGs of the memory cell transistors in each row are connected in common, and the row lines WL (subscripts ₀ , _1, ...
Is omitted as appropriate. Others are the same). The drains of the memory cell transistors in each column are connected in common, and the column line BL
Becomes Row decoder W receiving row address and column address
One row line WL and one column line BL are selected by D and the column decoder CD, and the memory cell transistor MC located at the intersection thereof is selected. The sense amplifier SA detects the conduction / non-conduction of the selected memory cell transistor and outputs it to the outside.

FIG. 5 shows an example of a redundant configuration in an EPROM. In EPROM, any one of the row address input to a corresponding row line (WL ₀ ~WL _n) is selected by the row decoder WD. If the row address input is N bits, there are 2 ^N row lines. If there is a defect in a certain row line WL _X, the semiconductor device becomes a defective operation, stores the row address of the row lines WL _X in the defective address storage ROM 10, a comparator C
The operation is compared with the address input by OMP, and when they match, the match signal φ is output to inhibit the operation of the row decoder WD, and if the spare row line WL _R is selected instead, no operation failure occurs. WL _R in FIG. 4 shows this spare row line. The defective address storage ROM of the EPROM may use a memory cell transistor (UPROM) which is entirely covered with aluminum (Al) and cannot be erased by ultraviolet rays (known example:
Patent No. 152015).

[0007] The completed EPROM wafer is tested (wafer test). At this time, the defective chip is repaired by redundancy, and becomes a good chip. that time,
The defective address is stored in the UPROM (other storage elements include a fuse of polycrystalline silicon, an aluminum wire, and the like, and these are stored by laser cutting / non-cutting addresses). After the wafer test, the wafer is cut into chips. Then, the good chip is assembled into a package.
Usually, the EPROM is housed in a ceramic package.
This package is divided into a base part and a lid part.
The PROM chip is mounted on the base, and a lid provided with an ultraviolet transmission window is put on the cover. The butted portion is bonded with a low melting point glass to be integrated.
As a result, the UPROM in the package is exposed to the high temperature of about 400 degrees C.
Electrons in the floating gate of M obtain thermal energy and a part of them escapes. In this case, reading is not performed at a normal read voltage (all elements are turned on), and a defective address cannot be obtained. Therefore, when the assembly is completed, a shipping test is performed. At this time, the UPROM programmed in the wafer test must be reprogrammed.

FIG. 6 shows a conventional defective address storage UPRO.
3 shows an M circuit. This is one bit, and 20 is the UPR
An OM program control circuit 30 is a UPROM state detection circuit. The VPC is a power supply that becomes a high voltage such as 12.5 V during programming and 5 V during normal operation.
The control circuit 20 includes an inverter I ₁ receiving the redundant program signal RPGM, a NOR gate G ₁ receiving its output and the address signal A, an inverter I ₂ inverting its output, N-type transistors Q ₆ , Q ₄ , P A level conversion circuit composed of the type transistors Q ₅ and Q ₃ , and an N-type transistor Q ₂ which operates upon receiving a signal from the level conversion circuit. Which is connected between the power source UPROM Q ₁ series.

The detection circuit 30 includes P-type transistors Q ₇ and U ₇
An inverter composed of a PROM Q _1, consisting of an inverter I ₃ for inverting its output. RA is one bit of the defective address. If the defective address is n bits, n such circuits are provided. In order to store a defective address in the UPROM, VPC is set to a high voltage and RPGM is set to logic H. If the address input A is logic H, NO
The output of the R gate G ₁ is L, the output of the inverter I ₂ is H,
Conducting transistor Q ₃ are turned off, the output of the CMOS inverter Q ₄ are in ON L, thus the transistor Q ₂ is turned off, no voltage is supplied to the drain of the UPROM Q _1, since the electron injection is not into FG Keep state. If contrary to the address input A is logic L to this, the transistor Q ₂ is turned on, the drain of the UPROM Q ₁ high voltage is applied, therefore programmed in the non-conducting state. Normally, since the RPGM is logic L, the NOR gate G
The output of ₁ L, the output of the inverter I ₂ is H, the output of the CMOS inverter Q _3, Q ₄ is L, and thus the transistor Q ₂ is turned off, the control circuit 20 and UPROMQ ₁ is disconnected.

Normally, VPC is 5V. Detection circuit 3
The 0, UPROM Q ₁ is defective address signal RA if non-conductive is a logic H is logic L, conduction. Incidentally transistor Q ₅ of the control circuit 20 is turned on when the output of the CMOS inverter Q _3, Q ₄ turns off the transistor Q ₂ with L, and H input of the CMOS inverter to ensure the operation Te pulling the VPC Is what you do.

[0011]

The writing of the defective address into the UPROM is performed at the time of the wafer test.
With high temperature processing of several tens of degrees Celsius at the time of EPROM assembly,
Some electrons escape from the floating gate of the UPROM. Then, when a normal read voltage of 5 V is applied to the UPROM control gate programmed in the wafer test after the assembly, all of them become conductive. In this case, the defective address cannot be read, and the defective word / bit line cannot be relieved. Therefore, an additional program (rewrite) to the UPROM is required in the shipping test.

A part of the electrons in the floating gate of the UPROM escapes by the high-temperature treatment, but not all of them escape. Therefore, the data is written in a thin state, and the data can be read by lowering the read voltage, for example, by changing the normal 5V to 3V. Therefore, conventionally, a power supply of 3 V
The address is changed from address 0 to the final address (scan). The comparator outputs a match signal when the address reaches the defective address.
Thus, the UPROM is additionally programmed (writing the defective address). However, this takes a particularly long time for the address scan in the shipping test, and therefore, a method of additionally programming the UPROM without performing this scan is required. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a circuit that enables high-speed rewriting of a defective address to an UPROM.

[0013]

FIG. 1 shows a rewriting circuit according to the present invention. As in all figures, the same parts as in the other figures have the same reference numerals. As is apparent from comparison with FIG. 6, in the present invention, the state detection circuit 30 of the UPROM is used.
, The provision of the latch circuit Q ₁₁ to Q ₁₄ of the storage data of the read UPROM cells Q _1. Also in the program control circuit 20 of the UPROM, providing the gate G ₂ for taking in the output RA of the state detection circuit 30 (defective address).

[0014]

According to the present invention, in rewriting, the UPROM is read with a low power supply voltage, and the UROM is read with the obtained defective address.
So that re-write the PROM, but read defective address is latched in the latch Q ₁₁ to Q _14. Then, this is input to the program control circuit 20, and the power supply voltage VPC is raised to the write voltage and written to the UPROM cell. According to this method, all of the n-bit defective addresses can be rewritten by two operations of reading and writing, and the required time is much longer than that of the conventional method that requires detection of defective addresses by address scanning. Can be shortened.

[0015]

FIG. 1 is described in detail. The control circuit 20 has an address input A and an output RA (defective address signal) of the detection circuit (30).
, And a NAND gate G ₃ receiving the output of the NAND gate G ₂ and the redundant program signal RPGM,
N-type transistors Q ₆ and Q ₄ , P-type transistors Q ₅ ,
Level conversion circuit composed of Q _3, consisting of the N-type transistor Q ₂ to which operates by receiving a signal of the level converting circuit.

The detection circuit 30 has a redundancy program signal RPG
It comprises an N-type transistor Q ₁₅ controlled by an inverter I ₄ for inverting M, a flip-flop composed of P-type transistors Q ₁₁ and Q ₁₃ and N-type transistors Q ₁₂ and Q ₁₄ , and capacitors C ₁ and C _2. . The first has a defective address signal RA is logic H (in the non-write state) UPROM Q ₁ is in conductive state. This is RP
When GM = L, the output of I ₄ is H, Q _{15 is} on, so if Q _{1 is} on, it depends on Q ₁₃ on and Q ₁₄ off. Gate G if RA = H
₂ is open.

[0017] In order to store the defective address in the UPROM Q ₁ is a VPC to a high voltage, a logic and RPGM H
To Address input A (this is one bit of the address of the defective word / bit line obtained in the wafer test) is logic H
Then, the output of G ₂ is L, the output of G ₃ is H, and the CMOS
The output L of the inverters Q ₃ and Q ₄ , and therefore Q ₂ is off. If the transistor Q ₂ is off, UPROM Q
_No voltage is supplied to the drain of ₁ and writing is not performed, so that the conduction state is maintained. If the address input A is logic L, the output of G ₂ is H, the output of the G ₃ are L, the output of the CMOS inverter Q _3, Q ₄ transistor Q ₂ is turned on by H, the drain of the UPROM Q ₁ is A high voltage is applied, programmed, and turned off. Normally RP
GM logic L since the output of the G ₃ are H, the output of the CMOS inverter Q _3, Q ₄ is L, the transistor 18 is off,
Control circuit 20 and the UPROM Q ₁ is disconnected.

The additional program is as follows. The power supply voltage VPC is set to about 3V. Then the programmed U
PROM Q ₁ is non-conducting state, unprogrammed (electron injection is not performed) UPROM becomes conductive.
When the power is turned on, the flip-flop is set by the capacitors C ₁ and C ₂ so that the output RA becomes logic L.
If UPROM Q ₁ is conductive, the flip-flop RA is a logic H inverted eventually. If it is not conducting, the logic L is maintained. This read UPROM Q _1, latch the storage data. Then (Open gate G ₂₎ to the address input A to logic H, the VPC to 12.5 V, the RPGM logical H. Detection circuit 3
The 0 in the transistor Q ₁₅ and the UPROM Q ₁ and the detection circuit 30 is disconnected. If UPROM Q ₁ is conductive state, RA is because the logic H, the output of G ₂ is the control circuit 20 L, the output of the G ₃ are H, the output of the CMOS inverter Q _3, Q ₄ is L, so that transistor Q ₂ Is turned off and no additional programs are made. UPROM
If Q ₁ is non-conductive RA is because logic L, transistor Q ₂ is turned on, additional program is made to UPROM Q _1.

By the way, in the conventional FIG. 6, the UPROM Q ₁
And an inverter composed of a P-type transistor Q ₇
For conductive state PROM Q _1, it has the disadvantage that constantly flowing current. However, in Figure 1, so to latch the state of the UPROM Q ₁ by the flip-flop Q ₁₁ to Q ₁₄ of a CMOS structure, Such drawbacks are overcome.

FIG. 2 shows another embodiment of the detection circuit 30 of FIG. Also in this figure, the same components as those in the other drawings are given the same reference numerals. In FIG. 2A, the state of the flip-flop at power-on is determined by a power-on detection pulse RESE.
Performed by T. RESET signal is several tens when power is turned on.
This is a signal that maintains logic H for about 0 μs and then becomes logic L. A circuit for generating such a pulse is known (Japanese Patent Application No. 63-060214). The RESET signal is output from the inverter I
Is inverted by _5, it is applied to the gate of the P-type transistor Q _16. Thus, the transistor Q ₁₆ is turned on only after the power is turned on. If UPROM Q ₁ is conductive, the drain of the transistor Q ₁₆ falls to near 0V, rises to the power supply voltage close as long as it is a non-conductive state. RA is H in the former case and L in the latter case. Thus initialization of the flip-flop formed by the transistors Q ₁₁ to Q ₁₄ is made.

FIG. 2B shows the RES in FIG. 2A.
This eliminates the need for the ET signal. In FIG. 2B, R
Transistor Q receiving inverted signal of PGM signal
_{At 15} , a RESET signal is applied. If you do this, UPRO
UPROM only immediately after the power is turned on to detect the state of the M Q ₁
Q ₁ and the detection circuit 30 are connected, and thereafter disconnected.

In order to set the flip-flops Q _{11 to} Q ₁₄ to a certain state when the power is turned on, the flip-flops may be configured as shown in FIG. In this figure, the transistors Q _{21 to} Q ₂₄ constituting the flip-flop are all N-channel MOS FETs, but Q ₂₁ is a depletion type.
Q ₂₂ ~Q ₂₄ is an enhancement type. On power up Q ₂₁ whereas immediately become ON, Q ₂₃ is not turned on until the supply voltage becomes equal to or higher than the threshold voltage. Therefore Q ₂₄
On, in the Q ₂₂ off, RA will be L. However, in this circuit, a current always flows, and the power consumption cannot be reduced as in the case of using CMOS.

[0023]

As described above, according to the present invention, U
The rewriting of the defective address to the PROM can be performed very simply, quickly and automatically, which is extremely effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram showing another example of each unit in FIG. 1;

FIG. 3 is an explanatory diagram of an EPROM cell.

FIG. 4 is a circuit diagram showing a configuration of an EPROM.

FIG. 5 is a block diagram illustrating a configuration of a redundant circuit.

FIG. 6 is a circuit diagram of a conventional defective address storage circuit.

[Explanation of symbols]

20 UPROM program control circuit 30 UPROM state detecting circuit Q ₁₁ to Q ₁₄ latch circuit Q ₁ UPROM cell (first switching element) Q ₁₅ second switching element

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hirokazu Yamazaki 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Masaya Kokubo 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu VSI Co., Ltd. In-company (72) Inventor Koichi Maeda 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-63-283000 (JP, A) (58) Fields investigated (Int. Cl. ^6, DB name) G11C 29/00 G11C 16/06

Claims (4)

(57) [Claims] 1. A nonvolatile first switching element (Q ₁ ) that can be set to an electrically conductive / non-conductive state and a state of the first switching element for redundancy control of a semiconductor memory device. a control circuit for (20), a latch circuit for detecting and storing the state of the first switching element (Q ₁₁ to Q _14), a second switching element connecting the first switching element and said latch circuit ( Q ₁₅ ) and a state detection circuit (3) having means (RPGM) for controlling the second switching element.
0), wherein the first switching element is connected to the latch circuit via the second switching element, and the second switching element is non-conductive when the state of the first switching element is set, and is conductive during normal operation. The latch circuit outputs a logic L if the state of the first switching element is non-conductive, and outputs a logic H if the state of the first switching element is conductive. When the state of the element is set, it operates according to the logic of the address input and the output of the latch circuit. When the address input is logic L, the first switching element is set to the non-conductive state regardless of the output of the latch circuit. If the address input is logic H, the first switching element is set to be kept conductive if it is conductive, and set to be further nonconductive if it is nonconductive. Wherein, the semiconductor memory device. 2. A nonvolatile first switching element (Q ₁ ) that can be set to an electrically conductive / non-conductive state and a state setting of the first switching element for redundancy control of a semiconductor memory device. a control circuit for (20), a latch circuit for detecting and storing the state of the first switching element (Q ₁₁ to Q _14), a second switching element connecting the first switching element and said latch circuit ( Q ₁₅ ) and a state detection circuit (3) having means (RPGM) for controlling the second switching element.
0), wherein the first switching element is connected to the latch circuit via the second switching element, and the second switching element is non-conductive when the state of the first switching element is set, and is conductive during normal operation. The latch circuit outputs a logic L if the state of the first switching element is non-conductive, and outputs a logic H if the state of the first switching element is conductive. When the state of the element is set, it operates according to the logic of the address input and the output of the latch circuit. When the address input is logic L, the first switching element is set to the non-conductive state regardless of the output of the latch circuit. If the address input is logic H, the first switching element is set to be kept conductive if it is conductive, and set to be further nonconductive if it is nonconductive. A semiconductor memory according to a first feature, wherein the latch circuit does not consume power in a steady state, and does not consume power in a steady state regardless of a state of the first switching element. apparatus. 3. A nonvolatile first switching element (Q ₁ ) that can be set to an electrically conductive / non-conductive state and a state of the first switching element for redundancy control of the semiconductor memory device. a control circuit for (20), a latch circuit for detecting and storing the state of the first switching element (Q ₁₁ to Q _14), a second switching element connecting the first switching element and said latch circuit ( Q ₁₅ ) and the pulse from the means for controlling the second switching element (RPGM) and the means for detecting the power-on and generating a pulse (RESET) are turned on temporarily to initialize the latch circuit. A state detection circuit (30) having a third switching element (Q ₁₆ ), wherein the first switching element is connected to the latch circuit via a second switching element, and a second switch The switching element is controlled so as to be non-conductive when the state of the first switching element is set, and to be conductive during normal operation. The latch circuit operates when the power-on pulse (RES) is turned on.
ET), the state of the first switching element is set to output a logical L if the state is non-conductive, and set to output a logical H if the state of the first switching element is conductive. When setting the state of the switching element, it operates according to the logic of the address input and the output of the latch circuit. When the address input is logic L, the first switching element is in the non-conductive state regardless of the output of the latch circuit. If the address input is logic H, the first switching element is set to be kept conductive if it is conductive, and set to be further nonconductive if it is nonconductive. Semiconductor storage device. 4. A nonvolatile first switching element (Q ₁ ) that can be set to an electrically conductive / non-conductive state and a state setting of the first switching element for redundancy control of the semiconductor memory device. a control circuit for (20), a latch circuit for detecting and storing the state of the first switching element (Q ₁₁ to Q _14), a second switching element connecting the first switching element and said latch circuit ( Q ₁₅ ) and the pulse from the means for controlling the second switching element (RPGM) and the means for detecting the power-on and generating a pulse (RESET) are turned on temporarily to initialize the latch circuit. A state detection circuit (30) having a third switching element (Q ₁₆ ), wherein the first switching element is connected to the latch circuit via a second switching element, and a second switch The latching element is controlled by the pulse to be conductive when the power is turned on and to be non-conductive in a steady state.
Is set to output a logic L if the state of the switching element is non-conductive, and set to output a logic H if the state of the switching element is conductive, the control circuit sets the state of the first switching element When the address input is logic L, the first switching element is set to a non-conducting state regardless of the output of the latch circuit when the address input is logic L, A semiconductor memory device characterized by being set so as to maintain a conductive state if the first switching element is in a conductive state if it is a logical H, and further to a non-conductive state if the first switching element is in a non-conductive state.