KR20000012893A - Repair circuit of dynamic random access memory - Google Patents

Abstract

PURPOSE: A repair circuit of a DRAM(Dynamic Random Access Memory) is provided to repair a defect cell and change the repaired state in a packaging process by using a non-volatile flash memory. CONSTITUTION: The repair circuit comprises: a fuse box(20) composed of MOS(Metal Oxide Semiconductor) transistors(24) instead of repair fuses; a flash memory cell array(60) storing information for controlling the MOS transistors of the fuse box(20); a decoding element(70) for writing or erasing data in the flash memory cell array(60) corresponding to an input address from an address input buffer(80) of the DRAM; a reading element(50) for reading information written in the flash memory cell array(60); a latching element(40) for latching information read by the reading element(50); and a sensing element(30) for operating the MOS transistors of the fuse box(20) by sensing an output of the latching element(40).

Description

DRMA repair circuit

The present invention relates to a repair circuit of a DRAM, and more particularly, a repair can be performed at a package stage by using a nonvolatile flash memory instead of a repair fuse that replaces a redundancy circuit when a defect occurs during DRAM production. To one of the DRAM repair circuits.

In a semiconductor memory device including a dynamic random access memory (DRAM), a redundancy circuit is provided to improve a yield by replacing a defective memory cell with a redundant memory cell when a small amount of the memory cell is defective. Adopt the method.

As the redundancy circuit is installed, the area of the chip increases and the test required for defect repair is a problem. However, since the area of the chip does not increase much in DRAM, it has been adopted from 64K to 256K DRAM in earnest.

Redundancy circuits of memory cells are installed for each sub-array block, and spare ROW and COLUMN are installed in advance, and defects are generated so that defective memory cells are replaced with redundancy memory cells by ROW / COLUMN units.

1 is a block diagram illustrating a repair circuit of a DRAM according to a conventional embodiment.

As shown here, a repair fuse is disposed around the block of the cell array 10 of the DRAM, and there is an extra redundancy cell 12 within the block of the cell array 10.

When the wafer processor is terminated, the test selects a bad memory cell and stores the corresponding bad address in the test equipment. Then, when the test is finished, the repair fuse 22 corresponding to the bad address is blown using the laser repair equipment. In this case, even if an attempt is made to access a defective cell from the outside, the redundant cell 12 is accessed from the inside, so that the address of the defective bit is normally operated.

Such programming methods include an electric fuse method that melts and blows a fuse due to overcurrent, a method of generating a fuse with a laser beam, and a method of shorting a junction with a laser beam. Among these methods, the laser cutting method is widely used because of its simple, reliable and easy layout.

The repair circuit of a DRAM which takes such a program method has the following problems. First, repairing is only possible at the wafer level, so repair is not possible at the package stage. In addition to the current problem, as DRAM becomes more integrated and faster, the test rate in a packaged state is increasing.

Second, if a repair is wrong, it cannot be recovered again. The repair fuse melts through the energy of the laser and can not be rejoined.

Third, it will not be repaired at the same time as the test. After the test is finished, the repair equipment is used, which adds a process for repair, and the laser equipment for repair is expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to use a nonvolatile flash memory to replace a repair circuit that replaces a redundant cell when a defective cell occurs during a test of a DRAM. It can be repaired at the package level by programming accordingly, and it provides a repair circuit of DRAM that can modify the repair state.

1 is a block diagram illustrating a repair circuit of a DRAM according to a conventional embodiment.

2 is a block diagram illustrating a repair circuit of a DRAM according to an exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating only one cell state in the repair circuit of FIG. 2.

-Explanation of symbols for the main parts of the drawings-

20,20 ': Fuse box

24: repair fuse

30: detector

40: latch portion

50: reading part

60: flash memory cell array

70: decoding unit

In order to achieve the above object, the present invention relates to a repair circuit of a DRAM in which a defective circuit is replaced with a redundancy circuit by cutting a repair fuse in a fuse box made of a repair fuse, a fuse box made of a MOS transistor instead of a repair fuse, and a fuse. A flash memory cell array in which information for interrupting a box MOS transistor is stored, a decoding unit for writing or erasing data into a flash memory cell array corresponding to an address input from an address input buffer of a DRAM, and a flash memory cell array. A readout unit for reading the recorded information, a latch unit for continuously holding the data read by the reader unit, and a sensing unit for sensing the output value of the latch unit and operating the MOS transistor of the fuse box according to the value.

Referring to the operation of the repair circuit of the DRAM made as described above is as follows.

If a defect occurs through a test after the wafer process is terminated, the decoding unit writes or erases the flash memory cell array and stores the information according to the address where the defect occurs. The stored value keeps this value in the latch part when the read part reads the value stored in the flash memory cell array. In this way, the detected value is detected by the detector to operate the MOS transistor in the fuse box to repair the defective memory cell to the redundancy cell.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2 is a block diagram illustrating a repair circuit of a DRAM according to an exemplary embodiment of the present invention.

As shown here, instead of the repair fuse (22 in FIG. 1) of the repair circuit of the DRAM, the fuse box 20 made up of the MOS transistor 24 and the MOS transistor 24 of the fuse box 20 may be intermittent. A flash memory cell array 60 in which information is stored, a decoding unit 70 for writing or erasing data to and from a flash memory cell array 60 corresponding to an address input from an address input buffer 80 of a DRAM, and a flash. A read unit 50 for reading information written in the memory cell array 60, a latch unit 40 for continuously holding data read by the read unit 50, and an output value of the latch unit 40 are sensed. It further comprises a sensing unit 30 for operating the MOS transistor 24 of the fuse box 20 according to this value.

The MOS transistor 24 of the fuse box 20 is connected to the position where the repair fuse 22 inserted by the energy of the laser is inserted into the NMOS transistors 24 and the signal of the sensing unit 30 applied to the gate. In accordance with the on / off state, when the repair fuse 22 is turned off, the same operation is performed. When the switch is turned off, the repair fuse 22 performs the same operation as the cut state.

FIG. 3 is a circuit diagram illustrating the operation of one cell in FIG. 2.

As shown here, the decoding unit 70 for storing charge in the floating gate G of the flash memory cell 62 includes a drain switch 72, a source switch 74, and a gate switch 76. Is done.

Table 1 shows the output values of the drain switch 72, the source switch 74, and the gate switch 76 of the decoding unit 70.

gate drain Source Record state 9 V 5 V 0 V Erased state -9V floating 5 V Steady state floating floating 5 V

The values in Table 1 are the voltages applied when data is written or erased to the flash memory cell 62, and are output from the drain in D when the power supply voltage is applied to the gate G in the normal state, that is, in the read mode. By reading the value, the data stored in the flash memory cell 62 can be read.

The read unit 50 is operated to cut an input and an output after reading data stored in the flash memory cell 62, so that the readout unit 50 intercepts the read signal R applied to the gate G. 52, the second NMOS 54 for intermittent the output of the drain-in D, the delay circuit 56 for delaying the read signal R for a predetermined time, and the value output from the delay circuit 56 are inverted. And an inverter 58 which is applied to the gate G of the first NMOS 52 and the second NMOS 54.

Referring to the operation of the present embodiment made as described above are as follows.

If a defect has not occurred as a result of testing the DRAM, it is not set to the repair mode, and the switching transistor 82 is turned off to input an address stored in the input buffer to the decoder of the normal DRAM.

However, in the event that a defect occurs as a result of testing the DRAM, the switching transistor 82 is turned on to accept the value of the address input buffer 80 so that the repair can be performed according to the address inputted to the address pin of the DRAM. Data can be stored in the memory cell 62.

When the decoding unit 70 is in the write state according to the input address as described above, the flash memory cell 62 is operated by operating the drain switch 72, the source switch 74, and the gate switch 76 as shown in Table 1. The charge is stored in the floating gate (G) of the to increase the threshold voltage. In addition, even in the erased state, a voltage is applied to the flash memory cell 62 according to the erased state shown in Table 1 to set the threshold voltage to be low.

As described above, the flash memory cell array 60 stores an address for replacing a defective memory cell with a redundancy cell.

When the value of the reading unit 50 rises from the low voltage to the high voltage, the first NMOS 52 and the second NMOS 54 of the reading unit 50 are turned on in the low voltage state. . Then, a power supply voltage is applied to the gate G of the flash memory cell 62. At this time, when data is written to the flash memory cell 62, the threshold voltage is high, and thus the power supply voltage does not turn on, so that the voltage applied to the source S does not flow to the drenin D in the normal state.

Therefore, the output value of the drenin D becomes low potential. This value is maintained by the latch unit 40 and the read signal R of the read unit 50 is delayed by the delay circuit 56 so that the high potential is converted to the low potential via the inverter 58. The 1,2NMOS 52 and 54 are turned off so that the drain value is not output.

The output value of the latch unit 40 is applied to the gate G of the NMOS transistor 24 in the fuse box 20 by the low potential value sensed by the detector 30 to turn off the NMOS transistor 24 to repair the fuse. Keep the cutting state of 22).

On the other hand, when the flash memory cell 62 is erased, the high potential applied to the source S is turned on when the read signal R is applied to the drone in D. The high potential value is maintained by the latch unit 40 and the sensing unit 30 which senses this value is turned on by operating the NMOS transistor 24 so that the repair fuse 22 remains uncut. .

As described above, the present invention replaces the fuse box of the repair fuse with the fuse box of the MOS transistor and stores the data for operating the MOS transistor in the flash memory, thereby repairing the repair by changing the data written to the flash memory in the package step. There is an advantage that it can be done.

In addition, by controlling the on / off of the MOS transistor by the data written in the flash memory, there is an advantage that it can be easily changed even if the repair is made wrong.

In addition, since the repair is performed using the MOS transistor and the flash memory, there is an advantage that the cost can be reduced without using expensive repair equipment used when cutting the repair fuse with the energy of the laser.

Claims (3)

In a repair circuit of a DRAM in which a defective circuit is replaced with a redundancy circuit by cutting a repair fuse into a fuse box formed of a repair fuse, Fuse box made of MOS transistor instead of repair fuse, A flash memory cell array in which information for interrupting a MOS transistor of a fuse box is stored; A decoding unit for writing or erasing data in a flash memory cell array corresponding to an address input from an address input buffer of a DRAM; A readout unit for reading information written in the flash memory cell array; A latch unit for continuously holding data read by the reading unit; Sensing part that senses the output value of the latch part and operates the MOS transistor of the fuse box according to this value. Repair circuit of a DRAM, characterized in that further comprises. The method of claim 1, wherein the decoding unit A drain switch for applying a voltage to the drain of the flash memory cell; A gate switch for applying a voltage to the gate of the flash memory cell; Source switch applying voltage to the source of the flash memory cell Repair circuit of a DRAM, characterized in that consisting of. The method of claim 1, wherein the reading unit A first NMOS for intermittent read signals; A second NMOS for controlling an output of the flash memory, A delay circuit for delaying the read signal for a predetermined time; Inverter that inverts delay circuit and operates first NMOS and second NMOS Repair circuit of a DRAM, characterized in that consisting of.