JP2985815B2 - Constant voltage circuit and DA conversion circuit using the same - Google Patents
Constant voltage circuit and DA conversion circuit using the sameInfo
- Publication number
- JP2985815B2 JP2985815B2 JP9014280A JP1428097A JP2985815B2 JP 2985815 B2 JP2985815 B2 JP 2985815B2 JP 9014280 A JP9014280 A JP 9014280A JP 1428097 A JP1428097 A JP 1428097A JP 2985815 B2 JP2985815 B2 JP 2985815B2
- Authority
- JP
- Japan
- Prior art keywords
- constant voltage
- value
- input
- voltage circuit
- linear amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Analogue/Digital Conversion (AREA)
- Logic Circuits (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は抵抗で電圧を分圧し
て定電圧を得る定電圧回路に関し、特に抵抗を可変抵抗
と固定抵抗とで構成し、可変抵抗の制御を、2つの増幅
器と、これらの出力を比較する比較器とで制御するよう
にした定電圧回路及び、この定電圧回路の特性を利用し
たDA(デジタル・アナログ)変換回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage circuit for dividing a voltage by a resistor to obtain a constant voltage, and more particularly to a constant voltage circuit having a variable resistor and a fixed resistor. The present invention relates to a constant voltage circuit controlled by a comparator for comparing these outputs and a DA (digital / analog) conversion circuit utilizing characteristics of the constant voltage circuit.
【0002】[0002]
【従来の技術】従来の定電圧回路の例として、特開平6
−175742号公報にあるような基準電圧発生回路が
ある。この基準電圧発生回路は、トランジスタのベース
・エミッタ間電圧をもとにして基準電圧を発生するよう
にしている。2. Description of the Related Art An example of a conventional constant voltage circuit is disclosed in
There is a reference voltage generation circuit as disclosed in Japanese Patent Publication No. 175742/1995. This reference voltage generation circuit generates a reference voltage based on the voltage between the base and the emitter of the transistor.
【0003】また、他の例として、ロバート.A.ピー
ズ氏の文献(IEEE1990、BCTM 9.3の2
14ページから218ページ)にあるようなバンドギャ
ップ電圧をもとにして、基準電圧を発生するようにして
いるものがある。As another example, Robert. A. Peas's document (IEEE 1990, BCTM 9.3-2)
In some cases, a reference voltage is generated based on a bandgap voltage as shown in pages 14 to 218).
【0004】[0004]
【発明が解決しようとする課題】この従来の定電圧回路
は、ベース・エミッタ間電圧や、バンドギャップ電圧な
ど、トランジスタ素子の特性をもとに基準電圧を発生す
るので、トランジスタの特性を所要のものにするため、
その製造プロセスを細かく制御することが必要で、ま
た、製造プロセスのばらつきや、出来上がったトランジ
スタのばらつきの影響を、特にCMOSプロセスを使用
する場合には、受けやすいという欠点があった。In this conventional constant voltage circuit, a reference voltage is generated based on characteristics of a transistor element such as a base-emitter voltage and a band gap voltage. To make things
There is a disadvantage that the manufacturing process needs to be finely controlled, and that it is easily affected by variations in the manufacturing process and variations in completed transistors, particularly when a CMOS process is used.
【0005】[0005]
【課題を解決するための手段】前記の欠点を解消するた
め、本発明の定電圧回路は、可変抵抗要素と固定抵抗要
素とで電圧を分圧して定電圧出力を得るようにした定電
圧回路において、前記定電圧出力信号を共通の入力とす
る2つの増幅器と、これら増幅器の出力を比較入力とす
る比較器とを備え、前記比較器の出力により、前記可変
抵抗要素の抵抗値を可変制御するように構成し、所要の
定電圧値を境界入力値として、前記2つの増幅器の増幅
出力の大小関係が、反転するようにした。SUMMARY OF THE INVENTION In order to solve the above-mentioned drawbacks, a constant voltage circuit according to the present invention is configured to obtain a constant voltage output by dividing a voltage between a variable resistance element and a fixed resistance element. And two comparators having the constant voltage output signal as a common input, and a comparator having the output of the amplifier as a comparison input. And the magnitude relationship between the amplified outputs of the two amplifiers is inverted with the required constant voltage value as the boundary input value.
【0006】また、2つの増幅器の内、一方を線形増幅
器、他方を非線形増幅器で構成し、各々の増幅特性曲線
が一点で交わる入力電圧値を、所要の定電圧値とするよ
うにした。Further, one of the two amplifiers is constituted by a linear amplifier and the other is constituted by a non-linear amplifier, and an input voltage value at which each amplification characteristic curve intersects at one point is set to a required constant voltage value.
【0007】また、2つの増幅器の内、一方を線形増幅
器、他方を非線形増幅器で構成し、前記線形増幅器の増
幅特性を可変制御することにより、各々の増幅特性曲線
が一点で交わる入力電圧値を、所要の定電圧値とするよ
うにした。Further, of the two amplifiers, one is constituted by a linear amplifier and the other is constituted by a non-linear amplifier, and the amplification characteristic of the linear amplifier is variably controlled so that the input voltage value at which each amplification characteristic curve intersects at one point is obtained. And the required constant voltage value.
【0008】また、可変抵抗要素が、MOSトランジス
タで構成され、ソース・ドレイン間の抵抗値を、ゲート
入力電圧で制御することにより、その抵抗値を可変制御
するようにした。The variable resistance element is constituted by a MOS transistor, and the resistance between the source and the drain is controlled by the gate input voltage, so that the resistance is variably controlled.
【0009】また、前記固定抵抗要素の定電圧出力端側
から、可変抵抗要素と並列に、別の固定抵抗要素を接続
して電圧の分圧回路を構成するようにした。Further, another fixed resistance element is connected in parallel with the variable resistance element from the constant voltage output terminal side of the fixed resistance element to form a voltage dividing circuit.
【0010】さらにまた、これらの定電圧回路における
デジタル値入力と定電圧回路出力との関係を、デジタル
・アナログ(DA)変換に利用するようにしてDA変換
回路とした。Further, the relationship between the digital value input and the constant voltage circuit output in these constant voltage circuits is used for digital-to-analog (DA) conversion to form a DA conversion circuit.
【0011】[0011]
【発明の実施の形態】本発明の第1の実施の形態につい
て、以下に図面を参照して説明する。図1は、本発明の
第1の実施の形態の定電圧回路のブロック図である。図
1で、1は可変抵抗要素、2は固定抵抗要素、3は、分
圧点30から所要の定電圧を出力する端子、4は線形増
幅器、5は非線形増幅器、6は比較器、7は分圧される
電圧を印加する端子を、それぞれ表している。線形増幅
器4及び非線形増幅器5はともに分圧点30の電圧を入
力し、この各々の増幅器の出力を比較器6の比較入力と
している。可変抵抗要素1は、比較器6の比較結果出力
信号により抵抗値を制御している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the constant voltage circuit according to the first embodiment of the present invention. In FIG. 1, 1 is a variable resistance element, 2 is a fixed resistance element, 3 is a terminal for outputting a required constant voltage from a voltage dividing point 30, 4 is a linear amplifier, 5 is a non-linear amplifier, 6 is a comparator, 7 is a comparator. The terminals to which the divided voltage is applied are shown. Both the linear amplifier 4 and the non-linear amplifier 5 receive the voltage at the voltage dividing point 30, and the output of each amplifier is used as the comparison input of the comparator 6. The resistance value of the variable resistance element 1 is controlled by the comparison result output signal of the comparator 6.
【0012】図2は、線形増幅器4及び非線形増幅器5
の増幅特性を表す特性曲線である。図2で、これらの特
性曲線が一点で交わる点Aの入力電圧Vaが、所要の定
電圧値となる。入力電圧がVaよりも小さいときには、
線形増幅器の出力が非線形増幅器の出力よりも大きく、
入力電圧がVaよりも大きいときには、この大小関係が
逆転する。FIG. 2 shows a linear amplifier 4 and a nonlinear amplifier 5.
5 is a characteristic curve showing the amplification characteristic of the. In FIG. 2, the input voltage Va at point A where these characteristic curves intersect at one point is a required constant voltage value. When the input voltage is smaller than Va,
The output of the linear amplifier is greater than the output of the nonlinear amplifier,
When the input voltage is higher than Va, the magnitude relationship is reversed.
【0013】次に、この定電圧回路の動作を説明する。
電源を投入直後は、可変抵抗要素1の抵抗値は固定抵抗
要素2の抵抗値より十分に大きく、分圧点30の電圧は
一般にVaよりも小さく、従って増幅器への入力電圧も
Vaよりも小さい。このとき、比較器6の比較結果出力
はアクテイブ・レベルとなり、可変抵抗要素1はこの比
較結果出力信号により抵抗値が固定抵抗要素2の抵抗値
に比べて十分小さな値となり、分圧点30の電圧はVa
よりも大きな値に上昇する。このとき、増幅器の入力電
圧もVaより大きな値となるので、その出力の大小関係
が逆転し、従って、比較器6の出力も反転する。する
と、可変抵抗要素1の抵抗値は再び大きな値となり、分
圧点30の電圧はVaよりも小さな値となる。このよう
な反転動作を繰り返しながら、やがて分圧点30の電圧
はVaに近づき、収束する。このとき、比較器6の出力
は、分圧点30の電圧がVaとなるような抵抗の分割比
となるような可変抵抗値に制御する中間レベルの出力電
圧になる。この収束電圧Vaが所要の定電圧出力値とな
る。Next, the operation of the constant voltage circuit will be described.
Immediately after the power is turned on, the resistance value of the variable resistance element 1 is sufficiently larger than the resistance value of the fixed resistance element 2, and the voltage at the voltage dividing point 30 is generally smaller than Va, so that the input voltage to the amplifier is also smaller than Va. . At this time, the comparison result output of the comparator 6 becomes an active level, and the resistance value of the variable resistance element 1 becomes sufficiently smaller than the resistance value of the fixed resistance element 2 by the comparison result output signal. The voltage is Va
To a larger value. At this time, since the input voltage of the amplifier also becomes a value larger than Va, the magnitude relation of the output is reversed, and the output of the comparator 6 is also reversed. Then, the resistance value of the variable resistance element 1 becomes a large value again, and the voltage at the voltage dividing point 30 becomes a value smaller than Va. By repeating such inversion operation, the voltage at the voltage dividing point 30 eventually approaches Va and converges. At this time, the output of the comparator 6 is an intermediate level output voltage that is controlled to a variable resistance value such that the voltage of the voltage dividing point 30 becomes Va so that the resistance is divided. This convergence voltage Va becomes a required constant voltage output value.
【0014】次に、本発明の第2の実施の形態につい
て、以下に図面を参照して説明する。Next, a second embodiment of the present invention will be described below with reference to the drawings.
【0015】図3は、本発明の第2の実施の形態の定電
圧回路のブロック図である。図3で、41は、デジタル
信号入力8で、その増幅特性を制御するようにした線形
増幅器で、例えば、オペアンプの帰還抵抗ネットワーク
を選択して帰還抵抗値を制御してゲインを選択するよう
にした線形増幅器である。他の構成要素は、図1の場合
と同様である。このデジタル信号入力値を変えること
で、線形増幅器の増幅特性直線が、例えば図4に示すよ
うに直線1から、直線2に変わり、非線形増幅器の特性
曲線との交点が点Aから点Bに移動する。このようにし
て、交点の入力電圧をVaからVbに変えることによっ
て、所要の定電圧値を、VaからVbに変更することが
でき、定電圧出力値を可変制御できる。FIG. 3 is a block diagram of a constant voltage circuit according to a second embodiment of the present invention. In FIG. 3, reference numeral 41 denotes a digital signal input 8, which is a linear amplifier whose amplification characteristic is controlled, such as selecting a feedback resistance network of an operational amplifier and controlling a feedback resistance value to select a gain. This is a linear amplifier. Other components are the same as those in FIG. By changing the input value of the digital signal, the amplification characteristic straight line of the linear amplifier changes from the straight line 1 to the straight line 2 as shown in FIG. 4, for example, and the intersection with the characteristic curve of the nonlinear amplifier moves from the point A to the point B. I do. Thus, by changing the input voltage at the intersection from Va to Vb, the required constant voltage value can be changed from Va to Vb, and the constant voltage output value can be variably controlled.
【0016】次に、本発明の第3の実施の形態につい
て、以下に図面を参照して説明する。Next, a third embodiment of the present invention will be described below with reference to the drawings.
【0017】図5は、図3の定電圧回路をDA(デジタ
ル・アナログ)変換回路として利用した例で、線形増幅
器へのデジタル信号入力を、DA変換回路のデジタル入
力、定電圧出力をDA変換回路のアナログ変換出力とし
たDA変換回路のブロック図である。デジタル値とアナ
ログ値の関係は、線形増幅器41及び非線形増幅器5の
各々の増幅特性曲線から求めるようにする。FIG. 5 shows an example in which the constant voltage circuit of FIG. 3 is used as a DA (digital / analog) conversion circuit. A digital signal input to a linear amplifier is converted to a digital input of the DA conversion circuit, and a constant voltage output is converted to DA. FIG. 3 is a block diagram of a DA conversion circuit which is an analog conversion output of the circuit. The relationship between the digital value and the analog value is determined from the amplification characteristic curves of the linear amplifier 41 and the nonlinear amplifier 5.
【0018】[0018]
【発明の効果】以上のように、本発明の定電圧回路は、
線形増幅器と非線形増幅器の増幅特性曲線が一点で交わ
る点での入力電圧値を、所要の定電圧値となるようにし
たので、トランジスタ素子の特性のバラツキなどの影響
を受けにくく、また、CMOSトランジスタで回路を構
成することが容易になるという効果がある。As described above, the constant voltage circuit of the present invention
The input voltage value at the point where the amplification characteristic curves of the linear amplifier and the non-linear amplifier intersect at a single point is set to a required constant voltage value. Therefore, the input voltage value is hardly affected by variations in the characteristics of the transistor elements and the like. Thus, there is an effect that the circuit can be easily configured.
【図1】本発明の第1の実施の形態の定電圧回路のブロ
ック図。FIG. 1 is a block diagram of a constant voltage circuit according to a first embodiment of the present invention.
【図2】本発明の第1の実施の形態の定電圧回路の増幅
器の特性曲線図。FIG. 2 is a characteristic curve diagram of the amplifier of the constant voltage circuit according to the first embodiment of the present invention.
【図3】本発明の第2の実施の形態の定電圧回路のブロ
ック図。FIG. 3 is a block diagram of a constant voltage circuit according to a second embodiment of the present invention.
【図4】本発明の第2の実施の形態の定電圧回路の増幅
器の特性曲線図。FIG. 4 is a characteristic curve diagram of the amplifier of the constant voltage circuit according to the second embodiment of the present invention.
【図5】本発明の第3の実施の形態のDA変換回路のブ
ロック図。FIG. 5 is a block diagram of a DA conversion circuit according to a third embodiment of the present invention.
1 可変抵抗要素 2 固定抵抗要素 3 定電圧出力端子 4 線形増幅器 5 非線形増幅器 6 比較器 7 分圧される電圧を印加する端子 8 デジタル信号入力 9 データ・バッファ 10 デジタル変換入力 11 アナログ変換出力 DESCRIPTION OF SYMBOLS 1 Variable resistance element 2 Fixed resistance element 3 Constant voltage output terminal 4 Linear amplifier 5 Nonlinear amplifier 6 Comparator 7 Terminal for applying divided voltage 8 Digital signal input 9 Data buffer 10 Digital conversion input 11 Analog conversion output
Claims (9)
分圧して定電圧出力を得るようにした定電圧回路におい
て、前記定電圧出力信号を共通の入力とする2つの増幅
器と、これら増幅器の出力を比較入力とする比較器とを
備え、前記比較器の出力により、前記可変抵抗要素の抵
抗値を可変制御するように構成し、所要の定電圧値を境
界入力値として、前記2つの増幅器の増幅出力の大小関
係が、反転するようにしたことを特徴とする定電圧回
路。1. A constant voltage circuit in which a voltage is divided by a variable resistance element and a fixed resistance element to obtain a constant voltage output, two amplifiers having the constant voltage output signal as a common input, and these amplifiers And a comparator having the output of the comparator as a comparison input, wherein the resistance of the variable resistance element is variably controlled by the output of the comparator, and a required constant voltage value is set as a boundary input value, and the two constant values are used as the boundary input value. A constant voltage circuit characterized in that the magnitude relationship between the amplification outputs of the amplifiers is inverted.
他方を非線形増幅器で構成し、各々の増幅特性曲線が一
点で交わる入力電圧値を、所要の定電圧値とするように
したことを特徴とする請求項1記載の定電圧回路。2. One of the two amplifiers is a linear amplifier,
2. The constant voltage circuit according to claim 1, wherein the other is constituted by a non-linear amplifier, and an input voltage value at which each amplification characteristic curve crosses at one point is a required constant voltage value.
他方を非線形増幅器で構成し、前記線形増幅器の増幅特
性を可変制御することにより、各々の増幅特性曲線が一
点で交わる入力電圧値を、所定の定電圧値とするように
したことを特徴とする請求項1記載の定電圧回路。3. One of the two amplifiers is a linear amplifier,
The other is constituted by a non-linear amplifier, and by variably controlling the amplification characteristics of the linear amplifier, the input voltage value at which each amplification characteristic curve crosses at one point is set to a predetermined constant voltage value. The constant voltage circuit according to claim 1.
他方を非線形増幅器で構成し、前記線形増幅器の増幅特
性を、デジタル値入力で可変制御することにより、各々
の増幅特性曲線が一点で交わる入力電圧値を、所要の定
電圧値とするようにしたことを特徴とする請求項1記載
の定電圧回路。4. One of the two amplifiers is a linear amplifier,
The other is constituted by a non-linear amplifier, and the amplification characteristic of the linear amplifier is variably controlled by digital value input so that the input voltage value at which each amplification characteristic curve intersects at one point is set to a required constant voltage value. The constant voltage circuit according to claim 1, wherein:
構成され、ソース・ドレイン間の抵抗値を、ゲート入力
電圧で制御することにより、その抵抗値を可変制御する
ようにしたことを特徴とする、請求項1、2,3または
請求項4記載の定電圧回路。5. A variable resistance element comprising a MOS transistor, wherein a resistance value between a source and a drain is controlled by a gate input voltage to variably control the resistance value. The constant voltage circuit according to claim 1, 2, 3, or 4.
変抵抗要素と並列に、別の固定抵抗要素を接続して電圧
の分圧回路を構成するようにしたことを特徴とする、請
求項1,2,3,4または請求項5記載の定電圧回路。6. A voltage dividing circuit in which another fixed resistance element is connected in parallel with the variable resistance element from the constant voltage output terminal side of the fixed resistance element to constitute a voltage dividing circuit. The constant voltage circuit according to claim 1, 2, 3, 4, or 5.
ジタル値入力と定電圧回路出力との関係を、デジタル・
アナログ(DA)変換に利用するようにしたことを特徴
とするDA変換回路。7. The relationship between a digital value input and a constant voltage circuit output in the constant voltage circuit according to claim 4,
A DA converter circuit used for analog (DA) conversion.
回路であることを特徴とする請求項7に記載したDA変
換回路。8. The DA converter according to claim 7, wherein the constant voltage circuit is the constant voltage circuit according to claim 5.
回路であることを特徴とする請求項7に記載したDA変
換回路。9. The DA converter according to claim 7, wherein the constant voltage circuit is the constant voltage circuit according to claim 6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9014280A JP2985815B2 (en) | 1997-01-28 | 1997-01-28 | Constant voltage circuit and DA conversion circuit using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9014280A JP2985815B2 (en) | 1997-01-28 | 1997-01-28 | Constant voltage circuit and DA conversion circuit using the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10209766A JPH10209766A (en) | 1998-08-07 |
JP2985815B2 true JP2985815B2 (en) | 1999-12-06 |
Family
ID=11856688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9014280A Expired - Fee Related JP2985815B2 (en) | 1997-01-28 | 1997-01-28 | Constant voltage circuit and DA conversion circuit using the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2985815B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5068522B2 (en) * | 2006-12-08 | 2012-11-07 | 株式会社リコー | Reference voltage generation circuit |
JP2011205202A (en) * | 2010-03-24 | 2011-10-13 | Toshiba Corp | Voltage-current converter circuit and pll circuit having the same |
-
1997
- 1997-01-28 JP JP9014280A patent/JP2985815B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH10209766A (en) | 1998-08-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH06152275A (en) | Differential circuit and differential amplifying circuit | |
JPH07122946A (en) | Voltage - electric current converter without series sense resistance | |
JP3410704B2 (en) | High speed current mirror circuit and method | |
KR20020035324A (en) | Differential amplifier | |
JPH01311608A (en) | Voltage/current converter | |
US6542098B1 (en) | Low-output capacitance, current mode digital-to-analog converter | |
JPS631766B2 (en) | ||
JP2985815B2 (en) | Constant voltage circuit and DA conversion circuit using the same | |
JP2783776B2 (en) | Operational transconductance amplifier | |
JPH11340753A (en) | Arithmetic amplifier | |
US4757275A (en) | Wideband closed loop amplifier | |
JPH04243308A (en) | Operational amplifier | |
JP3352899B2 (en) | Amplifier circuit | |
KR100821122B1 (en) | CMOS Type Variable Gain Amplifier | |
JP2859880B2 (en) | Variable gain amplifier circuit | |
JPH051646B2 (en) | ||
JPH04330812A (en) | Vca circuit | |
US20090045869A1 (en) | Semiconductor circuit and controlling method thereof | |
JP3144361B2 (en) | Differential amplifier | |
JPH0241927Y2 (en) | ||
JP2661530B2 (en) | Voltage-current converter | |
JPH0332095Y2 (en) | ||
JPH07183743A (en) | Voltage-current conversion circuit | |
JPH0246090Y2 (en) | ||
JPS59183515A (en) | Variable gain differential amplifier circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990831 |
|
LAPS | Cancellation because of no payment of annual fees |