JP2979289B2 - Semiconductor test package with high density array external contacts. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to semiconductor manufacturing, and more particularly to an improved package for temporarily packaging semiconductors for testing or other purposes (referred to herein as "testing"). Package "
Or "temporary package". ) .

[0002]

BACKGROUND OF THE INVENTION Conventional packaged semiconductor dies (hereinafter "package dies") undergo several tests throughout the manufacturing process. At the wafer level, a probe test is performed to test the gross function of the die. After the wafer has been separated into individual dies and packaged, each package die is subjected to its full functionality and burn-in test. These tests are performed on package external contacts (eg, lead terminals)
The test is performed using a standardized device that forms an electrical interface between the test circuit and the test circuit.

[0003] For example, a burn-in oven is an apparatus configured to hold a large number of dies in a chamber capable of periodically changing a temperature. Integrated circuits are electrically tested at different temperatures during the burn-in test. A burn-in board mounted in the chamber has connectors that match the external leads of the package dies to electrically connect the individual packaged dies to the test circuitry. That is, if the package die has male external contacts, e.g., pin-like lead terminals, then the burn-in device has a socket connector.
A board is used. If the package die has female external leads, a burn-in board with a pogo pin connector is used.

Since semiconductor dies are packaged in standardized shapes, burn-in boards are also standardized. For example, one commonly used semiconductor package for a single die is known as a Small Out-Ain-J-Lead (SOJ) package. SO
For the J package, a burn-in board having a standardized socket compatible with the J lead of the package is used. The spacing between the sockets is such that many packages can be densely arranged and mounted on a single board in close proximity.

[0005] In addition to the standardized boards, related devices such as automatic handling devices are used, which are also standardized to specific package shapes. Other examples of a single-die standardized package include a dual in-line package (DIP) and a zigzag in-line package (ZIP).

Recently, semiconductor dies have also been supplied from manufacturers without packaging, ie, bare. Test passing die (known good die: K
Abbreviated as GD. ) Refers to an unpackaged (unpackaged) die that has been tested at the same quality and reliability level as the packaged product. Burn-in testing must be performed on unpackaged dies to assure that the die passes the test. For this reason,
Test carriers have been developed that carry a single unpackaged die for burn-in and other tests. Any such test carrier contains a die to be tested and electrically interconnects the die with an external test circuit. Typical test carriers are Wood et al., U.S. Pat.No. 5,302,891, and Wood et al., U.S. Pat.
No. 408,190.

[0007]

One of the features of these carriers is that they require special test equipment, such as specific burn-in boards and handling equipment, unlike conventional test equipment for package dies. There is a point that. Moreover, carriers that have been developed to date are larger than conventional package dies, thus requiring larger test equipment to achieve the same throughput. Therefore, it would be advantageous to provide a test carrier for semiconductor dies that can be used in standardized test equipment.

Another problem with conventional carriers for testing semiconductor dies is the limited pinout function at the carrier's external contacts. A typical carrier has external contacts in the form of pins and connects to corresponding sockets on the burn-in board. With this type of external contact configuration, a die having a large number of high density bond pads is not well adapted to external contacts. Generally, the bond pads of a semiconductor die are smaller and denser. In this case, it would be advantageous to provide a carrier for a semiconductor die having a high density of external contact geometries capable of processing a die having multiple bond pads.

The present invention relates to the carrier being configured as a temporary package having a standard outer shape and densely arranged external contacts. As mentioned above, it is an object of the present invention to provide a temporary package of semiconductor dies for use in testing or other purposes. It is another object of the present invention to provide a temporary package of semiconductor dies having output contacts densely arranged in a densely packed portion. Still another object of the present invention is to provide a JE
It is an object of the present invention to provide a temporary semiconductor package having a DEC standard external shape and a JEDEC standard external contact shape. Other objects, advantages, and other features of the present invention will become apparent from the following description.

[0010]

SUMMARY OF THE INVENTION In accordance with the present invention, there is provided an improved temporary package for a semiconductor die. The temporary package has a standard outer shape and external lead shapes that match conventional semiconductor packages. Further, the external leads are formed in a high-density array adapted to bond pads (small-area electrode portions made of a metal thin film) of many devices. High-density arrays and lead shapes suitable for external leads include land grid arrays (LGA),
Grid Array (PGA), Ball Grit Array (BGA) and Peripheral Array. Because this temporary package has a standard outline and external lead shape, it can be used with standard burn-in boards and automated package handling equipment used in testing die that pass the test.

The temporary package has a base, an interconnect, and a pressurizing mechanism. The package base has an internal conductive member (conductor) electrically connected to the external contact. The package base may be made of ceramic or plastic. In the case of ceramic, the package base can be ceramic lamination or ceramic dip formation (Ce
rdip) method. Also, the package base can be manufactured by a 3-D injection molding method using plastic or a ceramic dip formation (Cerdip) method combining injection molding.

The package interconnect is mounted on a base and connected to conductive members on the package base by wire bonding. The interconnect is formed of silicon and has raised conductive members in contact with and in electrical contact with the conductive lines and bond pads of the die.
Interconnects can also be formed by mounting microbump contact members on a plastic film similar to a two-layer TAB tape.

The pressure mechanism of the package has a pressure plate, a spring, and a cover. The pressure mechanism secures the die in the base and makes the die and the interconnect electrically contact. This pressing mechanism is fixed to the base by a latch mechanism.

The package is assembled with the die and interconnect optically aligned. Prior to alignment, the interconnect is mounted in the package base by wire bonding,
Wire bonding is performed to form an electrical path between a contact member on the interconnect and an external contact on the package base. During the alignment process, the die and the pressing mechanism of the package are held by the assembling apparatus. Flip-chip optical alignment is used to align the die bond pads with the interconnect contact members. The die is placed on the interconnect by the assembling apparatus, and the pressing mechanism is attached to the package base.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 is an exploded perspective view of a temporary package (10) constructed in accordance with the present invention. The package (10) includes a semiconductor die (1).
Hold 2) and make temporary electrical connections with the die for testing and burn-in. After completing the test, the die (12) is removed from the package (10) and can be used as a passing die.

Broadly speaking, the package (10)
Package base (14), interconnect (1
6) and a pressure mechanism (18). The interconnect (16) consists of a package base (14) and a die (1).
2) is electrically connected to The pressing mechanism (18) fixes the die (12) to the package base (14) and presses the die (12) against the interconnect (16). Pressing mechanism (18) is pressing plate (20), spring (22)
And a cover (24). The package (1
No. 0) has a latch mechanism (FIG. 3 (FIG. 3)) composed of clips (26, 28), and fixes the pressing mechanism (18) on the package base (14).

The package base (14) has a pattern of the inner conductive member (40), and has a package base (14).
Are electrically connected to external contacts (38A to 38C) (FIG. 2) formed on the bottom surface (31) of FIG. 2 (FIG. 2). More specifically, the conductive member (4
0) is wire bonded to the interconnect (16), and the die (12) is connected to external contacts (38A-38).
C) and an electrical path is formed. The package base (14) also has an indicator (display) pocket (37), which is used to indicate the direction of the external contacts (38A-38C) with respect to the die (12) (i.e., pin #). 1 indicator).

As shown in FIG. 3 (FIG. 3), in the assembled package (10), the die (12) is held in the recess (36) in the package base (14) and is connected to the interconnect (16). It is sandwiched between the cover (24). The interconnect (16) is mounted in a recess (34) in the package base (14). As shown in FIG. 7 (FIG. 3), in the assembled package (10), the pressing plate (20) is placed on the die (12), and the spring (22) is connected to the pressing plate (20). Die (12) and interconnect (16)
Pressed against.

As shown in FIG. 7 (FIG. 3), clips (26, 28) are mounted in the openings (30, 32) of the base (14) facing each other, and the cover (2) is provided.
4) The spring (22), the pressure plate (20) and the die (12) are fixed in the package base (14). The clips (26, 28) are formed of a flexible material, such as spring steel or plastic, and are shaped to exert a retaining force on the cover (24). Also, in the assembled package (10), the cover (2)
4) is placed at a position recessed from the upper surface of the package base (14). Therefore, the outer peripheral size and outer shape of the package (10) are substantially equal to the package base (1).
It is determined by the outer peripheral size and outer shape of 4).

As shown in FIG. 3 (FIG. 3), a cover (24), a spring (22) and a pressure plate (20)
Have openings 48C, 48S, and 48P at the center, respectively. As will be described in detail later, the openings (48C, 48S, 48P) are used when assembling and disassembling the package (10). Specifically, the package (1) is formed by the openings (48C, 48S, 48P).
0), the die (12) and the interconnect (1) are assembled.
At the time of the optical alignment in 6), the die (12) can be held by the vacuuming device (not shown). The evacuation device (not shown) is used for dismantling the package (10) by the same method.

The package (10) has a standard outer shape substantially equivalent to that of a conventional semiconductor package. Further, the external contacts (38A to 38C) are formed with standard sizes and intervals substantially equivalent to those of a conventional semiconductor package. Here, the conventional semiconductor package means a plastic or ceramic package having a size and an external lead shape conforming to the standards of a publicly recognized industrial standard setting organization. Such standard setting organizations include the following: EIA / JEDEC: Electronic Industries Association / Electronic Element Industrial Technology Association Council JEIDA: Japan Electronics Industry Development Association PCMCIA: PC Memory Card International Association

Since the package (10) has a standard outer shape and lead shape, it can be used in a standardized standard burn-in device for a conventional package. For example, such a standard device includes AM from Micron Systems Integrations, Inc.
BYX® Intelligent Burn-in
And test systems.

As shown in FIG. 2 (FIG. 2), external contacts (38A to 38C) of the package (10) are formed in a high-density grid pattern on the bottom surface (31) of the base (14). As shown in FIG. 3 (FIG. 2A), the external contact (38A) has a land pad (plane) shape arranged in a land grid array (LGA). Also, as shown in FIG. 4 (FIG. 2B),
The external contacts (38B) are in the form of pins arranged in a pin grid array (PGA). FIG.
As shown in FIG. 2C, the external contacts (38
C) has the shape of a bump arranged in a ball grid array (BGA). External contacts (38A-3
8C) can be arranged in a high-density outer peripheral pattern (not shown) rather than a grid pattern.

In each of these cases, the external contacts (38A-38C) are connected to the package base (1).
4) It is electrically connected to the internal conductive line (49) always formed. The internal conductive line (49) is electrically connected to a conductive member (40) formed on the package base (14). As shown in FIG. 3A, the conductive member (40) ends at the bond shelf (42) and is wire bonded to the interconnect (16) using bonding wires (44).

As shown in FIG. 3 (FIG. 2A), the land
External contacts (38A) in the form of a grid array can be made from a suitable metal or a stack of metals from flat lands.
It is formed as a pad. Preferred metals are gold,
Examples include copper, silver, tungsten, tantalum, platinum, palladium, and molybdenum, or alloys of these metals. As a preferable lamination, a layer in which a gold layer is provided on a nickel base plating is cited. Preferred laminates include other combinations of the above-mentioned metals. The flat land pad-shaped external contact (38A) can be manufactured by a metal coating method such as plating. The plating process involves electrolytic or electroless deposition of a metal layer, followed by resist coating, exposure, development, and selective wet chemical etching. Typically, the exposed surface of the external contact (38A) is comprised of a metal such as electroplated gold.

The diameter of the external contact (38A) is, for example, about 50 μm to 500 μm. The distance between the center lines of the external contacts (38A) is about 50 μm to 500 μm.
μm. The thickness of the external contact (38A) is, for example, 1.25 μm to 100 μm. External contacts (3
8A) is electrically connected to an external test circuit by an electrical connector such as a pogo pin of a burn-in board, a solder ball or another connector.

As shown in FIG. 4 (FIG. 2B), the external contact (38B) is connected to the external contact (38).
It is manufactured using almost the same method as in A), but the pins are joined to the flat land pads by brazing or soldering. As shown in FIG. 5 (FIG. 2C), the external contact (38C) is connected to the external contact (38).
The solder paste is manufactured using substantially the same method as in A), but the solder paste is screen-printed on the flat land pad, heated, and then reflowed into a ball shape (reflow) .

The term "high density grid pattern" as used herein means a contact pattern in which the density of the contacts (38A-38C) is high compared to the total area occupied by the contacts. This relationship is sometimes described as "packing ratio". Generally, the packing ratio of a contact pattern refers to the area occupied by the contacts in the entire area. For example, a grid pattern of a block of 1 square inch in an area of 12 inches × 12 inches
The packing ratio of the 44 formed contacts is 1. 1
A pattern in which 144 1-inch diameter circular contacts are formed in 44 1-inch square grids has a packing ratio of 0.7854. In practice, a certain spacing is required to minimize shorts between contacts, and packing ratios close to 1 are not possible. For example, a bump (FIG. 5 (FIG. 2)
In the contact formed in 38C) of C), a certain interval is required to prevent a short circuit during re-inflow. Generally, the “high-density grid pattern” means that the packing ratio
0.25 or greater.

As shown in FIG. 6 (FIG. 2D),
The package base (14) is made of alumina (Al ₂ O ₃ )
It is a multilayer block formed by firing and laminating ceramic layers (41A to 41E) as described above. Such a process is described in U.S. patent application Ser. No. 08/3, filed Mar. 1, 1995.
No. 98,309 (US Pat. No. 5,519,332) , the contents of which are incorporated herein by reference. This method is, in short, an x-plane, y-plane
Forming a metallized circuit on the plane and the z-plane. These circuits are formed on ceramic green sheets using a suitable metallization process and interconnected by metal-filled vias. Then, it presses with a green sheet and sinters at high temperature to make a single structure. Using this method, the conductive member (40) and the external contacts (38A to 38A) are used.
C) is made of a suitable metal, and then the internal conductive lines (49)
Are formed and connected to each other. Further, FIG.
A) to FIG. 5 (FIG. 2C), the external contacts (38A to 38C) are provided at positions recessed from the outermost ceramic layer (41E).

The package base (14) may be formed from a high temperature glass filled plastic such as FR-4 material using a 3-D injection molding method. Such a method is disclosed in U.S. Pat. No. 4,985,116 and the previously cited U.S. patent application Ser. No. 08 / 398,309 (U.S. Pat.
5,519,332) . Suitable plastics include polyetherimide (PEI), polyethersulfone (PES), polyarylsulfone (PAS), polyphenylene sulfide (PPS),
Liquid crystal polymer (LCP) and polyether-ether ketone (PEEK). Injection molding is used to form a package base (14) having these cavities in the desired rectangular shape using these and other suitable materials. By a subsequent metallization step, the conductive member (40) is placed on the package base (14).
And various circuit patterns having external contacts (38A to 38C) are formed and connected to each other by forming internal conductive lines (49).

The package base (14) can also be formed by using a ceramic dip formation (Cerdip) method. In general, in the Cerdip method, a mixture of an alumina lubricant and a binder is molded and sintered to form a monolithic (integral structure) package base (14). Then, package base (1) using low-temperature glass
4) Connect the metal lead frame to the conductive member (4).
0) is formed. The external contacts (38A-38C) may be part of the lead frame or may be formed separately. Another type of ceramic dip
In the formation method, a plastic is used rather than a ceramic substrate. In short, the Cerdip method preforms a plastic base and bonds it to a lead frame. Conventional semiconductor packages formed using this method are available from GTE Products Corporation of Warren, Pennsylvania (GTE Product Corporation).
s Corporation) under the name QUADPACK (registered trademark).

FIG. 8A shows a package (10A) of another embodiment. The package (10A) of this embodiment has substantially the same elements (shown with the suffix "A") as described above in the package (10). However, in the package (10A) of this embodiment, the spring (22A) is formed of a flat plate member, and the pressing plate (20) (FIG. 3) is omitted. The spring (22A) may be, for example, a flat metal spring (for example, a wave spring) or may be formed of an elastic elastomer material such as a silicone elastomer or a polyimide material.

Further, in this package (10A),
The cover (24A) has a recess (50), and the spring (22A) and the die (12) are housed therein. The cover (24A) is in contact with the bottom surface of the recess (36A) of the package base (14A) and is held by a pair of sliding clips (26A, 28A).
The sliding clips (26A, 28A) are slidably mounted on the base (14A), are formed in an S shape, and exert a holding force on the cover (24A).

FIG. 9 (FIG. 4) shows the interconnect (16) of the package (10) alone. The interconnect (16) has a bonding pad (56) and a conductive member (4) formed in the package base (14).
0) is wire-bonded. The interconnect (16) also has conductive traces (58) and raised contact members (60). As shown in FIG. 5 (FIG. 5), the raised contact member (60) is
2) It is configured to contact and electrically connect to the upper device bond pad (62) or other contact sites. The raised contact member (60) also has an elongated blade-shaped intrusion protrusion (70) configured such that the intrusion depth into the device bond pad (62) is limited by itself. ing.

The interconnect (16) and the raised contact member (60) can be formed by etching the silicon substrate (64). Substrate (64)
The insulating layer (66) and the conductive layer (68) formed thereon cover the raised contact member (60). Conductive layer (6
8) is in electrical communication with the conductive traces (58), and the traces (58) are wire bonded to the wires (44). Alternatively, instead of wire bonding, a slide contact (44S) may be electrically connected to the conductive trace (58).

Suitable methods for forming the contact member (60) are described in US Pat. No. 5,326,428 and US Pat.
No. 5,419.807. These contents are incorporated herein by reference. Another suitable method is
No. 08 / 335,267, filed Nov. 7, 1994. The contents of which are incorporated herein by reference.

As shown in FIG. 11 (FIG. 5A), the interconnect (16) is a micro-bump contact member (60B) formed on a plastic film.
And conductive traces (58B).
The microbump contact member (60B) and the plastic film (72) are similar to a two-layer TAB tape (for example, ASMAT manufactured by Nitto Denko). Plastic film (72) is compatible
Substrate (64B) such as silicon with adhesive layer (74)
Mounted on top. This affinity adhesive layer can be formed of a silicone elastomer, epoxy or polyimide material. One method of forming interconnects having microbump contact members is described in US patent application Ser. No. 08 / 398,309, cited above (US Pat.
No. 5,519,332) .

Referring again to FIG. 1, the package (10) can be assembled using optical alignment techniques and aligner bonders used to flip chip bond semiconductor dies.
Flip chip bonding refers to a substrate (for example,
It refers to a method of placing a semiconductor die face down (ie, face down) on a printed circuit board) and connecting bond pads on the die to connection points on the substrate. The flip chip bonding apparatus is sometimes called an aligner bonder. An aligner bonder and optical alignment method for flip chip bonding are described in US Pat. No. 4,899,9 to Bendat et al., Entitled "AlignerBonder".
No. 21. Such aligner bonders are available from Piscataawa, NJ, USA.
y, NJ)
ces).

In the case of the present invention, the aligner bonder may be modified so as to constitute an assembling apparatus used for assembling the package (10). The assembling apparatus has an assembling tool (not shown) which includes a pressing mechanism (18) (FIG. 1), a die (12) and clips (26, 28) (FIG. 7). (FIG. 3)). Each element of the pressurizing mechanism (18) has an opening (48C, 48S, 48P) so that the die (12) can be attached to the evacuation wand (bar member) of the assembly tool.
Can be held. Bond pad (62) on die (12) with die (12) held in the assembly tool
(FIG. 10) is aligned with the contact member (60) on the interconnect (16) (FIG. 5). Thereafter, the assembling tool places the die (12) in contact with the interconnect (16) and clips (26,32) into the openings (30,32) of the package base (14).
28) (FIG. 3) is fixed.

US patent application Ser. No. 08 / 338,345, filed Nov. 14, 1994 (US Pat.
No. 267) includes a die (12) and an interconnect (1).
An automatic device is described for optically aligning 6) and fixing the pressing mechanism (18) to the package base (14).

After assembly, the die (16) can be tested using the package (10). Tests such as full function and burn-in tests are possible. After testing, the package (10) is disassembled using an assembly tool (not shown) and the clips (26, 28) and the pressurizing mechanism (1) are substantially as described above for the assembly process.
8) Remove.

While some preferred embodiments of the present invention have been described above, it will be apparent to those skilled in the art that changes and modifications can be made without departing from the scope of the invention.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a package configured according to the present invention.

FIG. 2 is a bottom view of a package base showing external contacts formed in a high-density grid array.

FIG. 3 is a cross-sectional view showing an external contact formed in a flat pad shape in a land grid array (LGA), taken along a line 2A-2A in FIG. 2;

FIG. 4 shows a pin-shaped external contact in a pin grid array (PGA);
Sectional drawing cut | disconnected along {-2}.

FIG. 5 shows external contacts formed in a bump shape in a bumped grid array (ΒGA);
Sectional drawing cut | disconnected along line 2C-2C of FIG.

FIG. 6 is a cross-sectional view illustrating the multilayer ceramic layer of the package base, taken along line 2D-2D in FIG. 2;

FIG. 7 is a cross-sectional view of the assembled package.

FIG. 8 shows a package according to a different embodiment.
Sectional drawing similar to.

FIG. 9 is a plan view of the interconnect of the package shown in FIG. 1;

FIG. 10 is a cross-sectional view of the interconnect raised contact member electrically connected to the device pond pad on the die, taken along section line 5-5 of FIG. 9;

FIG. 11 is a cross-sectional view similar to FIG. 10 showing an interconnect according to a different embodiment having microbump contact members.

[Explanation of symbols]

10, 10A package 12 Die 14, 14A Package base 16 Interconnect 18 Pressing mechanism 20 Pressing plate 22, 22A Spring 24, 24A Cover 26, 26A, 28, 28A Clip 36, 36A, 50 Recess 38A, 38B, 38C External contact 40 Conductive member 41A, 41B, 41C, 41D, 41E Ceramic layer 42 Bond shelf 44 Bonding wire 48C, 48S, 48P Opening 49 Internal conductive line 56 Bonding pad 58, 58B Conductive trace 60 Raised contact member 62 Device bond pad 64 Substrate 66 Insulating layer 68 Conductive layer

Continuation of the front page (72) Inventor Warren M. Farnworth United States of America, 83686, Idaho, Nampa, Es Banner 2004 Sails Court 1366 (72) Inventor Salman Akram United States, 83709, Idaho, Boise, Jekeller Lane 3713 (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 23/00 G01R 31/26 H01L 21/66

Claims (25)

(57) [Claims] 1. A plurality of external contacts on the surface are densely packed.
It formed in degrees array, based <br/> scan for holding the die; plurality of electrically connected to the plurality of contact locations on the die
Of including a contact member, the inter connection <br/> transfected on the base; a plurality of packages for semiconductor die testing include an electrical path formed between the external contacts and the contact member and the base on the interconnect. 2. The high density array of claim 1, wherein the high density array is selected from the group consisting of a land grid array (LGA), a pin grid array (PGA), a ball grid array (BGA), and a peripheral array. Package. 3. The package according to claim 1, wherein the base is formed to an outer shape corresponding to a normal semiconductor package. 4. The package of claim 1, wherein the base is made by a method selected from the group consisting of a ceramic lamination method, a 3-D molding method, and a ceramic dip formation method. 5. An electrical path comprising wire bonding between conductive traces made on the interconnect and conductive members on a base in electrical communication with external contacts.
The package of claim 1 comprising : 6. A base for holding a die, comprising:
An external contact pattern in the form of a high-density grid array selected from the group consisting of a land grid array (LGA), a pin grid array (PGA), and a ball grid array (BGA) formed on the base. a plurality of electrically connecting the plurality of contact locations on the die; the internal conductive traces electrically connected with including the base
Of including a contact member, interconnect <br/> bets on the base; semi <br/> conductor die test package comprising a plurality of conductive paths between and external contacts on the interconnect contact member and the base. 7. The package of claim 6 in which the package base has a conventional semiconductor package is substantially equal to the outer shape. 8. A conductive path is formed on the base such that the conductive path is in electrical communication with the internal conductive traces.
Interconnect so that it is electrically connected to the contact member.
Wiring the conductive member to conductive traces formed on the
The package according to claim 6, wherein the package is formed by wire bonding . 9. The green base made of a ceramic material.
Formed using a lamination method that combines sheets by a sintering process
The package of claim 6 being. 10. The package according to claim 6, wherein the base is formed from a glass-filled plastic using a 3-D molding method. The package of claim 6 11. base, which is formed by using a ceramic dip formation method. 12. An external contact having a thickness of 50 μm to 500 μm.
7. The package according to claim 6, wherein the package is formed with a diameter of between μm and a pitch between 50 μm and 500 μm. 13. An external contact having at least 0.25
Formed into a high-density grid array with a packing ratio of
The package of claim 6 being. 14. The method according to claim 1, wherein the external contact is a flat land.
The package of claim 6, including a pad. 15. The method according to claim 15, wherein the external contact is a flat land.
7. The package of claim 6, including a pin joining the pad. 16. The method according to claim 1, wherein the external contact is a flat land.
The package of claim 6, including solder bumps on the pads. 17. A package base for holding a die.
And formed as a ball grid array on the base
Electrical connection with multiple ball-shaped external contacts
Package base including a conductive member ; a plurality of contours electrically connected to the conductive member pattern
A contact member, the contact member being a contact member on the die.
Located to form an electrical connection with the
Semiconductor die testing package including interconnect on base . 18. The package of claim 17, wherein the interconnect includes a raised silicon contact member having an elongated intrusion protrusion formed on the silicon substrate. 19. The package of claim 17, wherein the interconnect includes a micro-bump contact member mounted on the substrate using an affinity adhesive layer. 20. The package according to claim 17, wherein the package base is formed of a material selected from the group consisting of plastic and ceramic. 21. The package according to claim 17, wherein the package base is made by a method selected from the group consisting of a ceramic lamination method, a 3-D molding method, and a ceramic dip method. 22. Fixing the die on the interconnect
18. The package according to claim 17, further comprising a pressurizing means for pressurizing.
cage. 23. The package according to claim 22, wherein the pressing mechanism includes a spring and a cover. 24. The package of claim 23 , wherein the spring is formed of a resilient material. 25. The package according to claim 17, wherein the external contacts of the high density grid array have a packing ratio of at least 0.25.