JP2977604B2 - Inverter controlled engine generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an inverter-controlled engine generator used for a portable AC power supply or the like.

(Prior Art) In recent years, an inverter device has been increasingly used in a portable AC power supply device to stabilize an output frequency. For example, an AC generator driven by an engine has a commercial frequency. In a portable power supply device that outputs AC power, a high-power AC current is obtained from a generator by operating an engine in a high rotational speed region, and this AC current is temporarily converted to DC, and then commercialized by an inverter device. A device that converts the frequency into AC and outputs it is
This is known from JP-A-59-132398.

(Problems to be Solved by the Invention) By the way, a drive power supply for driving an inverter device generally depends on a generator output, and the generator output is not sufficient in a low-speed rotation range of the generator at an early stage of engine start. As a result, the power supply voltage of the drive power supply of the inverter device tends to become unstable when the engine is started. Especially when the inverter device is configured with a FET bridge circuit,
When the power supply voltage is unstable as described above,
It was necessary to configure the FETs that should be turned off so that they did not turn on irregularly due to disturbance or the like, and it was very difficult to take countermeasures.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an inverter-controlled engine generator in which an unstable operation of an inverter circuit is suppressed in an early stage of engine start.

According to an embodiment of the present invention, there is provided an engine, a generator driven by the engine, and a thyristor bridge circuit. In a DC voltage control circuit that rectifies the output to maintain a predetermined DC voltage, and an inverter control type engine generator having an inverter circuit that converts output power from the DC voltage control circuit into AC output power of a predetermined frequency, The DC voltage control circuit feeds a rectified output voltage back to the thyristor bridge circuit to maintain the predetermined DC voltage when the engine speed is equal to or less than a set value set to a value lower than the speed during rated operation. And a rectified output is not supplied to the inverter circuit. The soft-start of the feedback control from when the rotation speed exceeds the set value gradually increases the conduction current amount of the thyristor bridge circuit to reach the predetermined DC voltage. An inverter controlled engine generator is provided.

(Operation) The AC output from the output winding of the generator driven by the engine is rectified by the DC voltage control circuit, and feedback control based on the rectified output voltage is performed so as to be maintained at a predetermined DC voltage. The output is converted into AC output power of a predetermined frequency by an inverter circuit. In the DC voltage control circuit, feedback control is performed so as to maintain the predetermined DC voltage on condition that the engine speed exceeds a set value lower than the engine speed during rated operation. At a time point when the engine speed is low, such as when the engine is started, the feedback control is prohibited, and the rectified output from the DC voltage control circuit is not supplied to the inverter circuit. By soft-starting the feedback control from the time when the engine speed exceeds the set value, the amount of conduction current of the thyristor bridge circuit constituting the DC conversion control circuit is gradually increased to reach the predetermined DC voltage. Try to tighten.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is an overall configuration diagram of an inverter-controlled engine generator according to the present invention. In the drawing, reference numerals 1 and 2 denote output windings wound independently on a stator of an AC generator, respectively.
Denotes a three-phase output winding, and 2 denotes a single-phase auxiliary winding. Further, a rotor (not shown) is formed with magnetic poles of a multi-pole permanent magnet, and is configured to be rotationally driven by an engine (not shown). The output terminal of the three-phase output winding 1 is connected to a bridge rectifier circuit 3 including three thyristors and three diodes, and the output terminal of the bridge rectifier circuit 3 is connected to a smoothing circuit 4.

The output terminal of the single-phase auxiliary winding 2 is connected to a constant voltage supply device 5 having positive and negative bipolar output terminals E and F. The constant voltage supply device 5 is composed of two sets of rectifier circuits, a smoothing circuit, and a constant voltage circuit 5a. With respect to the current in the direction, each circuit of the other set works, whereby positive and negative constant voltages are output to the output terminals E and F, respectively.

Reference numeral 6 denotes a thyristor control circuit. One end on the power input side is connected to the positive output terminal E of the constant voltage supply device 5, and the other end is grounded together with the positive terminal on the smoothing circuit 4. The signal input terminal of the thyristor control circuit 6 is a capacitor C1 and resistors R1 to R3.
One end of the capacitor C1 is connected to the positive output terminal E of the constant voltage supply device 5, and the other end of the resistor R3 is connected to the negative terminal of the smoothing circuit 4. The connection point between the resistors R1 and R2 is connected to the base of the transistor Q1, the collector of the transistor Q1 is connected to the base of the transistor Q2, and the collector of the transistor Q2 is connected to the gate input circuit of each thyristor of the bridge rectifier circuit 3. R1 and resistance
It is configured to control the input signal of the gate input circuit according to the potential of the connection point with R2.
Since it is disclosed in 230908, it is omitted here).

The output side of the transient suppression circuit 7 is connected to a connection point K between the capacitor C1 and the resistor R1. The transient suppression circuit 7 relates to a main part of the present invention and is configured as follows. That is,
The cathode side of the Zener diode D1 is connected to the input side (G) of the constant voltage circuit 5a provided on the positive electrode output terminal E side of the constant voltage supply device 5, and the anode side of the Zener diode D1 is connected to the constant voltage via the resistors R4 and R5. It is connected to the negative output terminal F of the supply device 5. The connection point of the resistors R4 and R5 is connected to the inverting terminal (-) of the inverting comparator 701 composed of an operational amplifier, and the non-inverting terminal (+) of the inverting comparator 701 is grounded via a resistor. The output side of the inverting comparator 701 is connected to the input side of the NOR circuit 702, while another terminal on the input side of the NOR circuit 702 is in a state requiring protection, such as an overcurrent state of the engine generator. Protection device 8 is connected to detect that a high level signal is output when a state requiring protection is detected.
It is supplied to the R circuit 702. The output side of the NOR circuit 702 is connected to the base of the transistor Q3 via the inverter 703 and the resistor R6. The emitter of the transistor Q3 is connected to the negative output terminal F of the constant voltage supply device 5, while the collector is connected to the positive output terminal E of the constant voltage supply device 5 via the resistor R7 and to the constant voltage via the capacitor C2. It is connected to the negative output terminal F of the supply device 5. The positive terminal of the capacitor C2 is connected to the base of the transistor Q4, the collector of the transistor Q4 is connected to the positive output terminal E of the constant voltage supply device 5, while the emitter is connected to the anode of the diode D2 and the thyristor control circuit. 6 is connected to a connection point K between the capacitor C1 and the resistor R1. The cathode of the diode D2 is connected to the positive terminal of the capacitor C2.

The bridge rectifier circuit 3, thyristor control circuit 6, and transient suppression circuit 7 constitute a DC voltage control circuit.

The output side of the smoothing circuit 4 is connected to the inverter circuit 9. The inverter circuit 9 is constituted by a bridge circuit composed of four FETs (field effect transistors) Q5 to Q8. FETQ
The drive signal circuits connected to the respective gate terminals of 5-Q8 will be described later.

The output side of the inverter circuit 9 is connected to output terminals 11 and 12 to which a load (not shown) is connected via an output circuit 10 composed of a low-pass filter.

Both ends of the output terminals 11 and 12 (both ends H of the capacitor constituting the low-pass filter) are connected to a detection circuit 13 including a dividing resistor and a differential amplifier. The detection circuit 13 is connected to the output terminal 1
By directly comparing the output voltage waveforms appearing at 1 and 12, the output waveform distortion or offset component is detected, and a detection signal is output.

Reference numeral 14 denotes a sine wave oscillator that generates a sine wave of a commercial frequency, for example, 50 Hz or 60 Hz. The output side of the sine wave oscillator 14 and the output side of the detection circuit 13 are connected to a differential amplifier 15. The differential amplifier 15 corrects the amplitude reference level of the sine wave output from the sine wave oscillator 14 with the detection signal output from the detection circuit 13 and outputs a corrected sine wave signal.

Reference numeral 16 denotes a rectangular wave oscillator, and the frequency of the rectangular wave oscillated by the rectangular wave oscillator 16 is set to a value significantly higher than the frequency of the sine wave output from the sine wave oscillator 14. The output side of the rectangular wave oscillator 16 is connected to an integrating circuit 17, which integrates the rectangular wave and converts it into a triangular wave signal.

The corrected sine wave signal output from the differential amplifier 15 and the triangular wave signal output from the integration circuit 17 are superimposed and supplied to the inverter buffer 18. Inverter buffer
Reference numeral 18 has a predetermined threshold (threshold level). When a signal having a level exceeding this threshold is input, a low-level signal is output, while a signal having a level lower than the threshold is input. Output a high-level signal to form a so-called pulse width modulation (PWM) signal.
For example, it is constituted by a C-MOS gate IC having a fixed threshold value for an input signal to a gate terminal.

The output side of the inverter buffer 18 is input to one input terminal of the NAND circuit 20 via the inverter 19 and is also directly input to one input terminal of the NAND circuit 21 as it is. The output terminal J of the NOR circuit 702 of the transient suppression circuit 7 is connected to the other input terminal of the NAND circuit 20 and the other input terminal of the NAND circuit 21.

Each output side of NAND circuits 20 and 21 is a circuit for FET gate drive signal
Connected to 22,23 respectively. The FET gate drive signal circuit 22 is composed of a push-pull amplifier, a surge absorbing diode, a low-frequency component cutting capacitor C3, and primary coils of pulse transformers A and C. Similarly, the FET gate drive signal circuit 23 is a push-pull circuit. It is composed of a pull amplifier, a diode for absorbing surge, a capacitor C4 for cutting low frequency components, and primary coils of pulse transformers B and D.

Secondary coil of pulse transformer A (inverter circuit 9
Are connected to the gate of the FET Q5 via an attenuation resistor, a demodulating capacitor C5, and bidirectional voltage regulating diodes D3 and D4. The secondary coils of the pulse transformers B, C, and D are also connected through the same circuit as the secondary circuit of the pulse transformer A.
Connected to each gate of FETQ6, Q7, Q8 respectively.

Next, the operation of the inverter-controlled engine generator configured as described above will be described.

The three-phase AC power output from the three-phase output winding 1 with the driving of the engine is rectified by the bridge rectifier circuit 3, smoothed by the subsequent smoothing circuit 4 and converted to DC power,
Fluctuations in the DC voltage in the smoothing circuit 4 are detected by the thyristor control circuit 6 via the resistors R2 and R3, and the amount of current flowing through each thyristor of the bridge rectifier circuit 3 is controlled based on the detection signal. The feedback control is performed such that the output voltage is maintained at a predetermined DC voltage stably. The thyristor control circuit 6 includes a transient control circuit 7
The operation of the thyristor control circuit 6 and the bridge rectifier circuit 3 based on this signal will be described later in detail.

The gates of the FETs Q5 and Q7 and the FETs Q6 and Q8 of the inverter circuit 9 receive a pulse width modulation signal (PWM) signal described later,
By switching the FETs Q5 and Q7 and the FETs Q6 and Q8 alternately in response to the PWM signal, the DC output of the smoothing circuit 4 is switching-controlled and output to the output circuit 10. The output circuit 10 cuts high frequency components and outputs AC power of the commercial frequency to the output terminal 1.
Supply the load from 1,12.

The detection circuit 13 compares the waveform of the output voltage appearing at the output terminal 11 with the waveform of the output voltage appearing at the output terminal 12, and detects the difference, that is, the distortion or offset component of the output voltage waveform. Output to the dynamic amplifier 15.

The differential amplifier 15 compares the sine wave signal of the commercial frequency output from the sine wave oscillator 14 with a feedback signal including a waveform distortion or a DC offset component of the output voltage output from the detection circuit 13, and The amplitude reference level of the sine wave signal is corrected by the feedback signal, and the corrected sine wave signal is output.

The square wave signal output from the square wave oscillator 16 is integrated by an integrating circuit.
It is integrated at 17 and converted to a triangular wave signal. The triangular wave signal and the corrected sine wave signal from the differential amplifier 15 are superimposed to form a superimposed signal, which is input to the inverter buffer 18. The inverter buffer 18 outputs a low-level signal when the superimposed signal exceeds the threshold value, and outputs a high-level signal when the superimposed signal is equal to or less than the threshold value. As a result, a pulse width modulated PWM signal is output. This PWM signal is
Since it is formed based on the corrected sine wave signal, it is possible to reduce the distortion and the offset component of the output voltage, and the response time of the comparator (about 1 μse
Inverter buffer much faster than c) (about 50nsec)
Can be used to form a PWM signal, so that the frequency of the carrier can be made higher, thereby making it possible to supply higher quality AC power whose output waveform approximates a sine wave.

One of the PWM signals output from the inverter buffer 18 is inverted by the inverter 19 and input to the NAND circuit 20, and the other is input to the NAND circuit 21 as it is. A low level signal is supplied to the NAND circuits 20 and 21 from the transient suppression circuit 7 when a state requiring protection such as an overcurrent state is detected or a low rotation state such as when starting an engine is detected. Sometimes, the outputs of the NAND circuits 20 and 21 become high level signals regardless of the PWM signal, and the PWM signal is not transmitted because this state is continued. On the other hand, when a state requiring protection is not detected and the engine speed is not low, a high-level signal is supplied from the transient suppression circuit 7, and at this time, the NAND circuits 20, 21
Outputs an inverted signal of the inverted or non-inverted PWM signal according to the input inverted or non-inverted PWM signal, respectively.
The gate drive signal circuit 22 is supplied with a PWM signal, and the FET gate drive signal circuit 23 is supplied with an inverted PWM signal.

In the FET gate drive signal circuit 22, the PWM signal is push-pull amplified, and then the low frequency component, that is, the commercial frequency component is cut by the capacitor C3. The signal immediately before passing through the capacitor C3 is a PWM signal having a constant amplitude with respect to the reference level, and the average voltage (integral value) of this signal changes in the same cycle as the sine wave from the sine wave oscillator 14. Therefore, this PWM signal contains the same frequency (commercial frequency) component as the sine wave. After this PWM signal passes through the capacitor C3, the entire pulse train goes up and down in a phase opposite to the commercial frequency component and is converted into a pulse signal train whose average voltage is always zero.

Since a pulse signal train whose average voltage is always zero is supplied to each primary coil of the pulse transformers A and C, the transformer cores constituting the pulse transformers A and C are hardly affected by magnetic saturation due to commercial frequency components. Therefore, the transformers A and C can be configured with a small size that does not cause magnetic saturation at the PWM carrier frequency.

The operation of the FET gate drive signal circuit 23 is exactly the same as the operation of the FET gate drive signal circuit 22 described above.

The pulse signal output from the secondary coil of the pulse transformer A is compared with the breakdown voltage of the Zener diodes D3 and D4, and the capacitor exceeding the breakdown voltage is charged and discharged by the capacitor C5. An average voltage (which has a commercial frequency) due to the excess of.
Therefore, between the gate and source of the FET Q5, a signal in which the voltage across the capacitor C5 having the commercial frequency and the pulse signal output from the secondary coil of the pulse transformer A are superimposed,
That is, the PWM signal before passing through the capacitor C3 is demodulated. FET
Q5 conducts only while the positive pulse of the PWM signal is being input to the gate.

The pulse signal output from the secondary coil of the pulse transformer C is processed in exactly the same manner as the pulse signal output from the secondary coil of the pulse transformer A, and the conduction of the FET Q7 is determined by the FET Q5.
Is performed at the same timing as the conduction.

The pulse signals output from the secondary coils of the pulse transformers B and D are processed in exactly the same manner as the pulse signals output from the secondary coils of the pulse transformers A and C. However, since the phases of the PWM signals input to the pulse transformers B and D and the PWM signals input to the pulse transformers A and C are opposite, when the FETs Q5 and Q7 are turned on, the FETs Q6 and Q8 are turned off, and conversely, the FET Q5 is turned off. , Q7
Is turned off, the FETs Q6 and Q8 operate to conduct.

As described above, the sine wave of the commercial frequency, which is feedback-corrected based on the output waveform, is pulse-width-modulated by the high-frequency triangular wave, and the inverter circuit 9 performs switching control based on the pulse-width-modulated signal. The carrier frequency component is cut off, and AC power having a commercial frequency that approximates a sine wave is supplied from the output terminals 11 and 12 to the load.

A more detailed description of the configuration and operation of the inverter circuit 9 and the detection circuit 13 to the FET gate drive signal circuit 23 has already been described in the inverter device filed on Nov. 13, 1990 by the present applicant. I have.

 Next, the operation of the transient suppression circuit 7 according to the present invention will be described.

Immediately after the start of the engine, the output voltage of the alternator is low, so the voltage at the input terminal of the constant voltage circuit 5a constituting the constant voltage supply device 5 is low.
(Corresponding to the set value of the engine speed set to a value lower than the speed at the time of rated operation), and the Zener diode D1 is non-conductive. Therefore, the inverting terminal (-) of the inverting comparator 701 is at a low level, and the output of the inverting comparator 701 is at a high level.

The NOR circuit 702 outputs a low-level signal when a high-level signal is input to at least one of the input sides.
Is at a low level by the high level output of the inverting comparator 701 or the high level output of the protection device 8.

This low-level signal is inverted by the inverter 703 to become a high-level signal, and conducts the transistor Q3 to turn on the capacitor.
Discharge C2. Therefore, the transistor Q4 is turned off, and the potential at the connection point K between the capacitor C1 and the resistor R1 becomes low.

Therefore, the transistor Q1 of the thyristor control circuit 6 is turned off, the transistor Q2 is turned on, and a low level signal is supplied to the gate of each thyristor of the bridge rectifier circuit 3. Thus, each thyristor does not conduct, and the bridge rectifier circuit 3 does not supply a rectified output. That is, when the engine speed is equal to or less than the set value or when a state requiring protection is detected, the bridge rectifier circuit 3 does not supply a rectified output. Is suppressed, and the output supply when a state requiring protection such as an overcurrent state due to an overload is detected is also stopped.

Next, after the engine is started, the output voltage of the alternator gradually increases, the voltage at the input terminal of the constant voltage circuit 5a increases, and exceeds the breakdown voltage of the Zener diode D1, that is, the engine speed decreases to the set value. When it exceeds, the Zener diode D1 becomes conductive, the inverting terminal (-) of the inverting comparator 701 turns to high level, and the output of the inverting comparator 701 goes to low level.

At this time, if a condition requiring protection has not been detected,
The output of the NOR circuit 702 changes to a high level, and the output of the inverter 703 changes to a low level. Therefore, the transistor Q3 is turned off, and the capacitor C2 starts charging through the resistor R7. By this charging, the positive electrode side potential of the capacitor C2 gradually increases based on a time constant determined by the capacitance of the capacitor C2 and the resistance value of the resistor R7. The transistor Q4 is turned on by the rise of the positive electrode potential of the capacitor C2.
If the emitter potential of the transistor Q4 rises due to the conduction of Q4 and becomes higher than the base potential of the transistor Q4, the transistor Q4 turns off, so that the potential at the point K is slightly lower than the potential on the positive electrode side of the capacitor C2. The value will always be maintained. That is, the potential at the point K gradually increases based on the time constant determined by the capacitance of the capacitor C2 and the resistance value of the resistor R7 after the engine speed exceeds the set value.

Accordingly, the base-emitter voltage of the transistor Q1 gradually increases, the transistor Q1 gradually conducts, the transistor Q2 gradually becomes non-conductive, and the gate voltage input to each thyristor of the bridge rectifier circuit 3 gradually increases. Accordingly, the amount of current flowing through each thyristor gradually increases. Finally, the potential at the point K substantially reaches the positive output potential of the constant voltage supply device 5, and the gate voltage of each thyristor is controlled by a predetermined feedback control for maintaining the potential at the connection point between the resistors R1 and R2 at a predetermined value. Leads to the input value. That is, the set value of the gate signal input to each thyristor is gradually increased from zero to reach the feedback control input value during normal operation.

Thus, even when the engine is started, the output terminals 11, 12
It is possible to prevent a sudden current from entering each thyristor of the bridge rectifier circuit 3 even when the load remains connected to the thyristor. At the same time, by controlling the gate voltage input to each thyristor of the bridge rectifier circuit 3 to gradually increase, the DC output of the smoothing circuit 4 gradually increases after the start of the engine, whereby each of the inverter circuits 9 A sudden voltage change is prevented from being applied to the FET. The effect of such prevention increases as the load connected to the output terminals 11 and 12 increases when the engine starts.
Particularly when the load is in a short-circuit state, the effect of suppressing the adverse effect on the thyristor and the FET is extremely large.

(Effect of the Invention) As described in detail above, the present invention includes an engine, a generator driven by the engine, and a thyristor bridge circuit, and rectifies an AC output of an output winding of the generator to obtain a predetermined output. In a DC voltage control circuit that maintains a DC voltage, and an inverter control type engine generator having an inverter circuit that converts output power from the DC voltage control circuit into AC output power of a predetermined frequency, the DC voltage control circuit includes: When the number of revolutions of the engine is equal to or less than a set value set to a value lower than the number of revolutions at the time of rated operation, feedback control for maintaining the predetermined DC voltage by feeding back a rectified output voltage to the thyristor bridge circuit is prohibited. So that the rectified output is not supplied to the inverter circuit, and the engine speed exceeds the set value. Since the feedback control is soft-started from this time, the amount of conduction current of the thyristor bridge circuit is gradually increased to reach the predetermined DC voltage. Since the operation can be suppressed and the sharp rise of the output voltage is suppressed,
Even if the starting operation is performed while the load is connected to the output terminal, the transient load on each power element can be greatly reduced, and the cause of deterioration of each power element can be eliminated.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an inverter-controlled engine generator according to the present invention. 1,2 …… Three-phase output winding, single-phase auxiliary winding (generator), 3,6,7
...... Bridge rectifier circuit, thyristor control circuit, transient suppression circuit (DC voltage control circuit), 9 ... inverter circuit.

Continuation of the front page (56) References JP-A-47-43910 (JP, A) JP-A-57-206275 (JP, A) JP-A-2-142398 (JP, A) JP-A-59-28899 (JP) JP-A-51-56916 (JP, A) JP-A-62-191392 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H02M 7/42-7/98 H02P 9/00-9/48

Claims (2)

(57) [Claims] 1. A DC voltage control circuit including an engine, a generator driven by the engine, and a thyristor bridge circuit for rectifying an AC output of an output winding of the generator to maintain a predetermined DC voltage. An inverter circuit that converts the output power from the DC voltage control circuit into AC output power of a predetermined frequency, wherein the DC voltage control circuit operates when the engine speed is at rated operation. When the speed is equal to or less than a set value set to a value lower than the rotation speed, the rectified output voltage is fed back to the thyristor bridge circuit to inhibit feedback control for maintaining the predetermined DC voltage, and the rectified output is supplied to the inverter circuit. And the feedback control is started when the engine speed exceeds the set value. Inverter-controlled engine generator characterized by configured to occupy reach up to the predetermined DC voltage is gradually increased conduction current of the thyristor bridge circuit by soft start. 2. The DC voltage control circuit is configured to gradually increase a gate input signal of the thyristor bridge circuit to a predetermined feedback control input value after the engine speed exceeds the set value. The inverter-controlled engine generator according to claim 1, wherein: