JP2688661B2 - Inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device,
In particular, the present invention relates to a pulse width modulation type inverter device used for a portable AC power supply device or the like.

[0002]

2. Description of the Related Art In recent years, an inverter device has been increasingly used in a portable AC power supply device to stabilize an output frequency. For example, an AC generator driven by an engine has a commercial frequency. In a portable power supply device that outputs AC power, a high-power AC current is obtained from a generator by operating an engine in a high rotational speed region, and this AC current is temporarily converted to DC, and then commercialized by an inverter device. A device which converts the frequency into an alternating current and outputs it is known from Japanese Utility Model Application Laid-Open No. 59-132398.

By the way, in such an AC power supply device, there is a demand for the output waveform to be as close as possible to a sine wave depending on its application. In order to meet this demand, a pulse modulation (PWM) method is applied to the inverter device. The adopted AC power supply device is also under study (Japanese Patent Laid-Open No. 82098/60).

In such an AC power supply device, generally, the output voltage is detected, feedback control is performed based on the detected value, and the output voltage is maintained at a predetermined value. For example, as disclosed in Japanese Unexamined Patent Publication No. 63-167677, an output voltage is detected through a transformer and feedback control is performed based on the detected value, or an R circuit is provided in front of an output circuit including a low pass filter.
The C filter is inserted, the inverter output voltage is detected from the child RC filter, and feedback control is performed based on this inverter output.

[0005]

However, in the above conventional method, in the former method of detecting the output voltage through the transformer, when the output voltage is offset,
The offset component cannot be detected, and therefore the output voltage offset component cannot be feedback-corrected. Further, in the latter method of detecting the inverter output voltage from the RC filter, it is necessary to intervene means such as insulation transmission and modulation transmission when the feedback correction signal is taken out from the detection voltage. Therefore, the feedback signal is collapsed or the residual offset is generated. The processing for the problem of becomes complicated.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an inverter device capable of accurately correcting waveform distortion of an output voltage and DC offset of the output voltage.

[0007]

In order to achieve the above object, the present invention provides a switching device for switching control of the output of a DC power supply circuit, a sine wave output circuit for outputting a sine wave reference signal of a predetermined frequency, and A pulse width modulation circuit for pulse width modulating a sine wave reference signal to output a PWM signal, a switching control circuit for switching the switching device based on the PWM signal output from the pulse width modulation circuit, and the switching device And an output circuit connected to the output circuit for outputting sinusoidal AC power through a pair of output lines,
A detection circuit that detects a relative voltage difference between the pair of output lines, and an offset DC component of the relative voltage difference signal is extracted, amplified, and fed back to the sine wave reference signal to obtain the sine wave reference signal. A first waveform correction circuit for offset correction and an AC component of the relative voltage difference signal are fed back to the sine wave reference signal to correct the sine wave reference signal and supply it to the pulse width modulation circuit. A second waveform correction circuit that corrects the AC power waveform so as to approximate it to a sine wave is provided.

[0008]

The relative voltage difference between the output lines is detected, the offset correction of the sine wave reference signal is performed in accordance with the offset DC component of the relative voltage difference signal, and the AC component of the relative voltage difference signal is determined in accordance with the offset component. Thus, the sine wave reference signal after the offset correction is corrected. The corrected sinusoidal reference signal is supplied to the pulse width modulation circuit. In the pulse width modulation circuit, the corrected sine wave reference signal is pulse width modulated and output as a PWM signal, and the switching device operates the switching device based on this PWM signal to control switching of the input DC current. As a result, the AC output voltage of the output circuit is corrected so that the distortion of the waveform, the amount of DC offset, etc. are reduced and the AC output voltage approaches the sine wave.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

1 to 5 are overall configuration diagrams of a portable AC power supply device using an inverter device according to the present invention,
In FIG. 1, 1 and 2 are output windings independently wound around a stator of an AC generator, 1 is a three-phase output winding, and 2 is a single-phase auxiliary winding. Further, a magnetic pole of a multi-pole permanent magnet is formed on a rotor (not shown), and the rotor is configured to be rotationally driven by an engine (not shown). The output terminal of the three-phase output winding 1 has three thyristors and three
The output terminal of the bridge rectifier circuit 3 is connected to the smoothing circuit 4. And this bridge rectification circuit 3 and smoothing circuit 4
The DC power supply circuit is composed of and.

The output terminal of the single-phase auxiliary winding 2 is connected to a constant voltage supply device 5 having positive and negative output terminals E and F. The constant voltage supply device 5 is composed of two sets of a rectifying circuit, a smoothing circuit, and a constant voltage circuit 5a. For a current from the single-phase auxiliary winding 2 in one direction, each circuit of one set works, and For the current in the opposite direction, each circuit of the other set works,
As a result, positive and negative constant voltages are output to the output terminals E and F, respectively.

A thyristor control circuit 6 has one end on the power input side connected to the positive output terminal E of the constant voltage supply device 5 and the other end grounded together with the positive terminal on the smoothing circuit 4. The signal input terminal of the thyristor control circuit 6 is connected to the negative terminal of the smoothing circuit 4, and the signal output terminal is connected to the gate input circuit of each thyristor of the bridge rectifier circuit 3.

Therefore, the three-phase AC power output from the three-phase output winding 1 is rectified by the bridge rectifier circuit 3, smoothed by the smoothing circuit 4 and converted to DC power, and the DC power in the smoothing circuit 4 is also converted. A thyristor control circuit 6 detects a voltage fluctuation, and feedback control such that the output voltage of the smoothing circuit 4 is stably maintained by controlling the conduction angle of each thyristor of the bridge rectifier circuit 3 based on the detection signal. Has been done.

For a detailed description of the control operation by the thyristor control circuit, see the Japanese Patent Application No. 1-23 of the present applicant.
No. 0908 and Japanese Utility Model Application No. 1-85360, and will not be described here.

Next, the inverter device will be described with reference to FIG.

The output terminal of the smoothing circuit 4 is connected to the inverter 7. The inverter 7 is configured by a bridge circuit including four FETs (field effect transistors) Q1 to Q4, which are switching devices. A drive signal circuit is connected to each gate terminal of the FETs Q1 to Q4, which will be described later.

The output terminal of the inverter 7 (FETQ1, Q4
And the connection points of the FETs Q2 and Q3) are connected to output terminals 9 and 9'to which loads (not shown) are connected via the output lines 7a and 7b and the low-pass filter 8.
The low pass filter 8 includes coils L1 and L2 for the load.
Are connected in parallel so that they are connected in series, and by passing an alternating current of a low frequency component (commercial frequency in this embodiment) of the output of the inverter 7, the output terminals 9 and 9 are connected. ′ Is configured to supply commercial frequency power to the load.

The output lines 7a and 7b are respectively connected to one end of the series circuit of the resistors R1 and R2 and the series circuit of the resistors R3 and R4 shown in FIG. On the other hand, the other ends of these resistor series circuits are connected to the positive electrode output terminal E of the constant voltage supply device 5. The connection points of the resistors R1 and R2 and the connection points of the resistors R3 and R4 are connected to the plus side input terminal and the minus side input terminal of the differential amplifier 101 through the resistors R10 and R11, respectively, and the above two connections are made. A capacitor C2 for cutting high frequency components is connected between the points. The positive input terminal of the operational amplifier forming the differential amplifier 101 is grounded via a capacitor C3 for cutting high frequency components.
The resistors R1 to R4, the capacitor C2, the differential amplifier 1
01 constitutes a detection circuit. Differential amplifier 101
Output is low-pass filter circuit 121 and differential amplifier 1
03 is connected to the positive side input.

The low-pass filter circuit 121 includes an operational amplifier, resistors R21 to R24, capacitors C11 and C12.
Composed of This circuit has a cutoff frequency of 5 Hz
The resistance value and the capacitance value of the capacitor are set so that they are about the same, and only the DC component of the input signal is output. The output of the low pass filter circuit 121 is connected to the positive side input terminal of the differential amplifier 122.

In the present embodiment, the low pass filter circuit 12
1 and the differential amplifier 122 configure a first waveform correction circuit, and the differential amplifier 103 configures a second waveform correction circuit.

Reference numeral 102 is a sine wave oscillator for generating a sine wave having a commercial frequency, for example, 50 Hz or 60 Hz. The output of the sine wave oscillator 102 is connected to the negative side input terminal of the differential amplifier 122. The output of the differential amplifier 122 is
It is connected to the negative side input terminal of the differential amplifier 103.

Reference numeral 104 denotes a rectangular wave oscillator, and the period of the rectangular wave oscillated by the rectangular wave oscillator 104 is set to a value larger than about 50 nsec which is a response time of the inverter buffer 106 described later. This value is much faster than the response time of the conventional comparator, which is about 1 μsec. Therefore, the frequency of the rectangular wave can be set significantly higher than the frequency of the conventional PWM carrier wave (triangular wave).

The output terminal of the rectangular wave oscillator 104 is an integrating circuit 1
05. The output end of the integrating circuit 105 and the output end of the differential amplifier 103 are connected to each other to form a superimposed signal forming circuit, and are connected to the inverter buffer 106 of FIG. The inverter buffer 106 has a predetermined threshold value (threshold level), outputs a low level signal when a signal having a level exceeding the threshold value is input, and outputs a signal having a level lower than the threshold value. When a signal is input, it outputs a high level signal, and is composed of a buffer IC having a fixed threshold value with respect to an input signal from its gate terminal, for example, having a CMOS gate threshold level. To do.

The output end of the inverter buffer 106 is NA
It is connected to one input end of the ND circuit 107.

The output terminal of the rectangular wave oscillator 104 is further connected to a differentiating circuit 110 via an inverter buffer 108 and a differentiating circuit 11 via a double inverter buffer 109.
1 is connected to each. The differentiating circuit 110 includes a coupling capacitor C4 provided between an input end and an output end,
It is composed of a parallel circuit of a diode D1 (with the anode facing the negative output terminal F side) provided between the output end of the capacitor C4 and the negative output terminal F of the constant voltage supply device 5 and a resistor R5. The differentiating circuit 111 is also different from the differentiating circuit 110.
Coupling capacitor C arranged in exactly the same manner as
5, a diode D2, and a resistor R6.

The output terminal of the differentiating circuit 110 is connected to the other input terminal of the NAND circuit 107 via the inverter buffer 112. An output terminal of the NAND circuit 107 is connected to one input terminal of the NAND circuit 114. Differentiating circuit 111
Is connected to the other input terminal of the NAND circuit 114 via the inverter buffer 113.

The output terminal of the NAND circuit 114 passes through the double inverter buffer 115 of FIG.
It is connected to a push-pull amplifier 116 composed of Q5 and Q6. The collector of the transistor Q5 of the push-pull amplifier 116 is connected to the negative output terminal F of the constant voltage supply device 5.

The output terminal of the push-pull amplifier 116 (the connection point between the emitters of the transistors Q5 and Q6) is connected to the connection point between the anode of the diode D3 and the cathode of the diode D4. The cathode of the diode D3 is connected to the positive output terminal E of the constant voltage supply device 5, and the anode of the diode D4 is connected to the negative output terminal F of the constant voltage supply device 5. The diodes D3 and D4 are for absorbing a surge generated in a pulse transformer described later.

The anode of the diode D3 and the diode D
The connection point with the cathode of 4 is connected to one end of each of the primary side coils L3 and L4 of the pulse transformers A and C via a capacitor C6 for cutting low frequency components. The other end of each of the primary side coils L3 and L4 is connected to the negative electrode output terminal F of the low voltage supply device 5. The capacitor C6 has a high frequency P
A constant value is set so that only the WM carrier frequency signal is passed and low frequency components are not passed.

The output terminal of the NAND circuit 114 is connected to the push-pull amplifier 118 composed of the transistors Q7 and Q8 after passing through the inverter buffer 117 of FIG. 5, and the output terminal of the push-pull amplifier 118 is the anode of the diode D5. And the cathode of the diode D6. This connection point is the capacitor C described above.
Similar to 6, the capacitor C is set to a constant value so that only the PWM carrier frequency signal is passed and low frequency components are not passed.
Through the primary side coil L5 of the pulse transformers B and D
It is connected to each end of L6.

Returning to FIG. 2, the drive signal circuit connected to each gate terminal of the FETs Q1 to Q4 will be described. One end on the secondary side of the pulse transformer A is connected to the gate terminal of the FET Q1 via a resistor R7, a capacitor C8 for demodulation, and a parallel circuit of the resistor R8 and a diode D7, while the other end on the secondary side of the pulse transformer A is connected. Is connected to the source terminal of FET Q1. The connection point between the capacitor C8 and the parallel circuit including the resistor R8 and the diode D7 is connected to the other end of the secondary side of the pulse transformer A via the Zener diodes D8 and D9. The anode of the diode D7 is F
The gate terminals of ETQ1 are connected, and the Zener diodes D8 and D9 are connected such that their anodes face each other.

The secondary side of each pulse transformer B, C, D,
Also between the corresponding FET Q2-Q4 gate terminals,
A circuit exactly the same as the circuit provided between the secondary side of the pulse transformer A and the gate terminal of the FET Q1 is provided.

The inverter device configured as described above (the inverter 7, the low-pass filter 8, and FIGS. 3 to 5)
The operation of the circuit device) will be described in detail below with reference to the signal waveforms shown in FIGS.

FETs Q1, Q3 and FE of the inverter 7
A pulse width modulation (PWM) signal to be described later is input to the gate terminals of TQ2 and Q4.
The output of the smoothing circuit 4 is switched and output to the low-pass filter 8 by alternately conducting the ETQ1 and Q3 and the FETs Q2 and Q4. The low-pass filter 8 cuts high-frequency components and supplies AC power of commercial frequency to the load from the output terminals 9 and 9 '.

The output voltage appearing on the output line 7a and the output voltage appearing on the output line 7b (the waveforms of these output voltages are PWM waveforms as shown in FIG. 6C) are respectively divided by the voltage dividing resistors R1 and R2. After passing through R3 and R4, the connection point between the capacitor C2 and the resistor R10 and the capacitor C2
PW by the capacitor C2 at the connection point between the resistor and the resistor R11.
A signal from which the carrier frequency of the M signal has been removed, that is, an AC signal similar to the AC output voltage of the output terminals 9 and 9'appears, and these two AC signals are compared by the differential amplifier 101. That is, it is detected as an AC signal (AC signal having an average level corresponding to the waveform distortion or the offset component) that includes the waveform distortion or the offset component of the output voltage, and the detected signal is amplified to obtain the low-pass filter circuit 121 and the differential signal. Output to the amplifier 103. Output line 7
Since the output voltages appearing at a and 7b are directly compared with each other, the distortion of the output voltage waveform can be accurately detected. The capacitors C2, C3, and C4 remove the high-frequency component (including the carrier component of the PWM signal) from the difference signal and also remove the disturbance applied to the differential amplifier 103. By detecting the offset component of the AC output voltage by directly comparing the voltages of the output lines 7a and 7b in this way, the change in the phase lead due to the external load is detected more than when it is detected from the output terminals 9 and 9 '. Since the feedback system for removing the offset component is stabilized and the feedback gain of this feedback system is increased, the sine waveform of the AC output voltage can be made more accurate including the level. Become.

In the detection circuit of FIG. 3, the value of R1: the value of R2 = the value of R3: the value of R4 and the values of the resistors R10 to R14 are set to appropriate values.
It is possible to faithfully detect the offset component and the waveform distortion from the PWM signals of the output lines 7a and 7b.

The differential amplifiers 103 and 122 and the low-pass filter circuit 121 correspond to the sine wave signal of the commercial frequency output from the sine wave oscillator 102, and the waveform distortion or DC offset of the output voltage output from the differential amplifier 101. Is configured based on a feedback signal that includes a sine wave signal of the commercial frequency whose amplitude reference level is corrected so that the output voltage waveform approaches the sine wave (see FIG. b ″)) is output from the differential amplifier 103. Since a PWM signal is generated based on this corrected sine wave signal as described later, variations in the threshold value of the inverter buffer 106,
It is possible to reduce the distortion of the waveform of the output voltage and the DC offset component that occur due to variations in the temperature characteristics of various components and to make the output waveform closer to a sine wave.

Here, the first waveform correction circuit consisting of the low-pass filter circuit 121 and the differential amplifier 122 extracts and amplifies the DC component (low frequency component) of the output signal (relative voltage difference signal) of the differential amplifier 101. Sine wave oscillator 10
By performing feedback to the output signal 2 (sine wave reference signal), offset correction of the sine wave reference signal is performed.
Thereby, the DC offset component of the output voltage can be reduced. On the other hand, the differential amplifier 103, which is the second waveform correction circuit, feeds back the relative voltage difference signal containing the AC component (high-frequency component) to the output signal of the differential amplifier 122 as it is, to thereby obtain the sine wave reference signal. Make a correction. Thereby, the waveform distortion of the output voltage can be reduced. By providing the two waveform correction circuits in this way, the following effects are achieved.

That is, when the first waveform correction circuit is not provided, it is necessary to strongly perform feedback control for offset correction of the direct current component, that is, to considerably increase the gain of the second waveform correction circuit. However, since the gain of the high frequency component also increases, the possibility of abnormal oscillation increases. Further, if the frequency of the signal to be fed back is lowered, the effect of waveform correction will be greatly reduced. On the other hand, with the configuration of the present invention, while properly maintaining the gain of the high frequency component,
By setting the gain of the feedback control of the direct current component (low frequency component) to be large, the waveform distortion of the output voltage and the direct current offset can be further reduced.

The rectangular wave signal (FIG. 7A) output from the rectangular wave oscillator 104 is integrated by the integrating circuit 105 to form a triangular wave signal (FIGS. 6B 'and 7B'). . This triangular wave signal and the corrected sine wave signal b ″ from the differential amplifier 103 are superposed to form a superposed signal b (see FIG. 6).
(B)) is formed and input to the inverter buffer 106. Inverter buffer 106 outputs a low level signal when a signal having a level exceeding a threshold value (the level shown by the broken line in FIG. 6B) is input, and outputs a signal having a level below the threshold value. A high level signal is output (FIG. 6 (c)). This output pulse train signal c
Is a pulse width modulation (PW) pulse width modulated by the sine wave signal b ″ using the triangular wave signal of FIG.
M) signal. Next, from this pulse width modulation signal c to N
An explanation will be given up to the output signal i of the AND circuit 114. In the description of this portion, the PWM signal is simplified and shown with the same pulse width as shown in FIG.

The rectangular wave signal (FIG. 7 (a)) output from the rectangular wave oscillator 104 is inverted by the inverter buffer 108 and then differentiated by the differentiating circuit 110.
The signal becomes as shown in (d). That is, when the rectangular wave signal (FIG. 7A) falls, it passes through the resistor R5 and the capacitor C.
4 is charged and the positive differential output shown in FIG. 7D appears, and at the rising time, the capacitor C4 passes through the diode D1.
Is discharged and a differential output on the negative side appears.

The output signal from the differentiating circuit 110 is inverted and amplified by the inverter buffer 112 with reference to the threshold value (the level shown by the broken line in FIG. 7 (d)) and becomes a signal as shown in FIG. 7 (e). . The output signal of the inverter buffer 112 (FIG. 7E) and the output signal of the inverter buffer 106 (FIG. 7C) are input to the NAND circuit 107, and the NAND circuit 107 outputs the signal shown in FIG. 7B. Output.

Further, the rectangular wave signal (FIG. 7 (a)) output from the rectangular wave oscillator 104 passes through two inverter buffers 109 and is then differentiated by the differentiating circuit 111, as shown in FIG. 7 (f). It becomes a signal like this. The signal that has been subjected to the differential processing is thresholded by the inverter buffer 113 (see FIG.
The signal is inverted and amplified with reference to the level indicated by the broken line in (f) to obtain a signal as shown in FIG. The signal processing operation in the differentiating circuit 111 and the inverter buffer 113 is the same as the operation in the differentiating circuit 110 and the inverter buffer 112 described above.

To the NAND circuit 114, the NAND circuit 1
07 output signal (FIG. 7 (h)) and the inverter buffer 1
13 output signal (Fig. 7 (g)) is input, and NAND
The circuit 114 outputs a signal as shown in FIG.

By the way, as described above, the output terminal 9,
When the output voltage waveform is distorted due to the influence of the load connected to 9 ', feedback control is performed so that this output waveform approaches a sine wave. In the case where a very large waveform distortion occurs temporarily, as in the case, the sine wave signal output from the differential amplifier 103 (see FIG.
The amplitude of (b ″)) may be larger than the amplitude of the triangular wave signal because it is corrected by the feedback signal from the differential amplifier 101. As a result, the level of the superimposed signal (FIG. 6 (b)). Is continuously deviated from the threshold value (the level shown by the broken line in FIG. 6B) (does not intersect with the threshold value), the output of the inverter buffer 106 remains at a high level during this period (the superimposed signal The maximum value is less than or equal to the threshold value) or remains at a low level (minimum value of the superimposed signal is greater than or equal to the threshold value), and DC output occurs, so that signal transmission cannot be performed by the pulse transformer. In the above configuration, the output signals of the inverter buffers 112 and 113 are configured so as not to cause such a problem.This operation will be described below.

For example, when the level of the output signal c of the inverter buffer 106 remains high (FIG. 8).
(C)) Even in this case, the output signals of the inverter buffers 112 and 113 are the same as those in the case where the signal c changes as shown in FIGS. 8E and 8G. The width is the inverter buffer 11
8 (h) by being limited by the pulse width of the output signal e of FIG.
(I).

On the other hand, when the output of the inverter buffer 106 remains at the low level (FIG. 9C), the output signals of the inverter buffers 112 and 113 are still as shown in FIGS. 9E and 9G. As in the case where the signal c changes, the output signal of the NAND circuit 107 is as shown in FIG.
As shown in FIG. 9H, the pulse width of the output signal of the NAND circuit 114 is limited by the pulse width of the output signal g of the inverter buffer 113 and becomes as shown in FIG. Therefore, even when a large distortion or offset of the waveform of the output voltage occurs, the pulse train with the minimum pulse width (FIG. 8 (i) or FIG. 9 (i)) is used as the PWM signal in the NAND circuit 1.
Continues to be output from 14. By this fail-safe processing, the inverter can be continuously operated.

Next, the PWM signal output from the NAND circuit 114 will be described. This PWM signal is
After passing through two inverter buffers 115 in series, it is push-pull amplified by a push-pull amplifier 116 and then supplied to a capacitor C6 for cutting low frequency components. The signal immediately before passing through the capacitor C6 is a PWM signal whose amplitude is constant with respect to the reference level, but the average voltage (integral value) of this signal changes in the same cycle as the sine wave from the sine wave oscillator 102. Therefore, this PWM signal contains the same frequency (commercial frequency) component as the sine wave.

Since the capacitor C6 does not pass the low frequency signal, that is, the commercial frequency signal in this embodiment, but only the PWM carrier frequency signal which is a high frequency signal, after the PWM signal passes through the capacitor C6, FIG. As shown in, the entire pulse train goes up and down in reverse phase to the commercial frequency component, and is converted into a pulse signal train in which the average voltage is always zero. The pulse signal train whose average voltage is always zero is the pulse transformer A,
It is supplied to each of the primary coils L3 and L4 of C. Therefore, the transformer cores forming the pulse transformers A and C have almost no adverse effect of magnetic saturation due to the commercial frequency component,
It is possible to use a small size that does not cause magnetic saturation at the PWM carrier frequency.

The pulse signal output from the secondary coil of the pulse transformer A (substantially the same as the signal shown in FIG. 6 (j)) is
Zener diodes D8 and D that are bidirectional voltage regulation circuits
9 is compared with each breakdown voltage, and when the output pulse signal exceeds each breakdown voltage in the positive polarity direction or the negative polarity direction, the Zener diode D8 or D9 conducts to regulate the voltage of the output pulse signal, and the capacitor C8. Are charged and discharged, and an average voltage (which has a commercial frequency) due to the output pulse signal exceeding each breakdown voltage in the positive polarity direction or the negative polarity direction appears across the capacitor C8. Therefore, between the gate and the source of the FET Q1, a signal in which the voltage across the capacitor C8 having the commercial frequency and the pulse signal output from the secondary coil of the pulse transformer A are superimposed, that is, the PWM signal before passing through the capacitor C6 ( FIG. 6C) is demodulated. The FET Q1 conducts while the positive pulse signal of the PWM signal is being input to the gate terminal.

The constant of the capacitor C8 is FETQ1.
A sufficiently large value is selected for the gate capacitance of the resistor R7, and the constant of the resistor R7 is selected so that the pulse transformer A and the capacitor C8 do not resonate at Q. Resistor R8 is F
The diode D7 adjusts the switching speed of the ETQ1, and when the voltage applied to the gate terminal of the FET Q1 drops, the diode D7 rapidly discharges the electric charge accumulated in the gate capacitance of the FET Q1 until then.
This is for immediately turning off Q1.

The pulse signal output from the secondary coil of the pulse transformer C is processed in exactly the same manner as the pulse signal output from the secondary coil of the pulse transformer A described above, and therefore F
The switching of the ETQ3 is performed at the same timing as that of the FET Q1. Therefore, when the positive pulse of the PWM signal is input, the FETs Q1 and Q3 are rendered conductive and the DC current is supplied from the smoothing circuit 4 to the low pass filter 8.

Next, the PWM signal output from the NAND circuit 114 is passed through the inverter buffer 117, and then subjected to the same signal processing as the signal circuit from the push-pull amplifier 116 to the FETs Q1 and Q3, and the FETs Q2 and Q3.
4 is switching-controlled according to this PWM signal.
However, since the PWM signal passes through the inverter buffer 117, the PWM signal is transmitted from the push-pull amplifier 116 to the FETs Q1 and Q2.
The PWM signal applied to the circuits up to 3 is a signal whose phase is inverted. Therefore, when the FETs Q1 and Q3 are conducting, the FETs Q2 and Q4 are non-conducting and the FETs are not conducting.
When Q1 and Q3 are non-conducting, FET Q2
Switching control is performed so that Q4 becomes conductive.

As described above, the switching control of the inverter 7 is performed based on the PWM signal obtained by modulating the commercial frequency sine wave with the high frequency triangular wave signal, and thereafter the inverter 7 is controlled.
The carrier frequency component contained in the switching output of is removed by the low-pass filter 8, and an alternating current having a commercial frequency approximate to a sine wave is supplied to the load from the output terminals 9 and 9 '.

[0055]

As described above in detail, according to the present invention, the correction mainly based on the offset DC component of the relative voltage difference signal indicating the relative voltage difference of the output line and the AC component of the relative voltage difference signal are mainly performed. Since this correction is performed by a separate correction circuit, the DC component gain is set large while maintaining the feedback control gain of the AC component (especially high frequency component) appropriately, and the waveform distortion of the output power voltage and the DC offset Can be accurately corrected.

[Brief description of the drawings]

FIG. 1 is a three-phase output winding that constitutes a portable AC power supply device.
It is a circuit diagram showing a single-phase auxiliary winding, a bridge rectifier circuit, a smoothing circuit, a constant voltage supply device, and a thyristor control circuit.

FIG. 2 is a circuit diagram showing an inverter device and an output circuit which constitute a portable AC power supply device and an inverter device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a detection circuit, a sine wave oscillator, a differential amplifier, a rectangular wave oscillator, an integrating circuit, and the like which constitute a portable AC power supply device and an inverter device according to an embodiment of the present invention. .

FIG. 4 is a pulse width modulation circuit which constitutes a portable AC power supply device and constitutes an inverter device according to an embodiment of the present invention;
It is a circuit diagram which shows a differentiating circuit etc.

FIG. 5 is a circuit diagram showing a push-pull amplifier or the like which constitutes a portable AC power supply device and constitutes an inverter device according to an embodiment of the present invention.

FIG. 6 is a timing chart of signal waveforms at various parts of the inverter device.

FIG. 7 is a timing chart of signal waveforms at various parts of the inverter device.

FIG. 8 is a timing chart of signal waveforms in various parts of the inverter device when the PWM signal fail-safe operation is performed.

FIG. 9 is a timing chart of signal waveforms in each part of the inverter device when the PWM signal fail-safe operation is performed.

[Explanation of symbols]

 7 inverters 7a, 7b output line 8 low-pass filter 101 differential amplifier 102 sine wave oscillator 103 differential amplifier 105 integrating circuit 106 inverter buffer 121 low-pass filter circuit 122 differential amplifier

Claims (2)

(57) [Claims] 1. A switching device for switching control of the output of a DC power supply circuit, a sine wave output circuit for outputting a sine wave reference signal of a predetermined frequency, and a pulse width modulation of this sine wave reference signal to output a PWM signal. A pulse width modulation circuit, a switching control circuit that causes the switching device to perform a switching operation based on a PWM signal output from the pulse width modulation circuit, and a pair of output lines connected to the switching device and supplying sinusoidal AC power. In an inverter device having an output circuit for outputting via
A detection circuit that detects a relative voltage difference between the pair of output lines, and an offset DC component of the relative voltage difference signal is extracted, amplified, and fed back to the sine wave reference signal to obtain the sine wave reference signal. A first waveform correction circuit for offset correction and an AC component of the relative voltage difference signal are fed back to the sine wave reference signal to correct the sine wave reference signal and supply it to the pulse width modulation circuit. An inverter device, comprising: a second waveform correction circuit that corrects the AC power waveform so as to approximate it to a sine wave. 2. A triangular wave output circuit that outputs a triangular wave signal having a frequency higher than that of the sine wave reference signal, an output signal from the triangular wave output circuit, and a corrected sine wave reference signal from the second waveform correction circuit. And a superposed signal forming circuit for forming a superposed signal by outputting the superposed signal to the pulse width modulation circuit, and the pulse width modulation circuit is an amplifier circuit for fixing the superposed signal from the superposed signal forming circuit to a threshold value. The inverter device according to claim 1, wherein the PWM signal is output after being pulse-width modulated by being amplified by.