JP2565475Y2 - Inverter device - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device and, more particularly, to an inverter device for controlling switching of a bridge type inverter circuit by a PWM signal boosted by a pulse transformer.

[0002]

2. Description of the Related Art In recent years, an inverter device has been increasingly used in a portable AC power supply device to stabilize an output frequency. For example, an AC generator driven by an engine has a commercial frequency. In a portable power supply device that outputs AC power, a high-power AC current is obtained from a generator by operating an engine in a high rotational speed region, and this AC current is temporarily converted to DC, and then commercialized by an inverter device. A device which converts the frequency into an alternating current and outputs it is known from Japanese Utility Model Application Laid-Open No. 59-132398.

In such an AC power supply device, there is a demand that the output waveform be as close as possible to a sine wave as much as possible depending on the intended use. In order to respond to this demand, the inverter device requires pulse width modulation (PW).
An AC power supply device adopting the M) method has also been studied (Japanese Patent Application Laid-Open No. 60-82098).

In such an AC power supply device, when an inverter device is constituted by a bridge circuit or the like composed of FETs, the source potentials of the FETs are not the same, so that when a gate signal, which is a gate-source voltage, is added,
A gate signal is transmitted using a pulse transformer or the like in a form insulated from a power supply voltage.

In such a pulse transformer, in order to boost and transmit the PWM-modulated signal, the number of turns of the secondary winding must be greater than the number of turns of the primary winding. In setting the diameter of the primary winding and the diameter of the secondary winding at this time, a simple signal transmission is sufficient as a function of the pulse transformer. The diameter of the secondary winding may be substantially the same.

[0006]

However, the primary winding and the secondary winding of the pulse transformer have the same diameter (for example,
As shown in FIG. 3, a secondary winding T2, a primary winding T3, and a secondary winding T4 are provided on the outer periphery of the bobbin T1 in this order, as shown in FIG. When the layers are wound while sandwiching them, the number of turns of the secondary winding (for example, 50 reciprocations) must be larger than the number of turns of the primary winding (for example, 15 times) for boosting. As shown in the figure, the required number of turns of the primary winding T3 ends in the middle of the bobbin T1. As a result, a gap is formed in the primary winding, and the primary winding T3 is connected to the secondary windings T2 and T4.
A magnetic path is generated which is not governed by the magnetic field. Therefore, the coupling impedance between the primary side and the secondary side increases, and inconvenience such as waveform distortion occurs in signal transmission.

Further, as shown in FIG. 4, the bobbin T1 is divided vertically by an insulating tape T5, and the secondary windings T2, T4
Therefore, even if the primary winding T3 is sandwiched in the vertical direction, the coupling impedance between the primary side and the secondary side is large, and is easily affected by disturbance.

The present invention has been made in order to eliminate such disadvantages of the conventional inverter device.
It is an object of the present invention to provide an inverter device in which the coupling impedance between the primary side and the secondary side is small, and stable signal transmission can be performed without waveform distortion or the like.

[0009]

According to the present invention, there is provided an inverter apparatus comprising: a DC power supply circuit;
A bridge type inverter circuit for switching-controlling an output of the DC power supply circuit, a pulse width modulation circuit for pulse width modulation of a sine wave reference signal of a predetermined frequency to output a PWM signal, and a PWM output from the pulse width modulation circuit A pulse transformer for boosting and transmitting a signal as a control signal for the switching operation of the bridge type inverter circuit, wherein the pulse transformer comprises:
The pulse width modulation circuit side is the primary side, the bridge type inverter circuit side is the secondary side, and the wire diameter of the primary winding is the secondary side.
Increase the winding width around the bobbin by making it larger than the winding wire diameter
By doing so, on the outer periphery of the bobbin, the respective layers are uniformly arranged in the order of
Characterized by comprising by winding superposed so properly.

[0010]

In the inverter device of the present invention, the wire diameter of the primary winding of the pulse transformer is made larger than the wire diameter of the secondary winding.
By increasing the winding width around the bobbin,
Is each layer uniform in the order of secondary, primary, and secondary ?
The primary winding and the secondary winding have a large contact area because they are wound around the bobbin so that the winding widths are approximately equal , and the secondary winding is not influenced by the primary winding. There is no road. As a result, the coupling impedance between the primary side and the secondary side decreases, and as a result, stable signal transmission without waveform distortion or the like can be achieved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a half of a pulse transformer used in an embodiment of the inverter device according to the present invention, and FIG. 2 is a diagram showing a connection relationship of coils of the pulse transformer of FIG.

In FIG. 1, the pulse transformer has a secondary winding T2, a primary winding T3, and a secondary winding T4, which are wound around the bobbin T1 in this order. The wire diameter of the primary winding T3 is 0.5 mm,
2, the wire diameter of T4 is 0.26 mm in diameter. Further, the primary winding T3 is wound 15 times around the bobbin, and the secondary windings T2 and T4 are wound 50 times in a reciprocating manner. By winding in this way, the primary winding T3
And the winding width in the height direction of the bobbin T1 after the winding of the secondary windings T2 and T4 is substantially equal. Further, as shown in FIG. 2, the secondary windings T2 and T4 form independent closed circuits.

FIGS. 5 and 6 are circuit diagrams showing the overall configuration of a portable AC power supply device using the inverter device of the present embodiment.

In FIG. 5, reference numerals 1 and 2 denote output windings independently wound on a stator of an AC generator, 1 denotes a three-phase output winding, and 2 denotes a single-phase output winding. The rotor (not shown) is formed with magnetic poles of a multi-pole permanent magnet, and is configured to be rotationally driven by an engine (not shown). The output terminal of the three-phase output winding 1 is connected to a bridge rectifier circuit 3 composed of three thyristors and three diodes, and the output terminal of the bridge rectifier circuit 3 is connected to a smoothing circuit 4. And this bridge rectifier circuit 3
And the smoothing circuit 4 constitute a DC power supply circuit.

The output terminal of the single-phase auxiliary winding 2 is connected to a constant voltage supply device 5 having positive and negative bipolar output terminals E and F. The constant voltage supply device 5 includes two sets of rectifier circuits, a smoothing circuit, and a constant voltage circuit 5a. One circuit of each set works for a current flowing from the single-phase auxiliary winding 2 in one direction, and the opposite set. With respect to the current in the direction, the other sets of circuits operate, whereby positive and negative constant voltages are output to the output terminals E and F, respectively.

Reference numeral 6 denotes a thyristor control circuit. One end on the power input side is connected to the positive output terminal E of the constant voltage supply device 5, and the other end is grounded together with the positive terminal on the smoothing circuit 4. The signal input terminal of the thyristor control circuit 6 is connected to the negative terminal of the smoothing circuit 4, and the signal output terminal is connected to the gate input circuit of each thyristor of the bridge rectifier circuit 3.

Therefore, the three-phase AC power output from the three-phase output winding 1 is rectified by the bridge rectifier circuit 3 and then smoothed by the smoothing circuit 4 to be converted into DC power.
The fluctuation of the DC voltage in the smoothing circuit 4 is controlled by the thyristor control circuit 6
The feedback control is performed such that the output voltage of the smoothing circuit 4 is stably maintained by controlling the conduction of each thyristor of the bridge rectifier circuit 3 based on the detection signal.

The detailed description of the control operation by the thyristor control circuit is described in Japanese Patent Application No. Hei.
No. 0908 and Japanese Utility Model Application No. 1-85360, and will not be described here.

Next, the inverter device will be described.

The output terminal of the smoothing circuit 4 is connected to an inverter 7. The inverter 7 is configured by a bridge circuit including four FETs (field effect transistors) Q1 to Q4, which are switching devices. A drive signal circuit connected to each gate terminal of the FETs Q1 to Q4 will be described later.

The output terminal of the inverter 7 (FET Q1, Q4
Are connected to output terminals 9, 9 'to which a load (not shown) is connected via a low-pass filter 8 which is an output circuit. The low-pass filter 8 is connected so that the coils L1 and L2 are in series with the load and the capacitor C1 is in parallel with the load.
By passing an alternating current of a low frequency component (a commercial frequency in this embodiment) of the output of the inverter 7, power of the commercial frequency is supplied from the output terminals 9 and 9 ′ to the load.

Both ends G of the capacitor C1 of the low-pass filter 8 are connected to one end of each of a series circuit of the resistors R1 and R2 and a series circuit of the resistors R3 and R4 shown in FIG. On the other hand, the other ends of these resistance series circuits are connected to the positive output terminal E of the constant voltage supply device 5. A connection point of the resistors R1 and R2 and a connection point of the resistors R3 and R4 are respectively connected to the resistor R1.
0 and R11, are connected to the positive input terminal and the negative input terminal of the differential amplifier 101, and a high frequency component cutting capacitor C is connected between the two connection points.
2 are connected. The positive input terminal of the operational amplifier constituting the differential amplifier 101 is grounded via a high frequency component cutting capacitor C3.

A sine wave oscillator 102 generates a sine wave of a commercial frequency, for example, 50 Hz or 60 Hz. The output of the sine wave oscillator 102 and the output of the differential amplifier 101 are connected to the negative input terminal and the positive input terminal of the differential amplifier 103, respectively.

Reference numeral 104 denotes a rectangular wave oscillator. The period of the rectangular wave oscillated by the rectangular wave oscillator 104 is set to a value larger than about 50 nsec, the response time of an inverter buffer 106 described later. This value is much faster than the response time of the conventional comparator, which is about 1 μsec. Therefore, the frequency of the rectangular wave can be set much higher than the frequency of the conventional PWM carrier (triangular wave).

The output terminal of the rectangular wave oscillator 104 is the integration circuit 1
05. The output terminal of the integration circuit 105 and the output terminal of the differential amplifier 103 are connected to each other to form a superimposed signal forming circuit, and are connected to the inverter buffer 106.
Inverter buffer 106 has a predetermined threshold (threshold level), and outputs a low-level signal when a signal having a level exceeding the threshold is input, while outputting a signal having a level lower than the threshold. It outputs a high-level signal when a signal is input, and has a fixed threshold value for an input signal from a gate terminal.
It is composed of a buffer IC having a threshold level of a MOS gate.

The output terminal of the inverter buffer 106 is N
Connected to one input terminal of AND circuit 107.

The output terminal of the square wave oscillator 104 is further connected to a differentiating circuit 110 via an inverter buffer 108 and to a differentiating circuit 1 via two inverter buffers 109.
11 respectively. A differentiating circuit 110 includes a coupling capacitor C provided between an input terminal and an output terminal.
4, the output terminal of the capacitor C4 and the constant voltage supply device 5
And a parallel circuit of a resistor R5 and a diode D1 (the anode is directed toward the negative electrode output terminal F) provided between the negative electrode output terminal F and the negative electrode output terminal F. The differentiating circuit 111 also includes a coupling capacitor C5, a diode D2, and a resistor R6, which are arranged in exactly the same manner as the differentiating circuit 110.

The output terminal of the differentiating circuit 110 is connected to the other input terminal of the NAND circuit 107 via the inverter buffer 112. An output terminal of the NAND circuit 107 is connected to one input terminal of the NAND circuit 114. Differentiating circuit 111
Is connected to the other input terminal of the NAND circuit 114 via the inverter buffer 113.

The output terminal of the NAND circuit 114 passes through two inverter buffers 115, and is connected to transistors Q5 and Q6.
Connected to a push-pull amplifier 116. The collector of the transistor Q5 of the push-pull amplifier 116 is connected to the positive output terminal E of the constant voltage supply device 5,
The collector 6 is connected to the negative output terminal F of the constant voltage supply device 5.

The output terminal of the push-pull amplifier 116 (the connection point between the emitters of the transistors Q5 and Q6) is connected to the connection point between the anode of the diode D3 and the cathode of the diode D4. The cathode of the diode D3 is connected to the positive output terminal E of the constant voltage supply device 5, and the anode of the diode D4 is connected to the negative output terminal F of the constant voltage supply device 5. The diodes D3 and D4 are for absorbing the surge generated in the pulse transformer A as described with reference to FIGS.

The anode of the diode D3 and the diode D
4 is connected to the cathode of the primary coil L of the pulse transformer A via a capacitor C6 for cutting low frequency components.
3 is connected to one end. The other end of the primary coil L3 is connected to the negative output terminal F of the constant voltage supply device 5. The capacitor C6 is set to a constant value that allows only a high frequency PWM carrier frequency signal and does not allow a low frequency component to pass.

The output terminal of the NAND circuit 114 is connected to a push-pull amplifier 118 composed of transistors Q7 and Q8 after passing through an inverter buffer 117. The output terminal of the push-pull amplifier 118 is connected to the anode of the diode D5 and the diode D5. It is connected to the connection point of D6 with the cathode. This connection point is connected to one end of the primary side coil L4 of the pulse transformer B via a capacitor C7 set to a constant value such that only the PWM carrier frequency signal is passed and the low frequency component is not passed, similarly to the capacitor C6 described above. Connected.

Returning to FIG. 5, a drive signal circuit connected to each gate terminal of the FETs Q1 to Q4 will be described. One end of the secondary coil L5 of the pulse transformer A is connected to a resistor R
7. Capacitor C8 for demodulation, resistor R8 and diode D
7, is connected to the gate terminal of the FET Q1, while the other end of the secondary coil L5 of the pulse transformer A is connected to the source terminal of the FET Q1. A connection point between the capacitor C8 and the parallel circuit including the resistor R8 and the diode D7 is connected to the other end of the coil L5 on the secondary side of the pulse transformer A via zener diodes D8 and D9. The diode D7 has an anode on the gate terminal side of the FET Q1, and has a zener diode D8,
D9 is connected such that the anodes face each other.

Another secondary coil L6 of the pulse transformer A and secondary coils L7 and L8 of the pulse transformer B
And the gate terminals of the corresponding FETs Q3, Q2, and Q4, the secondary coil L5 of the pulse transformer A and the FE
A circuit exactly the same as the circuit provided between the gate terminal of TQ1 is provided.

The operation of the inverter device configured as described above (the inverter 7, the low-pass filter 8, and the circuit device of FIG. 6) will be described below with reference to signal waveforms shown in FIG.

The FETs Q1, Q3 and FE of the inverter 7
A pulse width modulation (PWM) signal to be described later is input to the gate terminals of TQ2 and Q4.
The output of the smoothing circuit 4 is switched and output to the low-pass filter 8 by alternately conducting the ETQ1 and Q3 and the FETs Q2 and Q4. The low-pass filter 8 cuts high-frequency components and supplies AC power of a commercial frequency from the output terminals 9 and 9 'to the load.

The waveform of the output voltage appearing at the output terminal 9 and the waveform of the output voltage appearing at the output terminal 9 'are respectively passed through the voltage dividing resistors R1, R2 and R3, R4 and then compared by the differential amplifier 101. The difference, that is, the distortion or offset component of the output voltage waveform is detected, and this detection signal is amplified and output to the differential amplifier 103. Output terminal 9,
Since the output voltage waveforms appearing at 9 'are compared, distortion of the output voltage waveform can be accurately detected. The capacitors C2 and C3 remove high-frequency components from the difference signal, and the capacitor C3 also removes disturbance applied to the differential amplifier 103.

The differential amplifier 103 receives a commercial frequency sine wave signal input from the sine wave oscillator 102 and the differential amplifier 10.
A commercial frequency sine wave signal ("b" in FIG. 7) whose amplitude reference level is corrected by a DC feedback signal input from 1 is output. A PWM signal is generated based on the corrected sine wave signal as described later. Therefore, it is possible to reduce the distortion and the offset component of the waveform of the output voltage generated due to the variation in the threshold value of the inverter buffer 106 and the like.

The rectangular wave signal output from the rectangular wave oscillator 104 is integrated by the integrating circuit 105 and is integrated into a triangular wave signal (FIG. 7).
b ′) is formed. The triangular wave signal b ′ and the corrected sine wave signal b ″ from the differential amplifier 103 are superimposed to form a superimposed signal (FIG. 7B), and the inverter buffer 1
06. Inverter buffer 106 outputs a low-level signal when a signal having a level exceeding a threshold (broken line shown in FIG. 7B) is input, and outputs a high-level signal when a signal having a level lower than the threshold is input. Output (FIG. 7c). The output pulse train signal c is a pulse width modulation (PWM) signal obtained by using the triangular wave signal b ′ as a carrier wave and performing pulse width modulation with the sine wave signal b ″.

Next, the NAN is calculated from the pulse width modulated signal c.
The description up to the output signal i of the D circuit 114 will be described.

The square wave signal a output from the square wave oscillator 104 is inverted by the inverter buffer 108,
Differentiation is performed by the differentiating circuit 110 to obtain a differentiated signal d. That is, when the rectangular wave signal a falls, the capacitor C4 is charged via the resistor R5, and a positive differential output appears. When the rectangular wave signal a rises, the capacitor C4 is discharged via the diode D1 and the negative differential signal is output. Output appears.

The output signal from the differentiating circuit 110 is inverted and amplified by the inverter buffer 112 based on the threshold value, and becomes a low-level rectangular wave signal e while the positive differential output is larger than the threshold value. At this time, the output signal e of the inverter buffer 112 and the output signal c of the inverter buffer 106 are input to the NAND circuit 107,
The circuit 107 outputs a low-level rectangular wave signal h only when both the input signals are at a high level.

Further, the square wave signal a output from the square wave oscillator 104 passes through two inverter buffers 109 and is then subjected to a differentiation process by a differentiating circuit 111 to obtain a square wave signal a.
A positive differential output appears at the rising edge of the signal, and a differential signal f appears at the falling edge of the negative differential output. This differential signal f is inverted and amplified by the inverter buffer 113 based on the threshold value, and becomes a low-level rectangular wave signal g at the positive differential output portion. The signal processing operation in the differentiating circuit 111 and the inverter buffer 113 is the same as the operation in the differentiating circuit 110 and the inverter buffer 112 described above.

The NAND circuit 114 is connected to the NAND circuit 1
07 and the output signal g of the inverter buffer 113 are input, and the NAND circuit 114 outputs a low-level rectangular wave signal (PWM signal) i when both input signals are at a high level.
Is output.

P output from NAND circuit 114
The WM signal i is subjected to push-pull amplification by a push-pull amplifier 116 after passing through two inverter buffers 115, and then supplied to a low frequency component cutting capacitor C6. The signal immediately before passing through the capacitor C6 is
Although the PWM signal has a constant amplitude with respect to the reference level, the average voltage (integrated value) of this signal changes in the same cycle as the sine wave from the sine wave oscillator 102,
The WM signal contains the same frequency (commercial frequency) component as the sine wave.

Since the capacitor C6 does not pass the low frequency signal, that is, the commercial frequency signal in this embodiment, but passes only the PWM carrier frequency signal which is a high frequency signal, after the PWM signal passes through the capacitor C6, as shown in FIG. Then, a pulse signal train in which the entire pulse train rises and falls in the opposite phase to the commercial frequency component and the average voltage is always zero is supplied to the primary coil L3 of the pulse transformer A. Therefore, the transformer core constituting the pulse transformer A has almost no adverse effect of magnetic saturation due to the commercial frequency component, and can be configured with a small size that does not cause magnetic saturation at the PWM carrier frequency.

As described above, the pulse transformer A
Since the windings of the primary coil L3 and the secondary coils L5 and L6 after being wound around the bobbin are substantially equal, the coupling impedance is small, good signal transmission is possible, and waveform distortion and the like are reduced. Does not occur.

Thus, the pulse signal (substantially the same as the signal shown in FIG. 7j) transmitted well from the secondary coil L5 of the pulse transformer A is transmitted to the Zener diodes D8 and D9, which are bidirectional voltage regulating circuits. When the output pulse signal exceeds these breakdown voltages in the positive direction or the negative direction, the Zener diode D8 or D9 conducts, regulates the voltage of the output pulse signal, and charges the capacitor C8. Discharged
At both ends of the capacitor C8, an average voltage (which has a commercial frequency) due to the output pulse signal exceeding each breakdown voltage in the positive direction or the negative direction appears. Therefore, between the gate and the source of the FET Q1, a signal obtained by superimposing the voltage between both ends of the capacitor C8 having the commercial frequency and the pulse signal output from the secondary coil L5 of the pulse transformer A, that is, the PWM before passing through the capacitor C6. The signal (FIG. 7c) is demodulated. The FET Q1 conducts while the positive pulse signal of the PWM signal is being input to the gate terminal.

Note that the constant of the capacitor C8 is the FET Q1
The value of the resistor R7 is a sufficiently large value for the gate capacitance of
Secondary coil L5 of pulse transformer A and capacitor C8
Is selected so that Q can be suppressed.
The resistor R8 regulates the switching speed of the FET Q1, and the diode D7 rapidly charges the electric charge stored in the gate capacitance of the FET Q1 when the voltage applied to the gate terminal of the FET Q1 is reduced. This is for causing the FET Q1 to be immediately turned off by discharging. In addition, the Zener diode D9 has a function of preventing a rise in the reference potential of the FET Q1 generated by a kickback voltage from the secondary coil L5 of the pulse transformer A.

The pulse signal output from the secondary coil L6 of the pulse transformer A is processed in exactly the same manner as the pulse signal output from the secondary coil L5, and the FET Q3
Is performed at the same timing as that of the FET Q1. Therefore, when the positive pulse of the PWM signal is input, the FETs Q1 and Q3 conduct, and a DC current is supplied from the smoothing circuit 4 to the low-pass filter 8.

Next, after the PWM signal output from the NAND circuit 114 passes through the inverter buffer 117, the same signal processing as the signal processing circuit from the push-pull amplifier 116 to the FETs Q1 and Q3 is performed.
2, Q4 are switching-controlled in accordance with the PWM signal. However, since the signal passes through the inverter buffer 117, PW
The M signal is transmitted from the push-pull amplifier 116 to the FET Q
The PWM signal applied to the circuits up to Q1 and Q3 is a signal whose phase is inverted.
Are conducting, FETs Q2 and Q4 are non-conducting, and when FETs Q1 and Q3 are non-conducting, F
Switching control is performed so that ETQ2 and ET4 become conductive.

As described above, the switching control of the inverter 7 is performed based on the PWM signal obtained by modulating the sine wave of the commercial frequency with the triangular wave signal of the high frequency.
The carrier frequency component included in the switching output of the first embodiment is removed by the low-pass filter 8, and an AC current having a commercial frequency substantially similar to a sine wave is supplied to the load from the output terminals 9, 9 '. Then, the primary coils L3, L4 and the secondary coils L5, L6 and L7, L8 of the pulse transformers A, B for winding up and transmitting the PWM signal output from the pulse width modulation circuit to the bridge type inverter circuit are wound around the bobbin. Since the winding widths after mounting are substantially equal, the coupling impedance between the primary coils L3, L4 and the secondary coils L5, L6 and L7, L8 is small, and good signal transmission is performed.

[0054]

As described above, in the inverter device of the present invention, the pulse transformer has the primary side on the pulse width modulation circuit side, the secondary side on the bridge type inverter circuit side, and the wire diameter of the primary winding. Larger than the wire diameter of the secondary winding
By increasing the winding width to the outer periphery of the bobbin, the outer periphery of the <br/> bobbin, the secondary side, the primary side, it in the order of the secondary side
Since the layers are wound so as to be uniform and the winding widths are approximately equal , no air gap is created in the primary winding, and the secondary winding has a magnetic path that is not governed by the primary winding. Does not occur. As a result, the coupling impedance between the primary side and the secondary side of the pulse transformer is small, and waveform distortion or the like does not occur, and stable signal transmission can be performed.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a half of an embodiment of a pulse transformer used in the inverter device of the present invention.

FIG. 2 is a diagram showing a connection relationship between windings of the pulse transformer of FIG. 1;

FIG. 3 is a cross-sectional view showing a half of an example of a pulse transformer used in a conventional inverter device.

FIG. 4 is a sectional view showing a half of another example of the pulse transformer used in the conventional inverter device.

FIG. 5 is a circuit diagram showing a part of a circuit configuration of an embodiment of the inverter device of the present invention.

FIG. 6 is a circuit diagram showing another portion of the circuit configuration of the embodiment of the inverter device of the present invention.

FIG. 7 is a waveform diagram showing waveforms at various parts of the circuit of the embodiment of the inverter device of the present invention.

[Explanation of symbols]

 T1 bobbin T2, T4, L5, L6, L7, L8 Secondary coil T3, L3, L4 Primary coil 5 Constant voltage supply device 6 Thyristor control circuit 7 Inverter

Claims (1)

(57) [Scope of request for utility model registration] 1. A DC power supply circuit, a bridge type inverter circuit for switching-controlling an output of the DC power supply circuit,
Pulse width modulation of a sine wave reference signal of a predetermined frequency and PWM
An inverter device comprising: a pulse width modulation circuit that outputs a signal; and a pulse transformer that boosts and transmits a PWM signal output from the pulse width modulation circuit as a control signal for the switching operation of the bridge-type inverter circuit. The pulse transformer is such that the pulse width modulation circuit side is a primary side, the bridge type inverter circuit side is a secondary side, and the wire diameter of the primary winding is larger than the wire diameter of the secondary winding.
By increasing the winding width around the bobbin
On the outer periphery of the serial bobbin, the secondary side, the primary side, that in the order of the secondary side
An inverter device , wherein each of the layers is stacked and wound so that each layer is uniform and the winding width is substantially equal .