JP2976986B2 - Method of forming alignment mark - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In relation to a method of forming an alignment mark, in particular, a wafer is stuck to form an SOI (Silicon On Insulator) substrate, which is overlaid by a charged beam (for example, an electron beam) exposure. Regarding the method of forming alignment marks when performing exposure, forming alignment marks that do not disappear even when grinding and polishing the silicon wafer in the element formation section, and forming alignment marks that enable high-accuracy overlay exposure When forming a fine pattern with a charged beam on a first semiconductor substrate on which an element forming portion is formed, a position for the charged beam exposure using a heavy metal or a negative resist on the semiconductor substrate is provided. Forming an alignment mark so as to protrude from the semiconductor substrate surface, forming a stopper layer on the entire surface on the alignment mark formation surface side Forming an insulating layer on the stopper layer, forming a second semiconductor substrate on the previous insulating layer, and removing the first semiconductor substrate from the side opposite to the second semiconductor substrate until the stopper layer is exposed. And a step of removing the negative resist when a negative resist is used.

[Industrial applications]

The present invention relates to a method of forming an alignment mark, and in particular, to bonding a wafer to form an SOI (Silicon On Insulator).
The present invention relates to a method of forming an alignment mark when a substrate is formed and a superposition exposure is performed by a charged beam (for example, an electron beam) exposure.

[Conventional technology]

For example, in the overlay exposure using an electron beam, alignment marks 1 as shown in FIG. 3 are arranged at the four corners of the chip 3, and the positions of the alignment marks are detected by scanning with the electron beam, and the position, deflection distortion, Make various corrections such as
Perform overlay exposure. Reference numeral 2 denotes an element forming portion. FIG. 4 is a view showing various alignment marks.

Conventionally, for example, a positioning method in a bonded SOI is performed as shown in FIGS. 5 (a) to 5 (e).
First, as shown in FIG.
After forming an alignment mark 1 of the same shape having a depth of about 0.1 μm on the surface by, for example, a lithography technique,
As shown in FIG. 5B, an SiO ₂ film 6 is formed to a thickness of about 0.1 μm on the entire exposed surface. In the figure, reference numeral 2 denotes an element forming portion.

Next, as shown in FIG. 5 (c), a polycrystalline silicon 5 is formed on the SiO ₂ film 6 by a CVD method, and then, as shown in FIG. 5 (d), another mirror surface is formed on the polycrystalline silicon 5. The silicon wafer 7 was bonded and ground and polished from the back, that is, the mirror-finished silicon wafer 3 in the direction of the arrow. On the other hand, as shown in FIG.

[Problems to be solved by the invention]

As described above, in the bonded SOI, since the back surface is polished after exposing the element formation portion, the alignment marks are polished at the same time, and the alignment marks disappear, so that there is a problem that the subsequent overlay exposure cannot be performed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming an alignment mark that forms an alignment mark that does not disappear even when grinding and polishing a silicon wafer of an element forming portion and enables high-accuracy overlay exposure.

[Means for solving the problem]

According to the present invention, when forming a fine pattern with a charged beam on a first semiconductor substrate on which an element forming portion is formed according to the present invention, the charged beam exposure using a heavy metal or a negative resist on the semiconductor substrate is performed. Forming an alignment mark so as to protrude from the semiconductor substrate surface, forming a stopper layer on the entire surface on the alignment mark forming surface side, forming an insulating layer on the stopper layer, on a previous insulating layer Forming a second semiconductor substrate, and removing the first semiconductor substrate from the side opposite to the second semiconductor substrate until the stopper layer is exposed. The problem is solved by a method of forming an alignment mark, further comprising a step of removing the negative resist.

In the present invention, it is preferable that the first semiconductor substrate on which the element forming portion is formed is a silicon wafer of an SOI substrate formed by bonding wafers.

The heavy metal used in the present invention is preferably gold, tungsten or the like for detecting a mark.

(Operation)

According to the present invention, in order to form an alignment mark in advance after forming an element forming portion, superposition exposure can be performed after removal of a wafer such as grinding and polishing.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (e) are process sectional views showing an embodiment of the present invention.

The reference numerals shown in the figure are the same as the reference numerals shown in FIG.

First, as shown in FIG. 1 (a), after forming an element forming portion 2 on a mirror-finished silicon wafer 3, a positive resist 4 is applied to the entire surface, and the alignment marks used in the exposure of the element forming portion are used. An alignment mark for forming a pattern after bonding another mirror surface silicon wafer is exposed. Next, heavy metals (for example, lift-off, sputtering, etc.)
Au, W, etc.). Next, as shown in FIG. 1 (b), an SiO ₂ film 6 is formed by a thermal oxidation method as a polishing stopper layer, and polycrystalline silicon 5 as an insulating film is provided by a CVD method (FIG. 1 (c)). Next, as shown in FIG. 1D, another silicon wafer 7 is bonded and polished from the back. As a result, an alignment mark 10 for superposition after polishing is formed (FIG. 1 (e)).

2 (a) to 2 (e) are process sectional views showing a second embodiment of the present invention.

In the first embodiment shown in FIG. 1, a positive resist was applied after forming the element forming portion 2 and the forming portion 2 was formed. In the second embodiment, the negative resist 1 was applied and used for exposing the element forming portion. Using the alignment mark, the alignment mark 1 for forming a pattern after bonding is exposed. Next, an SiO ₂ film 6 is formed by a thermal oxidation method as a polishing stopper layer (FIG. 2 (b)), and then the polycrystalline silicon 5 of the insulating film is formed by a CVD method as shown in FIG. Provided by next,
As shown in FIG. 2D, another silicon wafer 7 is bonded and polished from the back. Next, by removing the resist film appearing after polishing, an alignment mark 10 for superposition after polishing is formed (FIG. 2 (e)).

〔The invention's effect〕

As described above, according to the present invention, when performing the overlay exposure after forming the element, the overlay exposure after bonding is performed with high accuracy in order to create a new alignment mark after the formation of the element forming portion. It can be carried out.

[Brief description of the drawings]

FIGS. 1A to 1E are process sectional views showing an embodiment of the present invention, and FIGS. 2A to 2E are process sectional views showing a second embodiment of the present invention. FIG. 3 is a plan view showing an arrangement of alignment marks in a chip, FIG. 4 shows four alignment mark shapes (examples), and FIGS. 5 (a) to 5 (e) show conventional processes. It is sectional drawing. 1 ...... alignment mark, 2 ...... element forming portion, 3 ...... mirror silicon wafer, 4 ...... positive resist, 5 ...... polycrystalline silicon, 6 ...... SiO ₂ film, 7 ...... silicon wafer.

Claims (5)

(57) [Claims] When forming a fine pattern with a charged beam on a first semiconductor substrate on which an element forming portion is formed, a positioning mark for the charged beam exposure is formed on a surface of the semiconductor substrate by using a heavy metal on the semiconductor substrate. Forming a stopper layer on the entire surface on the alignment mark forming surface side; forming an insulating layer on the stopper layer; forming a second semiconductor substrate on the front insulating layer Performing a step of removing the first semiconductor substrate until the stopper layer is exposed from a side opposite to the second semiconductor substrate. 2. The method according to claim 1, wherein the first semiconductor substrate on which the element forming portion is formed is an SOI substrate silicon wafer formed by bonding wafers. 3. The method according to claim 1, wherein said heavy metal is gold or tungsten. 4. When forming a fine pattern with a charged beam on a first semiconductor substrate on which an element forming section is formed, a positioning mark for the charged beam exposure is formed on the semiconductor substrate by using a negative resist on the semiconductor substrate. Forming a stopper layer on the entire surface on the alignment mark forming surface side; forming an insulating layer on the stopper layer; forming a second semiconductor substrate on the front insulating layer Forming an alignment mark, comprising: removing the first semiconductor substrate until the stopper layer is exposed from a side opposite to the second semiconductor substrate; and removing the negative resist. Formation method. 5. The method according to claim 4, wherein the first semiconductor substrate on which the element forming portion is formed is a silicon wafer of an SOI substrate formed by bonding wafers.