JP2921507B2 - Electron beam exposure mask and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam exposure method used for an electron beam exposure method for directly drawing an electron beam on a resist adhered to a semiconductor substrate to form a circuit pattern such as a semiconductor integrated circuit on the semiconductor substrate. Related to masks.

[0002]

2. Description of the Related Art In recent years, progress in semiconductor integrated circuits has been remarkable, and in particular, memory devices, such as DRAMs, have realized a large storage capacity of four times every three years. This progress is largely due to advances in microfabrication technology, and in particular depends on advances in lithography technology.

To form a fine pattern on a wafer as a semiconductor substrate, a reduction projection exposure apparatus using ultraviolet light as a light source, a so-called stepper, has been used. However, in order to transfer a finer pattern, a light source of the light source is used. The wavelength has been shortened, and the wavelength has changed from the g-line (436 nm) of the mercury lamp to the i-line (365 nm) of the same mercury lamp, and further to KrF excimer laser light (249 nm) using krypton fluoride gas.

However, the improvement of the fine pattern transfer capability, that is, the resolution, by shortening the wavelength of the light source, on the contrary, causes a decrease in the depth of focus. Therefore, an electron beam exposure method, which has a drastically wider depth of focus than a light exposure method, has attracted attention.

[0005] In this electron beam exposure method, a semiconductor integrated circuit pattern is successively drawn by imitating the pattern with an electron beam having a small spot, so that finer patterning is possible, but the processing capability is lower than that of the light exposure method. And it was.

[0006] However, in the electron beam exposure method,
Instead of this one-stroke drawing method, Japanese Patent Laid-Open No.
Japanese Patent Application Publication No. 30-301 discloses a partial batch electron beam exposure method in which batch reduction transfer is performed using a mask in which a semiconductor integrated circuit is partially formed, and the batch reduction patterns are connected to reduce and transfer the entire circuit pattern. It has been developed and processing capacity has been dramatically improved.

FIGS. 6 to 8 are a plan view and a sectional view for explaining the structure of a conventional mask for electron beam exposure and a method for manufacturing the same.

FIG. 6A is a plan view of a part of a conventional electron beam exposure mask, and FIG. 6B is a sectional view taken along the line AA 'in FIG. 6A. As shown in FIGS. 6 (a) and 6 (b), a conventional electron beam exposure mask 31 has a SiO ₂ layer having a thickness of 1 to 2 μm on a Si layer 1 having a thickness of 400 to 600 μm.
The Si pattern layer 3 having a thickness of 20 μm or more is bonded via the layer 2. A transfer pattern 5 is formed in the Si pattern layer 3 so as to have an opening 25 times as large as the design dimensions of the semiconductor device. Normally 50 KV is applied to the electron beam exposure mask 31.
The electron beam accelerated by the above voltage is applied. Therefore, the Si pattern layer 3 needs to have a thickness of 20 μm or more to completely block the electron beam so that the electron beam does not pass. Further, the conductive layer 4 for preventing charge-up due to electron beam irradiation is formed of the Si pattern layer 3.
Is deposited on top.

FIGS. 7 (a), 7 (b), 7 (c) and 7 (d) are cross-sectional views for explaining steps of manufacturing a conventional electron beam exposure mask 31. FIG.

First, as shown in FIG. 7A, a surface of a silicon bonded wafer 6 having a plane orientation of (100) is patterned by lithography and dry etching, and a wet etching protective film ( 7) is formed. Note that Japanese Patent Application Laid-Open
JP-A-126630 describes a process in which the Si layer 1 and the Si pattern layer 3 are bonded via the SiO ₂ layer 2, but such bonding has already been performed by a silicon wafer maker such as Shin-Etsu Chemical Co., Ltd. A bonded wafer is sold and can be used.

Next, as shown in FIG. 7 (b), the resist is patterned, and the wet etching protective film 7 is removed by dry etching using a resist mask 8 having an open window, and a back etch window 9 is formed. Form.

Next, as shown in FIG. 7 (c), the Si wafer 6 exposed from the back etch window 9 is etched using a wet etching solution heated with an alkali solution such as potassium hydroxide or hydrazine. An opening 10 is formed by back etching including the SiO ₂ layer 2.

The opening 10 is tapered by the appearance of the plane orientation (111) during wet etching. Thereafter, as shown in FIG. 7 (d), the resist 8 and the protection film 7 for wet etching are removed, and the conductive layer 4 is applied on the surface by sputtering. Thus, the electron beam exposure mask 31 is completed.

[0014]

The conventional electron beam exposure mask 31 irradiates the Si pattern layer 3 with an electron beam having an acceleration voltage of 50 KV or more during use. Except for this, the Si pattern layer 3 needs to have a thickness of 20 μm or more in order to completely block the electron beam so that the electron beam does not pass through. However, when the Si pattern layer 3 is thick, the transfer pattern 5 opened by the dry etching becomes tapered. FIG. 8 is an enlarged cross-sectional view showing a portion where the transfer pattern 5 is tapered. As shown in FIG. 8, the size S1 on the front side and the size S2 on the back side of the opening of the transfer pattern 5 are shown in FIG. Greatly fluctuates (hereinafter referred to as “dimension fluctuation”). Furthermore, the angle of this taper is not constant, and varies from 88 ° to 89 ° depending on the size, shape, and position on the mask of the transfer pattern, and this cannot be controlled. As described above, the thickness of the Si pattern layer 3 causes a reduction in dimensional accuracy of a pattern transferred onto a wafer by electron beam exposure.

If the Si pattern layer 3 is made thinner, the dimensional change due to the influence of the taper can be reduced, but this time, the electron beam passes through the place where the electron beam should be shielded, and the resist on the wafer is not exposed to light. Excess parts are exposed, and the pattern is not formed normally.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has an object to improve the dimensional accuracy of a transfer pattern by reducing the thickness of a Si pattern layer and to prevent an electron beam from being incident on a wafer. An object of the present invention is to provide a mask for electron beam exposure, on which a pattern can be transferred with high dimensional accuracy, and a method for manufacturing the same.

[0017]

In order to achieve the above object, the present invention provides an electron beam exposure mask in which a plurality of drawing opening patterns are formed on a plate member, the mask being provided on the back side of the mask. Provided is an electron beam exposure mask, wherein an electron beam scattering layer for scattering transmitted electron beams is formed. In the present invention, preferably, the electron beam scattering layer is a polycrystalline body formed on the back surface of the mask, for example, the polycrystalline body is at least one of polycrystalline silicon, tungsten silicide, molybdenum silicide, and titanium silicide. It is characterized by being formed by applying one polycrystalline material by a sputtering method. Or,
In the present invention, preferably, the electron scattering layer is an uneven layer formed on the back surface of the mask.

In the method of manufacturing an electron beam exposure mask according to the present invention, preferably, in the method of manufacturing an electron beam exposure mask for forming a drawing opening pattern on a plate member, a desired pattern is formed on the plate member. After that, an electron beam scattering layer for scattering the electron beam transmitted through the mask is formed on the back surface of the plate member. Alternatively, the method for manufacturing an electron exposure mask according to the present invention is preferably a method for manufacturing an electron beam exposure mask for forming an opening pattern for drawing on a plate member, wherein the electron beam transmitted through the mask on the back surface of the plate member. After forming an electron beam scattering layer for scattering light, a desired pattern is formed on the plate member. Alternatively, the method for manufacturing an electron beam exposure mask according to the present invention is preferably such that, in the method for manufacturing an electron beam exposure mask for forming a drawing opening pattern on a plate member, an electron beam scattering layer for previously scattering electron beams. A desired pattern is formed on the plate member formed with.

[0019]

According to the present invention, there is provided an electron beam exposure mask in which a pattern layer on which an opening pattern for drawing is formed is thinned to improve the dimensional accuracy of the pattern, and an electron beam scattering layer is provided on the back side of the pattern layer. Accordingly, it is possible to prevent the electrons transmitted through the pattern layer from being scattered and being incident on the wafer, so that the pattern can be transferred onto the wafer with high dimensional accuracy. Therefore, it is possible to greatly improve the yield of the manufactured LSI. Further, in the method of manufacturing a mask for electron beam exposure according to the present invention, since an electron beam scattering layer may be provided on the back side of the mask, the manufacturing is relatively easy and the manufacturing cost is not excessive.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

The basic structure of the mask for electron beam exposure according to the present invention is, for example, as shown in FIG. 1, a Si pattern layer 3 is bonded on a Si layer 1 via a SiO ₂ layer 2,
The transfer pattern 5 is formed in the i-pattern layer 3 with an opening. The thickness of the Si pattern layer 3 is smaller than that of the
The dimensional change due to the taper between the opening dimension S1 on the front side and the opening dimension S2 on the back side of the transfer pattern 5 formed on the pattern layer 3 is smaller than in the conventional example. Also,
An electron beam scattering layer 11 is formed on the back surface of the electron beam exposure mask.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of an electron beam exposure mask for explaining a first embodiment of the present invention. In the mask 21 for electron beam exposure according to the present embodiment, the Si pattern layer 3
Has a thickness of 5 μm, which is 20 μm or more in the conventional example, but is reduced to a quarter of that. For this reason, the dimension variation due to the taper of the etched portion, that is, the opening dimension S1 on the front side of the transfer pattern 5
The difference between the opening size S2 on the back side and the opening size S2 on the back side is one-fourth or less of the conventional size, and the dimensional accuracy is improved four times or more.

On the back side of the electron beam exposure mask 21, polycrystalline Si is applied by a sputtering method to form an electron beam scattering layer 11. Of the electron beams 12 applied to the electron beam exposure mask 21, those passing through the opening of the transfer pattern 5 go straight without any obstacle and reach a wafer (not shown) for forming a circuit pattern. . On the other hand, the electron beam 12 irradiated to the thin Si pattern layer 3 does not lose energy in the Si but passes through, but is scattered in various directions by the electron beam scattering layer 11 and hardly goes straight. , Does not reach the wafer. For this reason, the pattern is formed normally without any adverse effect on the resist formed on the wafer.

Here, since the electron beam 12 is scattered in various directions due to the unevenness, it is preferable that the electron beam scattering layer 11 has as many unevenness as possible as fine as possible, and a polycrystalline material is preferable as the material. Here, polycrystalline Si is used for the electron beam scattering layer 11, but tungsten silicide,
Various polycrystalline materials such as molybdenum silicide and titanium silicide can be used.

Although the thickness of the Si pattern layer 3 is 5 microns here, it is not necessarily limited to this thickness. If it is too thin, it may be broken due to insufficient mechanical strength. Therefore, it is desirable to be as thin as possible without breaking it.

The method of manufacturing the electron beam exposure mask 21 according to the present embodiment is similar to the method of manufacturing the electron beam exposure mask described in the conventional example. Since it is only necessary to perform sputtering, it is relatively easy, and the production cost is not much.

FIG. 2 is a sectional view showing the structure of a second embodiment of the mask for electron beam exposure according to the present invention. Here, Si
The thickness of the pattern layer 3 is set to 10
By setting the micron size, the dimensional accuracy is doubled as compared with the dimensional variation width of the conventional example. Here, fine irregularities were formed on the back surface of the Si pattern layer 3 as the electron beam scattering layer 11. This unevenness is similar to the polycrystalline Si of the first embodiment,
Since the electron beam 12 is scattered in various directions, a pattern can be formed on a wafer with high dimensional accuracy by using the electron beam exposure mask 22.

The method of manufacturing the mask 22 for electron beam exposure is the same as that of the conventional method of manufacturing a mask for electron beam exposure. After the mask is completed, the mask is immersed in an alkaline solution such as potassium hydroxide or hydrazine. Since it is only necessary to form fine irregularities by immersion, it is relatively easy and the production cost is not so large. Note that the method of forming the unevenness is not necessarily limited to this method, and any method may be used as long as the unevenness is formed.

Next, a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIGS. 3A, 3B, and 3C are cross-sectional views for explaining a process of manufacturing the electron beam exposure mask 23 according to the present invention.

An electron beam exposure mask 23 shown in FIG.
First, a protective film for wet etching (such as a silicon nitride film) 7 is formed on both sides by CVD on a silicon bonded wafer 13 having a Si pattern layer having a plane orientation (100) and a thickness smaller than that of a conventional one. Form. Next, the resist is patterned to form a resist mask 8 having an opened window.
Then, the protective film 7 for wet etching is removed by dry etching, and the Si wafer 13 is back-etched including the SiO ₂ layer 2 using a wet etching solution obtained by heating an alkaline solution such as potassium hydroxide or hydrazine. The opening 10 is formed. The opening 10 is
The emergence of the plane orientation (111) at the time of wet etching provides a taper. This stage is shown in FIG.
Is shown in

Next, as shown in FIG. 3B, the resist 8 and the wet etching protective film 7 formed on the Si wafer 13 are removed, and a polycrystalline material is formed on the back surface by a method such as sputtering or CVD. Then, an electron beam scattering layer 11 is formed.

Thereafter, the surface of the Si wafer 13 is patterned by lithography and dry etching, and Au is deposited on the surface as a conductive layer 4 by a sputtering method. As shown in FIG. Is completed.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 (a), (b), (c)
FIG. 5 is a cross-sectional view for explaining a step of manufacturing the electron beam exposure mask 24 according to the present invention.

An electron beam exposure mask 24 shown in FIG.
First, a protective film for wet etching (such as a silicon nitride film) 7 is formed on both sides by CVD on a silicon bonded wafer 13 having a Si pattern layer having a plane orientation (100) and a thickness smaller than that of a conventional one. Form. Next, the resist is patterned to form a resist mask 8 having an opened window.
Then, the protective film 7 for wet etching is removed by dry etching, and the Si wafer 13 is back-etched including the SiO ₂ layer 2 using a wet etching solution obtained by heating an alkaline solution such as potassium hydroxide or hydrazine. The opening 10 is formed. The opening 10 is
The emergence of the plane orientation (111) at the time of wet etching provides a taper. This stage is shown in FIG.
Is shown in

Next, as shown in FIG. 4B, the resist 8 formed on the Si wafer 13 is removed, and the resist 8 is further immersed in an alkaline solution such as potassium hydroxide or hydrazine to form fine irregularities on the back side. Electron scattering layer 1
Form one.

Thereafter, the protection film 7 for wet etching formed on the surface of the Si wafer 13 is removed, the surface of the Si wafer is patterned by lithography and dry etching, and Au is deposited as a conductive layer 4 on the surface by sputtering. Then, an electron beam exposure mask 24 is completed as shown in FIG.

Next, a fifth embodiment according to the present invention will be described with reference to FIG. FIG. 5 (a), (b), (c)
FIG. 5 is a cross-sectional view for explaining a step of manufacturing an electron beam exposure mask 25 (see FIG. 5C) according to the present invention.

In the fifth embodiment, the plane orientation (10
0), the bonded portion of the silicon bonded wafer 14 having the pattern layer 3 having a smaller thickness than the conventional
It is made of polycrystalline material 11 instead of iO ₂ . That is, the electron beam scattering layer 11 formed later in the first to fourth embodiments is formed in advance.

First, as shown in FIG. 5A, a protective film (such as a silicon nitride film) 7 for wet etching is formed on both surfaces of the bonded wafer 14 by patterning the surface of the bonded wafer 14 by lithography and dry etching. After that, the resist is patterned, and the wet etching protective film 7 is
Is removed by dry etching, and the window 9 for back etching is removed.
To form

Next, as shown in FIG. 5B, the opening 10 is formed by back-etching the Si wafer 14 using a wet etching solution obtained by heating an alkali solution such as potassium hydroxide or hydrazine. The opening 10 has a taper due to the appearance of the plane orientation (111) during wet etching.

Thereafter, as shown in FIG. 5C, the resist mask 8 and the wet etching protective film 7 are removed, and the conductive layer 4 is deposited on the surface by sputtering. 25 is completed.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments, but includes various embodiments according to the principles of the present invention. For example, in each of the above embodiments, a bonded Si wafer is used as the plate member in the present invention, but the bonded wafer may not be a bonded wafer, and another member may be used instead of the Si wafer.

Further, in each of the above embodiments, the protective film for wet etching is not limited to the Si nitride film, and the conductive layer is not limited to Au.

[0045]

As described above, the mask for electron beam exposure according to the present invention can be used even when the thickness of the Si pattern layer is small.
Since the electron beam scattering layer is formed on the back side of the Si pattern layer, the electron beam passing through the Si pattern layer does not adversely affect the resist pattern on the wafer. Also, S
Since the i-pattern layer is thin, the dimensional accuracy of the mask is high, and a resist pattern with high dimensional accuracy is formed on the wafer. Therefore, there is an effect that high-quality LSI can be produced at a high yield. Further, the method for manufacturing an electron beam exposure mask according to the present invention can be relatively easily manufactured since an electron beam scattering layer may be formed on the back side of a conventional electron beam exposure mask by a sputtering method or the like. It costs little.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of an electron beam exposure mask according to the present invention.

FIG. 2 is a cross-sectional view showing a second embodiment of an electron beam exposure mask according to the present invention.

3 (a), 3 (b) and 3 (c) are cross-sectional views showing the steps of manufacturing an electron beam exposure mask according to a third embodiment of the present invention.

FIGS. 4 (a), (b) and (c) are cross-sectional views showing manufacturing steps of a fourth embodiment of the electron beam exposure mask according to the present invention.

5 (a), 5 (b) and 5 (c) are cross-sectional views showing the steps of manufacturing an electron beam exposure mask according to a fifth embodiment of the present invention.

6A is a plan view of a part of a conventional electron beam exposure mask, and FIG. 6B is a cross-sectional view of FIG.

FIGS. 7A, 7B, 7C, and 7D are cross-sectional views showing steps of manufacturing a conventional electron beam exposure mask.

FIG. 8 is a cross-sectional view of a conventional electron beam exposure mask.

[Explanation of symbols]

Reference Signs List 1 Si layer 2 SiO ₂ layer 3 Si pattern layer 4 Conductive layer 5 Transfer pattern 6, 13, 14 Bonded wafer 7 Protective film for wet etching 8 Resist mask 9 Back etch window 10 Opening 11 Electron beam scattering layer 12 Electron beam

Claims (7)

(57) [Claims] 1. An electron beam exposure mask in which a plurality of drawing opening patterns are formed on a plate member, an electron beam scattering layer for scattering electron beams transmitted through the mask is formed on the back side of the mask. An electron beam exposure mask, comprising: 2. The electron beam exposure mask according to claim 1, wherein the electron beam scattering layer is a polycrystal formed on the back surface of the mask. 3. The electron beam scattering layer is formed by applying at least one polycrystalline material of polycrystalline silicon, tungsten silicide, molybdenum silicide, and titanium silicide on the back surface of the mask by a sputtering method. The mask for electron beam exposure according to claim 2. 4. The electron scattering layer according to claim 1, wherein the electron scattering layer is a layer having an uneven shape formed on the back surface of the mask.
3. The electron beam exposure mask according to 1. 5. A method of manufacturing an electron beam exposure mask for forming a drawing opening pattern on a plate member, wherein after forming a desired pattern on the plate member, the electron beam transmitted through the mask on the back surface of the plate member. A method for manufacturing an electron beam exposure mask, comprising forming an electron beam scattering layer for scattering light. 6. A method of manufacturing an electron beam exposure mask for forming an opening pattern for drawing on a plate member, wherein an electron beam scattering layer for scattering electron beams transmitted through the mask is formed on the back surface of the plate member. Then, a desired pattern is formed on the plate member. 7. A method for manufacturing an electron beam exposure mask for forming an opening pattern for drawing on a plate member, wherein a desired pattern is formed on the plate member on which an electron beam scattering layer for scattering electron beams is formed in advance. A method for manufacturing an electron beam exposure mask, comprising: