JP2976605B2 - Memory module - Google Patents
Memory moduleInfo
- Publication number
- JP2976605B2 JP2976605B2 JP21250991A JP21250991A JP2976605B2 JP 2976605 B2 JP2976605 B2 JP 2976605B2 JP 21250991 A JP21250991 A JP 21250991A JP 21250991 A JP21250991 A JP 21250991A JP 2976605 B2 JP2976605 B2 JP 2976605B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memory device
- memory module
- power supply
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Dram (AREA)
- Semiconductor Memories (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、メモリチップの高密度
な実装に供されるメモリモジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module used for high-density mounting of a memory chip.
【０００２】[0002]
【従来の技術】従来、この種のメモリモジュールとして
は、特願平１−３０３９６３号に係るものがある。この
メモリモジュールは、複数のメモリ装置１を積層して成
り、図４に示すように、メモリ装置１は、絶縁基板２の
一側表面に凹部３を形成し、この凹部３内にメモリチッ
プ４を収納，配設すると共に、絶縁基板２の表面の周縁
部に接続端子５を複数設け、この接続端子５〜５とメモ
リチップ４の電極とを夫々接続配線６で接続されて成
る。このようなメモリ装置１を複数積層したメモリモジ
ュールは、同図に示すように、ピングリッドアレイ７に
搭載されてプリント基板上に実装される。なお、メモリ
装置１を形成する絶縁基板２とピングリッドアレイ７の
材質は、両者の熱膨張率を同じくするため、同一材料が
採用され、主にセラミックスが用いられている。2. Description of the Related Art Conventionally, as a memory module of this type, there is one disclosed in Japanese Patent Application No. 1-303963. This memory module is formed by stacking a plurality of memory devices 1. As shown in FIG. 4, the memory device 1 has a recess 3 formed on one surface of an insulating substrate 2, and a memory chip 4 in the recess 3. And a plurality of connection terminals 5 are provided on the periphery of the surface of the insulating substrate 2, and the connection terminals 5 to 5 are connected to the electrodes of the memory chip 4 by connection wirings 6. A memory module in which a plurality of such memory devices 1 are stacked is mounted on a pin grid array 7 and mounted on a printed board, as shown in FIG. Note that the insulating substrate 2 and the pin grid array 7 forming the memory device 1 are made of the same material because of the same coefficient of thermal expansion, and are mainly made of ceramics.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うなピングリッドアレイ７は、セラミックスを用いて成
形されるため、導配線として、成形時の高熱に耐えるモ
リブデン（Ｍｏ）やタングステン（Ｗ）などの高融点金
属が用いられている。これらの高融点金属は、導電率が
小さいため、特に高速のメモリを備えたメモリ装置にお
いては、高融点金属配線の抵抗分で電源電圧が下がった
り、接地レベルに変動が生じてメモリの特性が悪化する
問題があった。However, since such a pin grid array 7 is formed by using ceramics, the pin grid array 7 is formed of a conductive wire such as molybdenum (Mo) or tungsten (W) that can withstand high heat during forming. Refractory metals are used. Since these refractory metals have low electrical conductivity, especially in a memory device having a high-speed memory, the power supply voltage decreases due to the resistance of the refractory metal wiring, or the ground level fluctuates, thereby deteriorating the characteristics of the memory. There was a problem that got worse.
【０００４】また、このような積層タイプのメモリモジ
ュールでは、実装密度が高いため、全体としてより大き
な電源供給能力が要求されるが、図４に示すように、パ
スコンデンサー８などの電源強化のための部品を、メモ
リモジュールの外に置いていた。このため、電流パスが
長くなり、特にパルシブな電源電流に対しては、電流パ
スのインダクタンスの悪影響が避けられない問題があっ
た。また、信号がメモリ装置の積層方向に伝搬するた
め、例えば最上層のメモリ装置に信号の反射によるノイ
ズに起因して特性の悪化を惹起する問題があった。[0004] Further, in such a stacked type memory module, a higher power supply capability is required as a whole due to a high mounting density. However, as shown in FIG. Was placed outside the memory module. For this reason, the current path is lengthened, and there is a problem that the adverse effect of the inductance of the current path is unavoidable especially for a pulsative power supply current. In addition, since the signal propagates in the stacking direction of the memory device, there is a problem in that the characteristics of the memory device in the uppermost layer are deteriorated due to noise due to signal reflection.
【０００５】本発明は、このような従来の問題点に着目
して創案されたものであって、工程を増やすことなく、
簡単に電源のインピーダンスを大幅に低下できると共
に、信号の反射によるノイズの発生を防止した特性の良
好なメモリモジュールを得んとするものである。[0005] The present invention has been made in view of such conventional problems, and without increasing the number of steps.
An object of the present invention is to provide a memory module which can easily greatly reduce the impedance of a power supply and has good characteristics in which noise generation due to signal reflection is prevented.
【０００６】[0006]
【課題を解決するための手段】そこで、本発明は、絶縁
基板の一側表面に凹部を形成し、該凹部内にメモリチッ
プを収納，配設すると共に、前記絶縁基板の表面の周縁
部に接続端子を複数設け、該端子と前記メモリチップの
電極とを夫々接続してなるメモリ装置を複数積層してな
るメモリモジュールにおいて、前記メモリ装置の一つに
電源強化用コンデンサ、及び終端抵抗が内蔵されている
ことを、その解決手段としている。SUMMARY OF THE INVENTION Accordingly, the present invention provides a method for forming a concave portion on one side surface of an insulating substrate, accommodating and disposing a memory chip in the concave portion, and forming a concave portion on a peripheral portion of the surface of the insulating substrate. In a memory module having a plurality of connection terminals, and a plurality of memory devices each having the terminals and the electrodes of the memory chip connected to each other, a power supply enhancement capacitor and a terminating resistor are incorporated in one of the memory devices. That is the solution.
【０００７】[0007]
【作用】電源強化用コンデンサは、メモリ装置側への電
源供給能力を強化し、電源のインピーダンスを低下させ
る作用を奏する。また、終端抵抗を積層されたメモリ装
置ユニットに内蔵することにより、信号の反射によるノ
イズの発生を防止し、良好な特性を維持させる作用を有
する。The power supply enhancement capacitor has the function of enhancing the power supply capability to the memory device side and reducing the impedance of the power supply. In addition, by incorporating the terminating resistor in the stacked memory device unit, it has an effect of preventing generation of noise due to signal reflection and maintaining good characteristics.
【０００８】[0008]
【実施例】以下、本発明に係るメモリモジュールの詳細
を図面に示す実施例に基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of a memory module according to the present invention will be described below based on embodiments shown in the drawings.
【０００９】本実施例においては、図１に示すように、
複数のメモリ装置ユニット１０を積層すると共に、これ
らメモリ装置ユニット１０〜１０の上には、電源強化用
コンデンサ（パスコンデンサ）Ｃ及び終端抵抗Ｒ1，Ｒ2
を内蔵したメモリ装置ユニット１１をさらに積層してメ
モリモジュールＡが構成される。また、メモリモジュー
ルＡは、ピングリッドアレイＢに搭載されてプリント基
板（図示省略する）に実装されるようになっている。In this embodiment, as shown in FIG.
A plurality of memory device units 10 are stacked, and a power supply enhancing capacitor (pass capacitor) C and terminating resistors R 1 , R 2 are provided on the memory device units 10 to 10.
Are further stacked to form the memory module A. The memory module A is mounted on a pin grid array B and mounted on a printed circuit board (not shown).
【００１０】メモリ装置ユニット１０は、図３に示すよ
うに、略正方形状の絶縁基板１５の一側表面に形成した
凹部１５Ａに２つのメモリチップ１４が配設されて大略
構成されている。また、絶縁基板１５の周縁には、他の
メモリ装置１０との接続に供される接続端子１６が所定
の間隔を隔てて複数配設されている。そして、メモリチ
ップ１４の取り出し電極１４ａ〜１４ａと接続端子１６
〜１６とは、夫々ボンデングワイヤ１７及び内部配線１
８を介して接続されている。As shown in FIG. 3, the memory device unit 10 is generally constructed by arranging two memory chips 14 in a concave portion 15A formed on one surface of a substantially square insulating substrate 15. A plurality of connection terminals 16 provided for connection to another memory device 10 are provided at a predetermined interval on the periphery of the insulating substrate 15. Then, the extraction electrodes 14a to 14a of the memory chip 14 and the connection terminals 16
16 to the bonding wire 17 and the internal wiring 1 respectively.
8 are connected.
【００１１】また、最上層に積層されるメモリ装置ユニ
ット１１は、図１及び図２に示すように、絶縁基板１５
上に電源強化用コンデンサＣと、終端抵抗Ｒ1，Ｒ2がア
ドレスバス，データバス，コントロールバスの夫々のラ
インに一対設けられている。また、電源強化用コンデン
サＣは、電源線（Ｖｃｃ）に一つ接続されていればよ
い。なお、図４は、メモリチップ１４と電源強化用コン
デンサＣと終端抵抗Ｒ1，Ｒ2を表わした等価回路を示し
ている。As shown in FIGS. 1 and 2, the memory device unit 11 stacked on the uppermost layer
A pair of a power supply enhancing capacitor C and terminating resistors R 1 and R 2 are provided on each line of an address bus, a data bus, and a control bus. Further, it is sufficient that one power supply enhancing capacitor C is connected to the power supply line (Vcc). FIG. 4 shows an equivalent circuit representing the memory chip 14, the power supply enhancing capacitor C, and the terminating resistors R 1 and R 2 .
【００１２】本実施例においては、メモリモジュールＡ
の最上層のメモリ装置ユニット１１に、終端抵抗Ｒ1，
Ｒ2を夫々のライン（アドレスライン，データライン，
コントロールライン）に設けているため、信号の反射に
よるノイズに起因する特性の悪化を防止することが出来
る。In this embodiment, the memory module A
, The terminal resistance R 1 ,
R 2 is assigned to each line (address line, data line,
(Control line), it is possible to prevent deterioration of characteristics caused by noise due to signal reflection.
【００１３】また、メモリ装置ユニット１１に電源強化
用コンデンサＣを内蔵させたため、抵抗率の大きいピン
グリッドアレイを用いても、電圧降下や、接地レベルの
変動を生じさせることがなく、メモリの特性が悪化する
のを防止できる。Further, since the power supply enhancement capacitor C is built in the memory device unit 11, even if a pin grid array having a large resistivity is used, a voltage drop and a fluctuation in the ground level do not occur, and the characteristics of the memory are not changed. Can be prevented from becoming worse.
【００１４】以上、実施例について説明したが、本発明
は、これに限定されるものではなく、構成の要旨に付随
する各種の設計変更が可能である。Although the embodiment has been described above, the present invention is not limited to this, and various design changes accompanying the gist of the configuration are possible.
【００１５】例えば、上記実施例においては、電源強化
用コンデンサＣを絶縁基板１５に実装したが、絶縁基板
１５に直接製造してもよく、また、終端抵抗Ｒ1，Ｒ2は
印刷抵抗や実装されたチップ抵抗であってもよい。For example, in the above-described embodiment, the capacitor C for reinforcing the power supply is mounted on the insulating substrate 15, but it may be manufactured directly on the insulating substrate 15, and the terminating resistors R 1 and R 2 may be printed resistors or mounting resistors. A chip resistor may be used.
【００１６】また、上記実施例においては、メモリモジ
ュールＡの最上層に、電源強化用コンデンサＣ及び終端
抵抗Ｒ1，Ｒ2を内蔵したメモリ装置ユニット１１を配設
したが、積層の中間に挿入した配置としても同様の作用
・効果を得ることが可能である。In the above embodiment, the memory device unit 11 including the power supply enhancing capacitor C and the terminating resistors R 1 and R 2 is disposed at the uppermost layer of the memory module A. The same operation and effect can be obtained even with such an arrangement.
【００１７】さらに、上記実施例においては、メモリ装
置ユニット１０中に２つのメモリチップ１４を設けた
が、これに限定されるものではなく、適宜変更が可能で
ある。Furthermore, in the above embodiment, two memory chips 14 are provided in the memory device unit 10, but the present invention is not limited to this, and can be changed as appropriate.
【００１８】[0018]
【発明の効果】以上の説明から明らかなように、本発明
に係るメモリモジュールは、工程を増やすことなく、電
源強化用コンデンサを内蔵させることが出来、電源のイ
ンピーダンスを大幅に低下させると共に、電流パスが短
くなり電流パスのインダクタンスの悪影響を防止する効
果がある。一つのメモリ装置ユニットに終端抵抗を備え
た構成としたことにより、モジュール全体における信号
の反射によるノイズ発生を防止出来、メモリの特性の悪
化を低減させる効果を有する。As is apparent from the above description, the memory module according to the present invention can incorporate a power supply strengthening capacitor without increasing the number of steps, greatly reducing the impedance of the power supply and reducing the current. The path is shortened, which has the effect of preventing the adverse effect of the inductance of the current path. With a configuration in which one memory device unit is provided with a terminating resistor, generation of noise due to signal reflection in the entire module can be prevented, and there is an effect of reducing deterioration of memory characteristics.
【図１】本発明の実施例を示す斜視図。FIG. 1 is a perspective view showing an embodiment of the present invention.
【図２】本発明の実施例のメモリ装置の断面図。FIG. 2 is a sectional view of a memory device according to an embodiment of the present invention.
【図３】本発明の実施例のメモリ装置の断面図。FIG. 3 is a sectional view of a memory device according to an embodiment of the present invention.
【図４】本実施例の等価回路図。FIG. 4 is an equivalent circuit diagram of the present embodiment.
【図５】従来例の斜視図。FIG. 5 is a perspective view of a conventional example.
Ａ…メモリモジュール、Ｂ…ピングリッドアレイ、１０
…メモリ装置ユニット、１１…メモリ装置ユニット、１
４…メモリチップ、１５…絶縁基板、Ｃ…電源強化用コ
ンデンサ、Ｒ1，Ｒ2…終端抵抗。A: memory module, B: pin grid array, 10
... Memory device unit, 11 ... Memory device unit, 1
4 ... memory chip, 15 ... insulating substrate, C ... power reinforcing capacitor, R 1, R 2 ... terminating resistor.
Claims (1)
凹部内にメモリチップを収納，配設すると共に、前記絶
縁基板の表面の周縁部に接続端子を複数設け、該端子と
前記メモリチップの電極とを夫々接続してなるメモリ装
置ユニットを複数積層してなるメモリモジュールにおい
て、 前記メモリ装置ユニットの一つに電源強化用コンデン
サ、及び終端抵抗が内蔵されていることを特徴とするメ
モリモジュール。A concave portion is formed on one surface of an insulating substrate, a memory chip is accommodated and disposed in the concave portion, and a plurality of connection terminals are provided on a peripheral portion of a surface of the insulating substrate. A memory module formed by stacking a plurality of memory device units each connected to an electrode of a memory chip, characterized in that one of the memory device units has a built-in capacitor for enhancing power and a terminating resistor. Memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21250991A JP2976605B2 (en) | 1991-08-26 | 1991-08-26 | Memory module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21250991A JP2976605B2 (en) | 1991-08-26 | 1991-08-26 | Memory module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555450A JPH0555450A (en) | 1993-03-05 |
| JP2976605B2 true JP2976605B2 (en) | 1999-11-10 |
Family
ID=16623852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21250991A Expired - Fee Related JP2976605B2 (en) | 1991-08-26 | 1991-08-26 | Memory module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2976605B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3461204B2 (en) * | 1993-09-14 | 2003-10-27 | 株式会社東芝 | Multi-chip module |
| US5701233A (en) * | 1995-01-23 | 1997-12-23 | Irvine Sensors Corporation | Stackable modules and multimodular assemblies |
| DE10107839A1 (en) | 2001-02-16 | 2002-09-05 | Philips Corp Intellectual Pty | Arrangement with an integrated circuit mounted on a carrier and a power supply assembly |
| JP5261974B2 (en) * | 2007-05-08 | 2013-08-14 | 日本電気株式会社 | Mounting board with built-in components |
-
1991
- 1991-08-26 JP JP21250991A patent/JP2976605B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0555450A (en) | 1993-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3051011B2 (en) | Power module | |
| JP3232562B2 (en) | Electromagnetic interference suppression component and electromagnetic interference suppression circuit | |
| JPH0828573B2 (en) | Multilayer printed circuit board | |
| US5666004A (en) | Use of tantalum oxide capacitor on ceramic co-fired technology | |
| JPH0513967A (en) | Semiconductor storage control device and high density mounting method therefor | |
| JPH0513666A (en) | Complex semiconductor device | |
| US6670692B1 (en) | Semiconductor chip with partially embedded decoupling capacitors | |
| JP2976605B2 (en) | Memory module | |
| JPH05102648A (en) | Printed board | |
| JPH0318112A (en) | Fitting structure for chip type noise filter | |
| JPH07147378A (en) | Semiconductor module and ic package used for it | |
| JP3514221B2 (en) | Printed wiring board | |
| JPH0851171A (en) | Semiconductor ceramic package | |
| JPH0653414A (en) | Microwave integrated circuit | |
| US20040055782A1 (en) | Surface-mounting type electronic circuit unit having no melting of solder attaching electric part thereto | |
| US7187065B2 (en) | Semiconductor device and semiconductor device unit | |
| JP2001118948A (en) | Substrate for mounting semiconductor element | |
| JP3337368B2 (en) | Relay board | |
| JPS605055B2 (en) | semiconductor equipment | |
| JP3203806B2 (en) | Semiconductor device mounting structure | |
| JP3308448B2 (en) | Terminating resistor array and substrate having the same | |
| JP2572626Y2 (en) | Multilayer circuit board | |
| JPH012345A (en) | Semiconductor integrated circuit device | |
| JPS634662A (en) | Electronic circuit device | |
| JP2919010B2 (en) | Semiconductor integrated circuit mounting structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |