JP2968727B2 - Light operation check device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a write operation check device, and more particularly to a write operation check device for writing data from a processor to system resources.

[0002]

2. Description of the Related Art When data is written from a processor to a system resource such as a memory or an I / O device, a wait for completion of a write operation may occur depending on a system control mode. Normally, an area that does not affect the operation is read with a dummy. This is because data cannot be received unless all the write buffers are flushed out in the read operation. Japanese Patent Application Laid-Open No. 5-282205 proposes an efficient operation. When an area that does not affect the actual operation is read with a dummy, the result is not necessary because it is merely a dummy read. To eliminate the disadvantage of having to wait until the result is returned even after the buffer becomes empty, a high-speed dummy read register is provided, and by accessing this register, an area that does not affect actual operation The dummy read is not performed.

[0003]

However, in the above-mentioned prior art, the efficiency of dummy reading is improved by providing a high-speed register for dummy reading.
Since the processor confirms completion of the write operation, there is still a problem that a decrease in system throughput cannot be refused.

[0004] It is an object of the present invention that a processor checks whether or not all the write data held in a write buffer has been flushed out, and determines whether or not the write data held in the write buffer has been completely swept out and the target has been sent to the target. By using a dedicated write buffer control unit status check register for checking whether or not the write access has been completed, there is no need to generate a dummy read cycle as in the related art, and a write for preventing a decrease in system throughput. An object of the present invention is to provide an operation check device.

[0005]

According to the apparatus of the present invention, a write request from a processor to a target is temporarily held in a write buffer, and even when the write to the target is not actually completed, the write buffer is transmitted to the processor. In the write operation confirmation device in the information processing device that returns a response, the write operation performed by the processor, when the processor confirms whether the write operation has actually reached the target and the write operation is truly completed,
Upon receiving the access from the processor, all the write data held in the write buffer before the access operation is swept out, and reaches the target, and when the write operation is completed, a response signal of the access operation is generated. A write buffer control unit status check register to be returned is provided.

According to the present invention, the processor determines whether or not all the write data held in the write buffer has been flushed out, and determines whether the write data held in the write buffer has been completely swept out and the write access to the target has been completed. This is performed using a dedicated write buffer control unit status check register for checking whether or not the writing has been completed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention, which includes a processor 1, a write buffer 2, a write buffer control unit status register 3, two targets 5a, 5
b. Here, the target is a memory, an I / O
It refers to system resources such as devices.

The processor 1 executes a write access to the targets 5a and 5b via the system bus 4.
Assuming now that a write access has been performed to the target 5a, if access from the processor 1 is received before the writing of the target data to the target 5a is completed, the write buffer 2 returns a response to the processor 1, and From the viewpoint of No. 1, it appears that the write operation has been completed.

If the write data held in the write buffer 2 is completely swept out by the control mode of the system and it is desired to confirm whether or not the write access to the target is completed, the write buffer control unit The status check register 3 is accessed for reading or writing. When the write buffer control unit status check register 3 receives an access from the processor 1, it checks the status of the write buffer 2 and does not return a response to the processor 1 until all the held data is flushed out.

Next, this embodiment will be described in detail with reference to FIG.

FIG. 2 shows the essential parts of the write buffer 2 and the write buffer control unit status check register 3. The write buffer 2 comprises a FIFO 2a, a write buffer control unit 2b and an address decoder 2c. As shown in FIG. 2, the write request from the processor 1 has Address / Data / Transfer Type set to FIFO.
Reserved by being stored in O2. At this point, the write buffer control unit 2b returns a response 2F to the processor 1, and the write cycle from the processor 1 ends apparently.

Here, the information held in the FIFO 2a is held until the write access to the target is completed. This FIFO has a storage capacity of three stages (2a1, 2a2, 2a3 in FIG. 2) in this embodiment, and the data stored earlier is output first. The notification that the write access to the target is completed is received by the write buffer control unit 2b from the target (5a, 5b in FIG. 1). Upon receiving this signal, the write buffer control unit 2b sends a clear instruction 2G for the information to the FIFO 2a, and the FIFO 2a clears the information.

In response to a write request from the processor 1,
When the FIFO 2a is full, the write buffer control unit 2b grasps the state by the FC signal 2H indicating the number of stages where valid data from the FIFO 2a exists, and does not return a response 2F to the processor 1.

Now, if the write data held in the FIFO 2a is completely swept out for the sake of convenience of the system and it becomes necessary to check whether or not the write access to the target has been completed, the processor 1 executes the write operation. Either read 2D or write 2E is accessed to the buffer controller status check register 3. In this case, if the address decode circuit 2C determines that the write buffer control unit status check register 3a is accessed, the decode signal 2L selects the write buffer control unit check register 3a.

The write buffer control unit status check register 3 grasps the status by the FC signal 2H indicating the number of stages in which valid data exists from the FIFO 2a (2J in FIG. 2).
Then, the write data held in the FIFO 2a is completely swept out, and a response signal 3B is returned to the write buffer control unit 2b when the write access to the target is completed.
In response to this, the write buffer control unit 2b returns a response to the processor 1, and the write data held in the FIFO 2a is completely swept out, and the check as to whether the write access to the target has been completed is completed. I do.

[0017]

As described above, according to the present invention, it is determined whether or not all the write data held in the write buffer has been flushed out, and the write data held in the write buffer is completely swept out. Since it is configured to use a dedicated write buffer control unit status check register to check whether write access to the target has been completed, there is no need to generate a dummy read cycle, which has been performed conventionally, and When all the write data held in a certain write buffer has been flushed out, the processor can immediately confirm the state, so that there is no useless processing time compared to the conventional case where the dummy read compensated. Having.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a detailed view of the embodiment shown in FIG.

[Explanation of symbols]

 1 Processor 2 Write buffer 3 Write buffer control unit status check register 4 System bus 5a, 5b Target 2a FIFO 2b Write buffer control unit 2c Address decoder 3 Write buffer control unit status check register

Claims (3)

(57) [Claims] 1. A write request from a processor to a target is temporarily held in a write buffer, and even when writing to the target is not actually completed, the write buffer checks a write operation in the information processing apparatus that returns a response to the processor. In the apparatus, when the write operation performed by the processor reaches the target and confirms whether or not the write operation is truly completed, the processor receives an access from the processor and performs the access operation. A write buffer control unit status check register that returns a response signal of the access operation is provided when all the write data previously held in the write buffer is swept out, reaches the target, and completes the write operation. A light operation check device characterized by the above-mentioned. 2. The write operation check device according to claim 1, wherein the access is a read. 3. The write operation checking device according to claim 1, wherein the access is a write.