JP2967063B2 - Single electron transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-electron transistor which is one of semiconductor devices based on a new operation principle, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, a single-electron transistor has been proposed as one of semiconductor devices based on a new operation principle. In single-electron transistors, tunnel barrier layers are provided between the source layer and the island layer and between the drain layer and the island layer, and the gate voltage changes the potential of the island layer to control electron tunneling. Controls on / off of the device.

FIGS. 18 and 19 are process sectional views showing a conventional method for manufacturing a single-electron transistor.

First, as shown in FIG. 18A, a 400-nm-thick silicon oxide film 82 is formed on the entire surface of a p-type silicon substrate 81 by a thermal oxidation method. Next, as shown in FIG. 2A, a polycrystalline silicon film 83 having a thickness of 30 nm is formed on the silicon oxide film 82 by LPCVD. As a result, an SOI substrate is obtained. Thereafter, an n-type impurity is introduced into the polycrystalline silicon film 83 by, for example, an ion implantation method.

Next, as shown in FIG. 18B, the polycrystalline silicon film 83 is processed into an island shape by anisotropic etching such as RIE. Next, as shown in FIG. 2B, a groove is formed on the surface of the polycrystalline silicon film 83 by anisotropic etching such as RIE, and tunnel barrier layers 85 and 87 are formed. To the source layer 84, the first tunnel barrier layer 85, the island layer 86, and the second
Are divided into a tunnel barrier layer 87 and a drain layer 88. The source layer 84 is connected to the island layer 86 via the tunnel barrier layer 85, and the drain layer 88 is connected to the island layer 86 via the tunnel barrier layer 87.

Next, as shown in FIG. 18C, a gate oxide film 8 made of a silicon oxide film having a thickness of 100 nm is formed on the entire surface.
9 is formed by the LPCVD method. Next, as shown in FIG. 4C, a 200 nm-thickness to be the gate electrode 90 is formed on the entire surface.
After forming the polycrystalline silicon film by the LPCVD method,
This polycrystalline silicon film is processed by anisotropic etching such as RIE to form a gate electrode 90.

Next, as shown in FIG. 19A, an interlayer insulating film 91 made of a silicon oxide film having a thickness of 500 nm is formed on the entire surface.
Is formed by the CVD method, a contact hole 92 is formed in the interlayer insulating film 91.

[0008] Next, as shown in FIG.
An Al film containing 1% of Si to be the l wiring 93 is formed by a sputtering method, and the Al film is patterned to form an Al wiring 93 on the source layer 84, the gate electrode 90, and the drain layer 88, respectively.

Finally, a sintering process in a forming gas atmosphere at 450 ° C. and a thickness of 1
It is completed through a film formation process of a 00 nm silicon oxide film (not shown).

Incidentally, this kind of conventional single electron transistor has the following problems.

Conventionally, lithography has been used in the step of forming grooves on the surface of the polycrystalline silicon film 83 and forming the tunnel barrier layers 85 and 87. For this reason, the minimum width of the groove is determined by the lithographic exposure limit, and is approximately 100n.
About m was the limit in a practical sense. Therefore, there is a problem that it is difficult to reduce the width of the tunnel barrier layers 85 and 87 and to miniaturize the device.

Further, since the widths of the tunnel barrier layers 85 and 87 cannot be reduced, even if an on-voltage is applied to the gate electrode 90, a tunnel effect is unlikely to occur and the element does not operate normally. Was.

On the other hand, in order to obtain a sufficient current without changing the width, it is necessary to increase the thickness of the tunnel barrier layers 85 and 87 and to lower the potential of the tunnel barrier layers 85 and 87 for electrons. In this case, if the temperature is not low, electrons flow even in a state where no on-voltage is applied to the gate electrode 90, so that there is a problem that the element does not operate normally. That is, in this case, it is difficult to increase the operating temperature.

Further, if the island layer 86 and the source layer 84 are separated and the tunnel barrier layer 85 and the island layer 86 and the drain layer 88 are separated and the tunnel barrier layer 87 is formed equally, the Coulomb step does not appear in the current-voltage characteristics. However, the characteristics of a single-electron transistor cannot be fully utilized. Therefore, it is necessary to form the tunnel barrier layers 85 and 87 asymmetrically by changing the width of the two grooves.

However, when changing the width of the two grooves,
Due to the processing limit mentioned above, the width of the narrower groove is 100 nm
The width of the wider groove is a larger value because it is limited to the value of the degree. As a result, miniaturization becomes more difficult, and the above-mentioned restrictions on the operating temperature become more severe.

Conventionally, the lithography process for forming the island layer 86 and the lithography process for forming the gate electrode 90 are different processes. For this reason, the gate electrode 90 must be formed larger than the island layer 86 in consideration of misalignment in the lithography process. That is, the gate electrode 90 needs to be large enough to overlap the source layer 84 and the drain layer 88.

As a result, the gate electrode 90 and the source layer 84
Unnecessary capacitance is formed between the gate electrode 90 and the drain layer 88 during this period, which also causes a problem that the operating temperature is lowered.

[0018]

As described above, the conventional single-electron transistor has a problem that the width of the tunnel barrier layer is limited by the exposure limit of photolithography, and it is difficult to miniaturize the transistor. Also, the size of the gate electrode is limited by the alignment accuracy of photolithography,
As a result, there has been a problem that the gate electrode cannot be reduced in size.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a fine single-electron transistor which is not limited to an exposure limit or alignment accuracy of photolithography, and a method of manufacturing the same. It is in.

[0020]

[Means for Solving the Problems]

[Structure] In order to achieve the above object, a single electron transistor according to the present invention (claim 1) comprises an island layer and a source layer connected to the island layer via a thinner first tunnel barrier layer. A drain layer connected to the island layer through a second tunnel barrier layer thinner than the drain layer, and disposed so as to sandwich the island layer with the source layer; and a gate insulating film on the island layer. And a gate electrode that does not overlap the source layer and the drain layer.

Here, it is preferable that the first tunnel barrier layer and the second tunnel barrier layer have different energy barriers for carriers. To achieve this, for example, the first tunnel barrier layer and the second tunnel barrier layer are different in at least one of thickness and width.

According to a second aspect of the present invention, there is provided a method of manufacturing a single-electron transistor, comprising the steps of: forming a gate electrode on a partial region of a semiconductor layer via a gate insulating film; forming a gate sidewall insulating film on side walls of the gate insulating film, Oyo the gate sidewall insulating film
The surface of the semiconductor layer not covered with the fine said gate insulating film, and the gate sidewall insulation films forming a mask insulating film material are different, after selectively removing the gate sidewall insulation film, said By using the mask insulating film, the gate insulating film and the gate electrode as a mask, the surface of the semiconductor layer exposed by removing the gate side wall insulating film is oxidized to form a groove, thereby forming the semiconductor layer as an island layer. A first tunnel barrier layer thinner than the island layer, a source layer connected to the island layer via the first tunnel barrier layer, a second tunnel barrier layer thinner than the island layer, Connecting to the island layer via a second tunnel barrier layer, and separating the island layer with the source layer into a drain layer sandwiching the island layer. The features.

According to a third aspect of the present invention, there is provided a method of manufacturing a single-electron transistor, comprising: forming a gate electrode on a partial region of a semiconductor layer via a gate insulating film; forming a gate sidewall insulating film on side walls of the gate insulating film, Oyo the gate sidewall insulating film
The surface of the semiconductor layer not covered with the fine said gate insulating film, and the gate sidewall insulation films forming a mask insulating film material are different, after selectively removing the gate sidewall insulation film, said By using the mask insulating film, the gate insulating film and the gate electrode as a mask, the surface of the semiconductor layer exposed by removing the gate side wall insulating film is etched to form a groove, thereby forming the semiconductor layer as an island layer. A first tunnel barrier layer thinner than the island layer, a source layer connected to the island layer via the first tunnel barrier layer, a second tunnel barrier layer thinner than the island layer, a step of dividing the second through the tunnel disabled <br/> wall layer connected to the island layer, and the drain layers sandwiching said island layer together with the source layer Characterized in that it has.

Here, in order to make the first tunnel barrier layer and the second tunnel barrier layer different in at least one of the thickness and the width, for example, before forming the groove, It is preferable to implant impurity ions into the surface of the semiconductor layer from a direction oblique to the semiconductor layer.

Thus, at least one of the concentration and distribution of the impurity ions is changed between the portion where the first tunnel barrier layer is formed and the portion where the second tunnel barrier layer is formed, and the oxidation rate and the etching rate are changed. Since the rate is changed, at least one of the thickness and the width can be easily changed.

Although the present invention is called a single-electron transistor, carriers are not limited to electrons, and may be holes.

[Operation] In the single-electron transistor having the structure of the present invention (claim 1), the width value of the tunnel barrier layer is reduced by the exposure limit of photolithography by the manufacturing method of the present invention (claims 2 and 3). Can be smaller than the value determined by

Further, since the width of the tunnel barrier layer can be reduced, the probability of tunneling of carriers increases, and when an on-voltage is applied to the gate electrode, the element can be reliably turned on. Further, since the tunnel probability of carriers is high, a sufficient amount of current can be secured without increasing the thickness of the tunnel barrier layer. Therefore, the operating temperature is not limited to a low temperature.

Further, according to the present invention, since the gate electrode does not overlap the source layer and the drain layer, unnecessary parasitic capacitance which has conventionally existed is eliminated, and the operating temperature is prevented from lowering due to the unnecessary parasitic capacitance. become able to.

Here, if the first tunnel barrier layer and the second tunnel barrier layer have different energy barriers for carriers, a Coulomb staircase appears in the current-voltage characteristics, and the characteristics of the single electron transistor are reduced. You will be able to take full advantage of it. That is, although the tunnel phenomenon is originally due to the wave nature of electrons, electrons (holes) are expected to tunnel one by one in particles.

The essence of the forming method according to the present invention is to form a groove defining a tunnel barrier layer in a self-aligning manner, to eliminate misalignment with a gate electrode, and to form a fine structure smaller than an exposure limit of lithography. It is in.

In the present invention (claim 2), first, a gate portion (gate insulating film, gate electrode), a gate sidewall insulating film, and a mask insulating film are formed, and then the gate sidewall insulating film is selectively removed. The surface of the semiconductor layer is selectively exposed. Next, using the gate portion and the mask insulating film as a mask, the exposed surface of the semiconductor layer is oxidized to form a trench in which the oxide film is embedded.

Here, the gate side wall insulating film can be formed thin, for example, by forming an insulating film as the gate side wall insulating film over the entire surface and performing anisotropic etching (etch back). The width value of the exposed surface of the semiconductor layer, which is obtained by selectively removing the film, can be made smaller than the value determined by the exposure limit of photolithography.

Therefore, a groove narrower than the width limited by the exposure limit of photolithography can be formed. Further, since the groove can be formed in a self-aligned manner with respect to the gate electrode, the gate electrode can be formed to have a size that does not overlap the source layer and the drain layer. Since the material of the mask insulating film is different from that of the gate sidewall insulating film, the gate sidewall insulating film can be easily and selectively removed.

In the present invention (claim 3), after forming a gate insulating film, a gate electrode, a gate side wall insulating film, and a mask insulating film, the exposed surface of the semiconductor layer which appears by removing the gate side wall insulating film is removed. The grooves are formed by etching.

Here, as in the case of the above invention (claim 2), the gate sidewall insulating film can be formed thin, so that a groove narrower than the width limited by the exposure limit of photolithography can be formed. Further, as in the case of the above invention (claim 2), the gate electrode can be formed to have a size that does not overlap the source layer and the drain layer.

Here, in the above inventions (claims 2 and 3), if impurity ions are implanted obliquely to the surface of the semiconductor layer, the concentration and distribution of the impurity ions will be different from the gate electrode. .

If there is such a difference in the concentration and distribution, the amount of oxidation and the amount of etching when forming the trench change with the gate electrode as a boundary, and the first and second tunnel barriers having different depths and widths. A layer is formed. As a result, a Coulomb step appears in the current-voltage characteristics, and the characteristics of the single-electron transistor can be fully utilized.

[0039]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 are process sectional views showing a method for manufacturing a single-electron transistor according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a 400 nm thick silicon oxide film 2 is formed on the entire surface of a p-type silicon substrate 1.
Is formed by a thermal oxidation method, and then the silicon oxide film 2 is formed.
A polycrystalline silicon film 3 having a thickness of 30 nm is formed thereon by an LPCVD method. As a result, an SOI substrate is obtained. It should be noted that the SOOX method is used by another method such as the SIMOX method or the bonding method.
An I substrate may be manufactured.

Next, as shown in FIG. 1B, the polycrystalline silicon film 3 is processed into an island shape by anisotropic etching such as RIE (mesa type element isolation). Next, as shown in FIG. 3B, for example, As ions 4 are implanted into the polycrystalline silicon film 3 under the conditions of an acceleration voltage of 50 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 1C, a surface of the polycrystalline silicon film 3 having a thickness of, for example, 20 n
m oxide film 5 is formed by thermal oxidation. Next, FIG.
As shown in FIG.
A 0 nm polycrystalline silicon film 6 is formed by the LPCVD method.

Next, as shown in FIG. 1D, the polycrystalline silicon film 6 and the oxide film 5 are processed by anisotropic etching such as RIE, and the gate electrode 6 and the gate oxide film 5 are processed.
To form

Next, as shown in FIG. 2A, after a silicon oxide film to be the gate side wall silicon oxide film 7 is formed on the entire surface, the entire surface of the silicon oxide film is etched back by anisotropic etching such as RIE. Then, a gate sidewall silicon oxide film 7 having a thickness of, for example, 10 nm is formed on the sidewalls of the gate electrode 6 and the gate oxide film 5.

Next, as shown in FIG. 2A, a silicon nitride mask film, for example, a 1000 nm-thick silicon nitride film is formed on the entire surface, and this silicon nitride film is etched back to form a gate side wall silicon oxide film. A silicon nitride mask film 8 is selectively formed on the surface of polycrystalline silicon film 3 not covered with gate oxide film 7 and gate oxide film 5.

Next, as shown in FIG. 2B, the gate sidewall silicon oxide film 7 is selectively removed using, for example, a hydrofluoric acid solution, and the exposed surface of the polycrystalline silicon film 3 is thermally oxidized. Then, a groove is formed in a self-aligning manner by forming an oxide film 9.

As a result, the polysilicon film 3
Source layer 10, first tunnel barrier layer 11, island layer 12, second tunnel barrier layer 13, and drain layer 1
4 are formed. Thereafter, the silicon nitride mask film 8 used as a mask during the above oxidation is removed using, for example, a hot phosphoric acid solution.

Since the thickness of the gate side wall silicon oxide film 7 is 10 nm, the width of the groove formed by oxidizing the exposed surface is about the same. In the case of the conventional method, the width of the groove is limited by the exposure limit of lithography, and the limit is about 100 nm. Therefore, according to the present embodiment, a groove that is approximately one digit smaller can be formed.

In the case of the present embodiment, the width of the trench, that is, the width of the tunnel barrier layers 11 and 13 is determined mainly by the thickness of the gate side wall silicon oxide film 7, and the thickness of the gate side wall silicon oxide film 7 is etched. It is limited by the accuracy of the film thickness that can be left by the back, and even with the current technology, an accuracy of about 10 nm can be secured.

As described above, according to the present embodiment, the width of the tunnel barrier layers 11 and 13 can be made sufficiently small, so that miniaturization of the device can be easily achieved.

Further, since the width of the tunnel barrier layers 11 and 13 can be reduced, the probability of electron tunneling increases, and when an on-voltage is applied to the gate electrode 6, the element can be reliably turned on. . Further, since the tunneling probability of electrons is high, a sufficient amount of current can be secured without increasing the thickness of the tunnel barrier layers 11 and 13. Therefore, the operating temperature is not limited to a low temperature.

The source layer 10 and the drain layer 14 are also formed in a self-alignment manner at the same time as the grooves. Gate electrode 6
The source layer 10 and the drain layer 14 are formed outside the gate electrode 6. Therefore, the gate electrode 6 does not overlap with the source layer 10 and the drain layer 14, and unnecessary capacitance does not occur. As a result, it is possible to prevent the operating temperature from rising due to this kind of unnecessary capacitance.

Finally, similarly to the conventional method, as shown in FIG. 2C, an interlayer insulating film 15 is formed on the entire surface, and a contact hole is formed in the interlayer insulating film 15, and then A is formed on the entire surface.
An Al film is formed, and the Al film is patterned to form an Al film on the source layer 10, the gate electrode 6, and the drain layer 14, respectively.
The wiring 16 is formed and completed.

The present embodiment can be variously modified as follows, and the same effect can be obtained in any case.

That is, in this embodiment, As ions 4
Is implanted, but ions of P (phosphorus) or other impurities may be implanted instead. Further, the impurities may be those of Group III such as B. The impurity may be introduced by a method other than the ion implantation method, for example, a solid phase diffusion method or a gas phase diffusion method.

Further, in the present embodiment, the source layer 10 and the drain layer 14 are not silicided, but may be silicided.

In this embodiment, a polycrystalline silicon film is used as the gate electrode. However, a film made of another material such as a metal film and a metal silicide film may be used. Further, these stacked films may be used.

In this embodiment, an oxide film is used as the gate insulating film. However, a nitrided oxide film or a stacked film of an oxide film and a nitride film may be used.

In this embodiment, the substrate is SOI
Although a substrate is used, a normal bulk semiconductor substrate may be used. That is, a gate oxide film may be formed on the surface of a semiconductor substrate, and a gate electrode made of a polycrystalline silicon film or the like may be formed thereon.

In the present embodiment, the silicon nitride film 8 is removed after the formation of the groove, but the silicon nitride film need not be removed.

In this embodiment, only a single-electron transistor is shown. However, an active element (for example, a field-effect transistor, a bipolar transistor), a passive element (for example, a capacitor), or a substrate (semiconductor device) including both elements is used. The single-electron transistor of this embodiment may be formed in the portion.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating an element structure of a single-electron transistor according to the embodiment. 1 and 2 are denoted by the same reference numerals as those in FIGS. 1 and 2, and detailed description thereof is omitted (the same applies to other embodiments).

This embodiment differs from the first embodiment in that the tunnel barrier layer 11 and the tunnel barrier layer 13 are asymmetric with respect to, for example, the depth, the width, or both.

That is, the tunnel barrier layer 11 and the tunnel barrier layer 13 have different energy barriers (potentials) for electrons. As a result, a Coulomb staircase appears in the current-voltage characteristics, and the characteristics of the single-electron transistor can be fully utilized. Other effects similar to those of the first embodiment can be obtained, and various modifications can be made in the same manner.

Such an asymmetric tunnel barrier layer 11,
In order to form 13, an oblique ion implantation method is used. First, following the step shown in FIG. 1D, as shown in FIG. 4, the angle (incident angle) between the particle beam of the As ion 4 and the normal line of the polycrystalline silicon film 3 (substrate) is, for example, 30. As ions 4 are implanted so as to be at a right angle. Here, the acceleration voltage is, for example, 30 keV, and the dose is, for example, 1 × 10 ¹⁶ cm ^−2.
And Subsequent steps are the same as those in the first embodiment shown in FIG.
The steps are the same as those described below.

When As ions 4 are implanted obliquely as in this embodiment, one side of the gate electrode 6 (left side in the figure)
Becomes negative, and As ions 4 are not implanted. As a result, the As concentration differs between the left and right sides of the gate electrode 6, and FIG.
In the oxidation step (b), asymmetric grooves having different depths and the like are formed on the left and right sides of the gate electrode 6 due to the difference in oxidation speed, and the tunnel barrier layers 11 and 13 are asymmetric.

(Third Embodiment) FIG. 5 shows a third embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating the method for manufacturing the single-electron transistor according to the embodiment.

This embodiment is different from the second embodiment in that ions of the constituent material of the substrate, that is, Si ions 17 are obliquely implanted in order to form an asymmetric tunnel barrier layer. Specifically, for example, the Si ions 17 are incident at an angle of 30 °, an acceleration voltage of 30 keV, and a dose of 1
It is implanted into the polycrystalline silicon film 3 under the condition of × 10 ¹⁶ cm ⁻² . Subsequent steps are the same as the steps shown in FIG. 2A and thereafter of the first embodiment. When the Si ions 17 are obliquely implanted as in this embodiment, one side (the left side in the figure) of the gate electrode 6 becomes negative, and the Si ions 17 are not implanted. As a result, the crystallinity is not destroyed on the left side of the gate electrode 6, and asymmetric grooves having different depths are formed on the left and right sides of the gate electrode 6 due to the difference in oxidation rate in the oxidation step of FIG. The layers 11, 13 are asymmetric.

In this embodiment, the same effects as those of the first and second embodiments can be obtained, and various modifications can be made in the same manner as in the first embodiment.

(Fourth Embodiment) FIG. 6 shows a fourth embodiment of the present invention.
FIG. 7 is a process cross-sectional view illustrating the method for manufacturing the single-electron transistor according to the embodiment.

This embodiment is an example using a normal bulk silicon substrate instead of an SOI substrate.

First, as shown in FIG. 6A, a 50-nm-thick silicon oxide film 22 is formed on the surface of a p-type silicon substrate 21 by, for example, thermal oxidation at 900 ° C. Next, as shown in FIG.
200 nm thick silicon nitride film 23 by PCVD
To form

Next, as shown in FIG. 6B, the silicon nitride film 23, the silicon oxide film 22, the p-type silicon substrate 21
Are sequentially and selectively etched, and these are processed into an island shape.

Next, as shown in FIG. 6C, using the silicon nitride film 23 and the silicon oxide film 22 as masks, the exposed surface of the p-type silicon substrate 21 is oxidized to a thickness of 100 nm by thermal oxidation at 950 ° C., for example. After forming the film 24, the silicon nitride film 23 and the silicon oxide film 22 are removed. As a result, the p-type silicon substrate 21 is isolated by the oxide film 24. Next, as shown in FIG. 3C, for example, As ions 4 are implanted into the p-type silicon substrate 21 under the conditions of an acceleration voltage of 50 keV and a dose of 1 × 10 ¹⁵ cm ⁻² .

The subsequent steps are the same as the steps after the step of FIG. 1C of the first embodiment. In the present embodiment, the same effect as in the first embodiment can be obtained.

(Fifth Embodiment) FIG. 7 shows a fifth embodiment of the present invention.
FIG. 7 is a process cross-sectional view illustrating the method for manufacturing the single-electron transistor according to the embodiment.

First, following the step shown in FIG. 6C of the fourth embodiment, as shown in FIG. 7A, the surface of the p-type silicon substrate 21 is formed to a thickness of 20 nm by, for example, a thermal oxidation method.
An oxide film 25 serving as a gate oxide film of m is formed. Next, as shown in FIG. 2A, a polycrystalline silicon film 26 serving as a gate electrode having a thickness of 200 nm is formed on the entire surface by, eg, LPCVD.

Next, as shown in FIG. 7B, the polycrystalline silicon film 26 and the oxide film 25 are processed by, for example, anisotropic etching of RIE, and the gate electrode 26 and the gate oxide film 25 are processed.
To form Next, as shown in FIG. 3B, As ions 4 are implanted into the p-type silicon substrate 21 under the conditions of, for example, an incident angle of 30 °, an acceleration voltage of 30 keV, and a dose of 1 × 10 ¹⁶ cm ⁻² . Subsequent steps are the same as those in the first embodiment shown in FIG.
This is the same as the steps described below. In this embodiment, effects similar to those of the second embodiment can be obtained.

(Sixth Embodiment) FIG. 8 shows a sixth embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating the method for manufacturing the single-electron transistor according to the embodiment.

First, following the step shown in FIG. 7A of the fifth embodiment, as shown in FIG. 8, the polycrystalline silicon film 26 and the oxide film 25 are processed by, for example, RIE anisotropic etching. After the gate electrode 26 and the gate oxide film 25 are formed, the Si ions 17 are incident on the p-type silicon substrate 21 at an incident angle of 30 °, an acceleration voltage of 30 keV, and a dose of 1 ×
Inject under the condition of 10 ¹⁶ cm ^-2 . The subsequent steps are the first
This is the same as the steps shown in FIG.
In this embodiment, the same effects as in the third embodiment can be obtained.

(Seventh Embodiment) FIG. 9 shows a seventh embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating the method for manufacturing the single-electron transistor according to the embodiment.

This embodiment is different from the previous embodiments in that a groove is not formed by oxidation but formed by etching.

First, following the step shown in FIG. 2A of the first embodiment, as shown in FIG. 9, the gate side wall silicon oxide film is selectively removed using, for example, a hydrofluoric acid solution.
Using the gate electrode, the gate insulating film, and the silicon nitride mask film as a mask, the surface of the polycrystalline silicon film 3 exposed by removing the gate side wall silicon oxide film is etched with a mixed solution of choline, alkylphenylethoxylate, and imidazolium betaine. Then, the grooves are formed in a self-aligned manner.

As a result, the polycrystalline silicon film 3
Source layer 10, first tunnel barrier layer 11, island layer 12, second tunnel barrier layer 13, and drain layer 1
4 are formed. After that, the silicon nitride film 8 is removed using a solution such as hot phosphoric acid.

Finally, the single-electron transistor is completed through the interlayer insulating film, the contact hole, the wiring, etc. in the same manner as in the conventional single-electron transistor manufacturing method.

In this embodiment, the same effect as in the first embodiment in which the groove is formed by oxidation can be obtained.

(Eighth Embodiment) FIG. 10 is a process sectional view showing a method for manufacturing a single-electron transistor according to an eighth embodiment of the present invention.

First, following the step shown in FIG. 1D of the first embodiment, as shown in FIG. 10A, for example, As ions 4 are accelerated in the polycrystalline silicon film 3 at an incident angle of 30 ° and an acceleration of 30 °. The implantation is performed under the conditions of a voltage of 30 keV and a dose of 1 × 10 ¹⁶ cm ⁻² .

Next, as shown in FIG. 10B, a gate sidewall silicon oxide film 7 having a thickness of, for example, 10 nm, for example, a silicon nitride film 8 having a thickness of 1000 nm is deposited as in the first embodiment. It is formed by etching back.

Next, as shown in FIG. 10C, the gate side wall silicon oxide film 7 is removed and the exposed surface is etched to form a groove as in the ninth embodiment. At this time, since the As ions 4 are implanted obliquely, the As concentration differs between the left and right sides of the gate electrode 6, and asymmetric grooves having different depths and the like are formed on the left and right sides of the gate electrode 6. 11 and 13 are formed.

After that, the single electron transistor is completed through the interlayer insulating film, the contact hole, the wiring, etc. in the same manner as in the conventional single electron transistor manufacturing method. In this embodiment, effects similar to those of the second embodiment can be obtained.

(Ninth Embodiment) FIG. 11 is a sectional view showing a method for manufacturing a single-electron transistor according to a ninth embodiment of the present invention.

First, following the step shown in FIG. 1D of the first embodiment, as shown in FIG. 11, for example, Si ions 17 are applied to the polycrystalline silicon film 3 at an incident angle of 30 °, an acceleration voltage of 30 keV, and The implantation is performed under the condition of a dose amount of 1 × 10 ¹⁶ cm ⁻² . The subsequent steps are the same as those in the eighth embodiment shown in FIG.
This is the same as the subsequent steps.

When the Si ions 17 are obliquely implanted as in this embodiment, one side (the left side in the figure) of the gate electrode 6 becomes negative, and the Si ions 17 are not implanted.
As a result, the crystallinity is not destroyed on the left side of the gate electrode 6, and asymmetric grooves having different depths and the like are formed on the left and right sides of the gate electrode 6 due to the difference in the etching rate in the etching step of FIG. Tunnel barrier layer 11,
13 are formed. In this embodiment, the same effects as in the third embodiment can be obtained.

(Tenth Embodiment) FIG. 12 is a process sectional view showing a method for manufacturing a single-electron transistor according to a tenth embodiment of the present invention.

The present embodiment is different from the previous embodiments in that a silicon oxide mask film is used as a gate side wall silicon nitride film and a silicon nitride mask film instead of the gate side silicon oxide film.

First, following the step shown in FIG. 1D of the first embodiment, a gate sidewall silicon nitride film 18 is formed on the sidewall of the gate electrode 6 as shown in FIG. The method of forming the gate sidewall silicon nitride film 18 is the same as that of the gate sidewall silicon oxide film 17.

Next, as shown in FIG. 9A, a silicon oxide film having a thickness of 1000 nm to be a silicon oxide mask film 19 is formed on the entire surface by, for example, the LPCVD method, and the silicon oxide film 19 is etched back. A silicon oxide mask film 19 is formed on the surface of the polysilicon film 4 not covered with the gate sidewall silicon nitride film 18 or the gate oxide film 5.
To form

Next, as shown in FIG. 12B, the gate side wall silicon nitride film 18 is removed by using, for example, a hot phosphoric acid solution, and the exposed surface is made of, for example, a mixed solution of choline, alkylphenylethoxylate, and imidazolium betaine. After the trench is formed in a self-aligned manner, the silicon oxide film 19 is removed using, for example, a hydrofluoric acid solution.

Thereafter, the single-electron transistor is completed through the interlayer insulating film, the contact hole, the wiring, etc. in the same manner as in the conventional method for manufacturing the single-electron transistor. In the present embodiment, the same effects as in the first embodiment can be obtained.

(Eleventh Embodiment) FIG. 13 is a process sectional view showing a method for manufacturing a single-electron transistor according to an eleventh embodiment of the present invention.

First, following the step shown in FIG. 1D of the first embodiment, as shown in FIG. 13A, for example, As ions 4 are accelerated into the polycrystalline silicon film 3 at an incident angle of 30 ° and an acceleration of 30 °. The implantation is performed under the conditions of a voltage of 30 keV and a dose of 1 × 10 ¹⁶ cm ⁻² .

Next, as shown in FIG. 13B, a gate sidewall silicon nitride film 18 having a thickness of, for example, 10 nm is formed on the sidewall of the gate electrode 15. Next, as shown in FIG. 2B, a 1000-nm-thick silicon oxide film serving as a silicon oxide mask film 19 is formed on the entire surface by, for example, the LPCVD method, and the silicon oxide film is etched back to form a gate sidewall silicon nitride. The silicon oxide film 19 is left on the surface not covered with the film 18 or the gate oxide film 5. Subsequent steps are the same as the steps shown in FIG. 12B of the tenth embodiment.

When As ions 4 are implanted obliquely as in this embodiment, one side of the gate electrode 6 (left side in the figure)
Becomes negative, and As ions 4 are not implanted. As a result, the As concentration differs between the left and right sides of the gate electrode 6, and FIG.
In the etching step (b), asymmetric grooves having different depths and the like are formed on the left and right sides of the gate electrode 6 due to the difference in the etching rate, and the tunnel barrier layers 11 and 13 are asymmetric. In this embodiment, effects similar to those of the second embodiment can be obtained.

(Twelfth Embodiment) FIG. 14 is a sectional view showing a method for manufacturing a single-electron transistor according to a twelfth embodiment of the present invention.

First, following the step shown in FIG. 1D of the first embodiment, as shown in FIG. 14, for example, Si ions 17 are applied to the polycrystalline silicon film 3 at an incident angle of 30 °, an acceleration voltage of 30 keV, and The implantation is performed under the condition of a dose amount of 1 × 10 ¹⁶ cm ⁻² . Subsequent steps are the same as those in FIG.
This is the same as the step shown in FIG.

When the Si ions 17 are obliquely implanted as in this embodiment, one side (the left side in the figure) of the gate electrode 6 becomes negative, and the Si ions 17 are not implanted.
As a result, the crystallinity is not destroyed on the left side of the gate electrode 6, and in the oxidation step after the removal of the gate sidewall silicon nitride film 18, asymmetrical grooves having different depths and the like on the left and right sides of the gate electrode 6 due to a difference in etching rate. Is formed, and asymmetric tunnel barrier layers 11 and 13 are formed. In this embodiment, the same effects as in the third embodiment can be obtained.

(Thirteenth Embodiment) FIG. 15 is a sectional view showing a method for manufacturing a single-electron transistor according to a thirteenth embodiment of the present invention.

The present embodiment differs from the tenth embodiment in that the silicon oxide mask film 19 is formed not by deposition but by oxidation.

First, following the step shown in FIG. 1D of the first embodiment, as shown in FIG.
For example, a gate sidewall silicon nitride film 18 having a thickness of 20 nm is formed on the side wall of the gate electrode 5. Next, as shown in the figure, a silicon oxide film 19 is formed on the surface of the polycrystalline silicon film 3 not covered with the gate side wall silicon nitride film 18 by thermal oxidation. Subsequent steps are the same as in FIG. 12B of the tenth embodiment.
It is the same as the steps after. In the present embodiment, the same effect as in the first embodiment can be obtained.

Note that nitriding may be performed instead of oxidation. In this case, a gate side wall silicon oxide film is used as in the tenth embodiment.

(Fourteenth Embodiment) FIG. 16 is a sectional view showing a method for manufacturing a single-electron transistor according to a fourteenth embodiment of the present invention.

The present embodiment differs from the thirteenth embodiment in that As is introduced by oblique ion implantation.

First, following the step shown in FIG. 1D of the first embodiment, as shown in FIG. 16, for example, As ions 4 are incident on the polycrystalline silicon film 3 at an incident angle of 30 °, an acceleration voltage of 30 keV, and The implantation is performed under the condition of a dose amount of 1 × 10 ¹⁶ cm ⁻² . Subsequent steps are the same as the steps shown in FIG. 15 of the thirteenth embodiment and the subsequent steps. In this embodiment, effects similar to those of the second embodiment can be obtained.

(Fifteenth Embodiment) FIG. 17 is a sectional view showing a method for manufacturing a single-electron transistor according to a fifteenth embodiment of the present invention.

The present embodiment is different from the thirteenth embodiment in that Si is introduced by oblique ion implantation.

First, following the step shown in FIG. 1D of the first embodiment, as shown in FIG. 17, for example, Si ions 17 are incident on the polycrystalline silicon film 3 at an incident angle of 30 °, an acceleration voltage of 30 keV, and The implantation is performed under the condition of a dose amount of 1 × 10 ¹⁶ cm ⁻² . Subsequent steps are the same as the steps shown in FIG. 15 of the thirteenth embodiment and the subsequent steps. In this embodiment, the same effects as in the third embodiment can be obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the case where the carrier is an electron has been described. However, if the impurity to be added is a p-type impurity, an element in which the carrier is a hole can be realized.

The thickness of each layer (film) and the thickness of each layer (film)
Is not limited to the method described in the above embodiment.

Further, in the above embodiment, all the combinations of the steps are not described, but those which are not described are also possible. In other words, As ion implantation, oblique ion implantation, Si ion implantation,
Select one of oblique ion implantation, select a method using oxidation or a method using etching as a method of forming a groove, and use a combination of a gate side wall silicon oxide film and a silicon nitride mask film as a combination of a gate side wall side insulating film and a mask insulating film. Alternatively, the gate side wall silicon nitride film / silicon oxide mask film is selected, an SOI substrate or a bulk substrate is selected as a substrate, and a deposition method or an oxidation method is selected as a method of forming a mask insulating film. Although only typical ones are described, other methods not described are also possible. In addition, various modifications can be made without departing from the scope of the present invention.

[0122]

As described above in detail, according to the present invention, since a groove defining a tunnel barrier layer can be formed in a self-aligning manner, a fine tunnel barrier layer not limited by the exposure limit of photolithography is provided. In addition, a single-electron transistor having a fine gate electrode which is not limited by alignment accuracy of lithography can be realized.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a first-half method for manufacturing a single-electron transistor according to a first embodiment of the present invention;

FIG. 2 is a process sectional view showing the latter half of the method for manufacturing the single-electron transistor according to the first embodiment of the present invention;

FIG. 3 is a sectional view showing an element structure of a single-electron transistor according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing the method of manufacturing the single-electron transistor of FIG. 3;

FIG. 5 is a sectional view showing a method for manufacturing a single-electron transistor according to a third embodiment of the present invention.

FIG. 6 is a process sectional view showing the method for manufacturing the single-electron transistor according to the fourth embodiment of the present invention.

FIG. 7 is a process cross-sectional view showing a method for manufacturing a single-electron transistor according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view showing a method for manufacturing a single-electron transistor according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view showing the method of manufacturing the single-electron transistor according to the seventh embodiment of the present invention.

FIG. 10 is a process sectional view showing the method for manufacturing the single-electron transistor according to the eighth embodiment of the present invention.

FIG. 11 is a sectional view showing a method for manufacturing a single-electron transistor according to a ninth embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method for manufacturing the single-electron transistor according to the tenth embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the single-electron transistor according to the eleventh embodiment of the present invention.

FIG. 14 is a sectional view showing a method for manufacturing a single-electron transistor according to a twelfth embodiment of the present invention.

FIG. 15 is a sectional view showing the method of manufacturing the single-electron transistor according to the thirteenth embodiment of the present invention.

FIG. 16 is a sectional view showing the method of manufacturing the single-electron transistor according to the fourteenth embodiment of the present invention.

FIG. 17 is a sectional view showing the method of manufacturing the single-electron transistor according to the fifteenth embodiment of the present invention.

FIG. 18 is a process cross-sectional view showing the first half of a conventional method for manufacturing a single-electron transistor;

FIG. 19 is a process cross-sectional view showing the first half of a method for manufacturing a conventional single-electron transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... p-type silicon substrate 2 ... silicon oxide film 3 ... polycrystalline silicon film 4 ... As ion 5 ... gate oxide film 6 ... gate electrode 7 ... gate side wall silicon oxide film 8 ... silicon nitride mask film 9 ... oxide film 10 ... source Layer 11: first tunnel barrier layer 12: island layer 13: second tunnel barrier layer 14: drain layer 15: interlayer insulating film 16: Al wiring 17: Si ion 18: gate sidewall silicon nitride film 19: silicon oxide mask Film 21: p-type silicon substrate 22: silicon oxide film 23: silicon nitride film 24: oxide film 25: gate oxide film 26: gate electrode

Claims (3)

(57) [Claims] 1. An island layer, a source layer connected to the island layer via a first thinner tunnel barrier layer, a source layer connected to the island layer via a second thinner tunnel barrier layer, And a drain layer disposed so as to sandwich the island layer together with the source layer; and a drain layer disposed on the island layer via a gate insulating film;
And a gate electrode which does not overlap the source layer and the drain layer. A step of forming a gate electrode on a partial region of the semiconductor layer via a gate insulating film; a step of forming a gate side wall insulating film on a side wall of the gate electrode and the gate insulating film; the surface of the semiconductor layer not covered with the gate sidewall insulating film and the gate insulating film, a step of material than the gate side wall insulating film to form a different mask insulating film, selectively removing the gate sidewall insulating film Then, by using the mask insulating film, the gate insulating film and the gate electrode as a mask, removing the gate side wall insulating film and oxidizing the exposed surface of the semiconductor layer to form a groove, the semiconductor layer An island layer, a first tunnel barrier layer thinner than the island layer, a source layer connected to the island layer via the first tunnel barrier layer,
A second tunnel barrier layer thinner than the island layer;
A step of connecting to the island layer via the second tunnel barrier layer and separating the source layer into a drain layer sandwiching the island layer together with the source layer. A step of forming a gate electrode on a partial region of the semiconductor layer via a gate insulating film; a step of forming a gate sidewall insulating film on a side wall of the gate electrode and the gate insulating film; the surface of the semiconductor layer not covered with the gate sidewall insulating film and the gate insulating film, a step of material than the gate side wall insulating film to form a different mask insulating film, selectively removing the gate sidewall insulating film Then, using the mask insulating film, the gate insulating film and the gate electrode as a mask, the surface of the semiconductor layer exposed by removing the gate sidewall insulating film is etched to form a groove, thereby forming the semiconductor layer. An island layer, a first tunnel barrier layer thinner than the island layer, and a source layer connected to the island layer via the first tunnel barrier layer. ,
A second tunnel barrier layer thinner than the island layer;
A step of connecting to the island layer via the second tunnel barrier layer and separating the source layer into a drain layer sandwiching the island layer together with the source layer.