JP2622588B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a field-effect transistor that operates at high speed, and relates to a method for manufacturing a transistor that operates at high speed and consumes less power by a simpler method.
And forming a second semiconductor layer on the first semiconductor substrate that is less oxidized than the first semiconductor substrate, forming an insulating film on the second semiconductor layer, Patterning the insulating film and the second semiconductor layer by etching to form a projection including at least the second semiconductor layer and the insulating film on the first semiconductor substrate; Forming a field oxide film by oxidizing the surface, forming a thin oxide film on the side wall of the second semiconductor layer, forming a conductive film by covering the entire surface with a conductive material, and selectively forming the conductive film. Patterning to form an electrode in contact with the insulating film remaining on the side wall of the second semiconductor layer.

[Industrial applications]

The present invention relates to a method of manufacturing a transistor that operates at high speed, and more particularly to a method of manufacturing a field effect transistor (FET) in which a gate region is formed on a side wall of SiC grown on a silicon substrate.

With the recent demand for faster computers, development of transistors that operate at ultra-high speeds has been desired. In addition, these transistors are required to have low power consumption.

[Conventional technology]

Conventionally, in the planar type bipolar transistor shown in FIG. 5, n ⁺ , n, p and n ⁺ regions are formed from below in a silicon substrate 1, and the lower n ⁺ region is a collector region provided with a collector electrode C. The p region is the base region and the base electrode B
Is provided, and the upper n ⁺ region is an emitter region in which an emitter electrode E is provided. In the figure, the inside of the broken line is an operation area, and the outside of the broken line is an area unnecessary for operation. As described above, in the planar type bipolar transistor, it is necessary to separately form the base electrode window on the insulating film on the substrate, for example, SiO ₂ other than the emitter electrode window, and the area of the region unnecessary for operation is about 10 times as large as the operation region. As they became closer, the parasitic capacitance and parasitic resistance were larger.

FIG. 6 shows a conventional example that solves these problems and achieves high-speed operation. By forming a Polysi base extraction structure on the side surface of the p layer of the base, a base region unnecessary for operation is eliminated, the parasitic capacitance is reduced, and high-speed operation becomes possible. The base region of the p-type region is formed by self-alignment using the same mask (resist) as the emitter region of the n ⁺ region above. Transistors with the structure obtained by such technology are SICOS (Sidewall base Contact
Structure).

Hereinafter, a method of manufacturing the SICOS transistor of FIG. 6 will be described with reference to FIGS. 7A to 7E.

First, after forming an n ⁺ buried layer in a silicon substrate,
An O ₂ film, a Si ₃ N ₄ film, and a SiO ₂ film are successively formed, and a portion serving as an inactive region is etched (FIG. 7A).

After thermally oxidizing the entire surface and depositing a Si ₃ N ₄ film, the flat portion of the Si ₃ N ₄ film is removed by RIE (FIG. 7B).

Next, selective oxidation is performed using the Si ₃ N ₄ film as a mask to form a thick oxide film. After removing the side Si ₃ N ₄ film and SiO ₂ film,
Non-doped polycrystalline Si (PolySi) is deposited. Then 2
Fill the grooves with different types of photoresist (PR) (Fig. 7C).

The polycrystalline Si in the convex portion is planarized by RIE with the same etching rate (FIG. 7D).

Next, the oxide film and the Si ₃ N ₄ film on the surface are removed, and a P-type impurity is introduced into the polysilicon portion and an N-type impurity is introduced into the collector lead portion by ion implantation. Windows are opened to grow an inner base formed after the whole surface CVD SiO _2, the N-type diffusion layer is formed on the SiO ₂ portion is performed to form the base / emitter / collector by a metal deposition (No. 7E view).

As described above, the conventional method of manufacturing a SICOS transistor is very complicated and requires a long process.

The present inventor has previously invented a method for easily manufacturing this SICOS-type transistor-like structure.Bipolar transistors have excellent performance in terms of high-speed operation, but have the disadvantage of high power consumption. . Therefore,
We have been studying applications to FETs that have the advantage of low power consumption. Generally, FETs are characterized by a lower operating speed but lower power consumption than bipolar transistors. Furthermore, if a vertical FET in which this FET is formed in a vertical type can be formed, it is considered that a transistor that consumes low power and operates at high speed can be formed.

[Problems to be solved by the invention]

As described above, the conventional ultra-high-speed SICOS type transistor has a problem that the manufacturing process is complicated and the number of steps is long. Further, no matter how small the device is, there is a disadvantage that power consumption is large because the transistor is a bipolar transistor.

Accordingly, the present invention provides an improved method of manufacturing a conventional SICOS transistor, a method of manufacturing a semiconductor device which can be obtained in a simpler and shorter process, and provides a method of manufacturing a SICOS transistor.
It is an object of the present invention to provide a method for forming a transistor with high speed operation and low power consumption by applying the basic structure of a type transistor to a field effect transistor.

[Means for solving the problem]

The principle configuration of the present invention is shown in FIGS. 1A to 1E which will be described later in detail. The present invention will be described with reference to the drawing. (A) A second semiconductor layer, for example, a SiC film (2), which is less oxidized than the first semiconductor substrate, is formed on a first semiconductor, for example, a silicon substrate (1). Process, (b)
Forming an insulating film (3) on the second semiconductor layer;
(C) a step of patterning the insulating film (3) and the second semiconductor layer (2) by etching to form a projection including at least the second semiconductor layer and the insulating film on the first semiconductor substrate; (D) oxidizing the exposed surface of the first semiconductor substrate to form a field oxide film (4); (e) forming an insulating film (5) made of a thin oxide film on the side wall of the second semiconductor layer. Forming a conductive film by covering the entire surface with a conductive material, selectively patterning the conductive film, and contacting the insulating film (5) remaining on the side wall of the second semiconductor layer. And (b) forming a semiconductor device.

[Action]

According to the present invention, a first semiconductor substrate made of silicon or the like (1)
A gate region can be formed on the side wall of the second semiconductor layer (2) made of, for example, SiC, which is hardly oxidized, so that the manufacturing process of the vertical transistor can be simplified. Further, a transistor structure capable of self-alignment is formed.

In particular, the operation of the semiconductor device formed by the present invention is enumerated below.

In order to operate the FET at high speed, it is necessary to eliminate the parasitic capacitance of the transistor. Since the gate portion of the FET transistor has the shape of the capacitor itself, a capacitance is parasitic in this portion. To speed up the transistor, it is necessary to reduce the capacitance in this portion. The capacity can be reduced by reducing the area of the gate portion. In this regard, when the vertical transistor of the present invention is formed,
Since the gate length is determined by the thickness of SiC and does not use a lithography technique, a finer gate length than the current lithography technique can be achieved. For example, the thickness of SiC
It is easy to set the thickness to 0.1 μm, and the gate length can be finely processed, so that the gate area can be reduced and the gate capacitance can be extremely reduced, so that a high-speed transistor can be formed.

In order to operate the FET transistor at high speed, it is necessary to shorten the gate length and shorten the transit time of electrons or holes between the source and the drain. However, as described above, the gate length can be shortened. However, speeding up is possible.

As described above, it is possible to relatively easily achieve a gate length of 0.1 μm or less, so that the electrons in SiC can have a gate length that is equal to or less than the mean free path. In such a case, the electrons running between the source and the drain reach the drain from the source with almost no collision while in a solid state, that is, a ballistic effect can be expected. The speed of the electrons running ballistically is much higher than the drift speed of the ball while running countless times in a solid, so that a transistor can be formed at a higher speed than ever before.

A bipolar transistor requires a current to flow between the base and the emitter as the transistor is turned on and off. This consumes power. On the other hand, according to the present invention, in order to form an FET and turn on / off the transistor, only the change in the voltage applied to the gate is sufficient, and no current flows. Therefore, a low power consumption transistor which does not consume power as compared with a bipolar transistor is obtained.

In addition, SIC has physical properties such as a large band gap, a high electron saturation velocity, and a large breakdown electric field.By forming a transistor using this, it can operate at high voltage, operate at high temperature, An advantage is also obtained that an environment-resistant element such as a wire that operates even in a bad environment can be formed.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

The method of the first embodiment is shown in process sectional views of FIGS. 1 (A) to 1 (E).

First, as shown in FIG. 1 (A), on a silicon substrate 1
An N ⁺ layer is formed, and about 200
Deposit N ^- type silicon carbide (SiC) to a thickness of 0Å
The film 2 was formed, and SiO ₂ was further deposited thereon to a thickness of about 4000 ° by the CVD method to form the insulating film 3. Where
Various conditions in forming the SiC film 2 are as follows.

Si source gas: trichlorosilane (SiHCl ₃ ) C source gas: propane (C ₃ H ₈ ) Dopant gas: N-type impurity gas PH ₃ Carrier gas: hydrogen (H ₂ ) Reaction chamber pressure: (200 pa) Growth Temperature: (1000 ° C.) Growth temperature (40 minutes) Film thickness: (approximately 2000 °) Here, a specific example of the growth process of the N-type SiC film is as follows.

(A) Induction heating of the reaction chamber to start heating (b) 10 minutes after starting the heating of the reaction chamber, SiHCl, C ₃ H _8, N-type dopant and H ₂ are introduced (c) At 1000 ° C. (D) Stop the high-frequency oscillator and start cooling down the reaction chamber. (E) Rapidly cool to room temperature in 10 minutes. Next, as shown in FIG. 1 (B), the insulating film 3 and the SiC film 2
Then, the silicon substrate 1 (5000 °) is selectively subjected to RIE (reactive ion etching) to form a convex portion including the insulating film 3 and the SiC film 2 on the silicon substrate 1. The etching of the silicon substrate in this RIE process is performed in order to prevent the deposition of the silicon substrate from increasing in the next oxidation process (field oxide film forming process) and covering the side wall of the SiC film with the oxide film. is there.

Next, as shown in FIG. 1C, the entire surface is thermally oxidized to form a field oxide film 4 of 6000.degree. During this oxidation process,
The side wall of the C film 2 is also oxidized to a thickness of about 600 ° (about 1/100 of SiO ₂ ).
The (oxidized) SiC sidewall oxide film 5 is formed to a thickness of 10.

Next, as shown in FIG. 1 (D), a substantially central portion of the insulating film 3 is removed by etching to open a window 6 of the source (S). At this time, although not shown, a window for the drain (D) is opened at the same time.

Next, in FIG. 1 (E), as shown in FIG. 1, metal Al is vapor-deposited on the entire surface and patterned to form a source electrode (S),
Forming a gate electrode (G) and a drain electrode (D);
A vertical FET is formed. Although not shown, it is preferable to form a contact region by performing As ⁺ or P ⁺ ion implantation and annealing after opening the window of the source.

In this vertical FET transistor, the electron traveling distance is determined by the thickness of SiC, and a gate current of 0.1 μm or less can be relatively easily achieved. For this reason, it is possible to make the gate length less than the mean free path of the electrons in SiC, and in that case, the electrons running between the source and the drain reach the drain from the source almost without collision. In other words, it is possible to form an ultra-high-speed transistor that operates ballistically, and since the speed of electrons running on the ballistic is extremely faster than the drift speed of running while repeating collisions in a solid, it is possible to form an unprecedented high-speed transistor. Become. Further, since the window area of the gate electrode can be made extremely small by using the side wall of SiC, the parasitic capacitance can be eliminated and reduced, and further higher speed can be expected.

2 (A) to 2 (G) are process sectional views for explaining a second embodiment of the present invention.

First, as shown in FIG.
Silicon carbide (SiC) is deposited to a thickness of about 2000 mm by the CVD method to form a SiC film 12, and then about 30% by the CVD method.
Polycrystalline silicon (PolySi) deposited to a thickness of 00mm
A Si film 13 is formed, and about 1500 is formed on the PolySi film 13 by a CVD method.
Silicon nitride (Si ₃ N ₄ ) is deposited to a thickness of Å to form a Si ₃ N ₄ film 14
Was formed. Here, the conditions for forming the SiC film 12 are the same as those for the SiC film 2 of the previous embodiment.

Next, as shown in FIG. 2 (B), the Si ₃ N ₄ film 14, PolySi
The film 13, the SiC film 12, and the silicon substrate 11 (3000 mm) are selectively RIE, and a convex portion including three layers of the Si ₃ N ₄ film 14, the PolySi film 13, and the SiC film 12 is formed on the silicon substrate 11. . In this RIE step, the etching of the silicon substrate is performed in order to prevent the deposition of the silicon substrate from increasing in the next step (field oxide film forming step) and to cover the side wall of the SiC film with the oxide film.

Next, as shown in FIG. 2 (C), the entire surface of the silicon substrate 11 is thermally oxidized at 900 ° C. to form a field oxide film 15 of about 6000 °.
Form. In this oxidation step, the side wall of the SiC film 12 is oxidized to a thickness of about 600 mm (an oxidized SiC side wall oxide film 16 is formed to a thickness of about 1/10 of SiO ₂ , and simultaneously the PolySi side wall is oxidized, too). 17 is formed.

Next, as shown in FIG. 2 (D), doped PolySi is deposited again to a thickness of about 7000 mm on the entire surface by the CVD method.
PolySi sidewall film 18 on sidewall by anisotropic etching with E
To form

Next, as shown in FIG. 2 (E), the entire surface is oxidized (about 900 ° C.).
The surface of the PolySi sidewall film 18 by thermal oxidation
An SiO ₂ film 19 is formed to a thickness of 3000 mm. Next, a drain electrode and a gate electrode are opened by resist patterning. FIG. 3 is referred to for the plan configuration at this time. After opening the windows for the drain electrode and the gate electrode, the CVDSi ₃ N ₄ film 14 is removed with boiling phosphoric acid to form a source window.

Next, as shown in FIG. 2 (F), a conductive film made of Al is formed on the entire surface by a normal vapor deposition method, and is patterned to form a gate electrode (G), a source electrode (S), and a drain electrode (D). It was formed by self-alignment (self-alignment). In addition, phosphorus (P) is introduced into PolySi13 and SiC12 by ion implantation.
Alternatively, (As) is ion-implanted to form a contact layer.

In this way, the vertical FET [or S
IT (Static Indaction Transistor) type transistor]
Is formed.

The plan view of the semiconductor device thus formed is shown in FIG.
FIG. 2G is a sectional view taken along the line AA ′ of FIG.
Is equivalent to

Next, a third embodiment will be described with reference to FIGS. 4 (A) to 4 (G).

The difference from the second embodiment is that PolySi is not formed on the SiC film.

First, as shown in FIG. 4A, an SiC film 12 is formed by depositing SiC to a thickness of about 2000 mm on a silicon substrate 11 on which an N ⁺ layer is formed by a CVD method, and a SiC film 12 is formed thereon by a CVD method. The Si ₃ N ₄ film 14 was formed to a thickness of about 5000 mm.

Incidentally, this Si ₃ N ₄ film is preferably a method for stably forming the side wall PolySi described below or for oxidizing the SiC surface as much as possible, but it is possible to leave the side wall PolySi with only SiC. Since Si is hardly oxidized to about 1/10 of Si, SiC itself can be substituted and omitted.

Hereinafter, in the same manner as in the second embodiment, the Si ₃ N ₄ film 14 and the SiC film 12
Is formed (FIG. 4 (B)). Then, as shown in FIG. 4 (D), PolySi is deposited to a thickness of about 7000 mm, and then anisotropically etched by RIE to form PolySi. Side wall film 1
After the formation of 8, the Si ₃ N ₄ film 14 is removed by boiling with phosphoric acid (FIG. 4E). After that, the PolySi sidewall film 18 is thermally oxidized.
Is oxidized to form an SiO ₂ film 19 (FIG. 4 (F)). Next, the thin oxide film (approximately 1/10 on PolySi) formed on the SiC film is removed by control etching. Next, after applying a resist, patterning is performed to etch SiO ₂ , and windows for the gate electrode and the drain electrode are opened.

Finally, as shown in FIG. 4 (G), Al was deposited and patterned to form a gate electrode (G), a source electrode (S), and a drain electrode (D) made of Al by self-alignment.

〔The invention's effect〕

As described above, according to the present invention, a field effect transistor applying a SICOS-like structure, that is, a gate can be formed on the side wall portion by a very simple and short process, and the gate width is equal to that of the SiC epitaxial layer. Since the thickness is determined by the thickness, an extremely fine gate region can be formed. As a result, the capacitance parasitic to the gate can be reduced, and high speed can be expected.

Further, according to the present invention, it is possible to form all the main parts (source, gate, drain) of the transistor in a self-aligned manner by using one mask. Furthermore, a ballistic device (tunnel control device) can be formed by making the thickness of SiC less than the electron meanfreepass in the formation of a MOS type device. Therefore, there is an effect that the short channel effect can be prevented.

[Brief description of the drawings]

FIGS. 1 (A) to 1 (E) are process sectional views of a first embodiment of the present invention, FIGS. 2 (A) to 2 (G) are process sectional views of a second embodiment of the present invention, and FIGS. The drawings are plan views of the second embodiment of the present invention, FIGS. 4 (A) to 4 (G) are cross-sectional views of the process of the third embodiment of the present invention, and FIG. 5 is a cross-section of the first conventional example. FIG. 6, FIG. 6 is a sectional view of a second conventional example, and FIGS. 7A to 7E are process sectional views of the second conventional example. 1 is a silicon substrate 2 is a SiC film 3 is an insulating film (SiO ₂ ) 4 is a field oxide film 5 is a side wall oxide film 6 (for forming a source electrode) window 11 is a silicon substrate 12 is a SiC film 13 is PolySi 14 is Si ₃ N ₄ Film 15 is field oxide film 16 is SiC side wall oxide film 17 is PolySi side wall oxide film 18 is PolySi side wall film 19 is SiO ₂ film

Claims (1)

(57) [Claims] 1. The following (A) to (F): (A) a step of forming a second semiconductor layer which is less susceptible to oxidation than the first semiconductor substrate on the first semiconductor substrate; (C) patterning the insulating film and the second semiconductor layer by etching to form a projection including at least the second semiconductor layer and the insulating film on the first semiconductor substrate. (D) oxidizing the exposed surface on the first semiconductor substrate to form a field oxide film; (e) forming a thin oxide film on the side wall of the second semiconductor layer; Forming a conductive film by covering the conductive material, and selectively patterning the conductive film to form an electrode in contact with an insulating film remaining on a side wall of the second semiconductor layer. A method for manufacturing a semiconductor device.