JP2962282B2 - Elastic store memory fault detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an elastic
The present invention relates to a failure detection device for a store memory, and more particularly, to a failure detection device for an elastic store memory that detects a failure in a memory based on information held in a register when data is written to the memory.

[0002]

2. Description of the Related Art As a prior art, Japanese Patent Application Laid-Open No. 6-27431 is disclosed.
Publication No. 3 discloses an elastic store, described below.
A memory fault detection circuit is disclosed.

When writing received serial data to a memory, the serial data is written in units of 8 bits or 2 bits.
Is converted into parallel data in units of n bits (n is a natural number), a parity is generated for each converted parallel data unit, and this parity bit is stored in a register. The serial data read from the memory is converted into parallel data in units of 8 bits or 2 n bits, and parity is generated for each parallel data unit, as in the case of writing. Then, a failure in the elastic store memory is detected by comparing the parity generated at the time of reading with the corresponding parity information held in the register.

[0004]

In the above-described conventional fault detecting circuit for an elastic store memory, a parity bit is held for each parallel data unit converted in parallel into 8-bit units or 2 n -bit units. Register is required. For this reason, when the capacity of the memory for storing the input data increases, the number of parity bits also increases. Therefore, the capacity of the register for holding the parity bits must be increased, and the required circuit scale is increased. There is a problem that becomes large. In order to reduce the required register capacity, it is conceivable to increase the number of bits of the parallel-converted parallel data. In this case, however, the circuit scale of the serial / parallel converter and the parallel / serial converter is increased. There is a problem that needs to be done.

According to the present invention, when data is written to a memory, the data is temporarily stored in a register, and data corresponding to the data stored in the register is sequentially read from the memory and compared with the data stored in the register. It is an object of the present invention to provide an elastic store memory failure detection device capable of reducing the circuit scale by detecting the failure of the elastic store memory.

[0006]

In order to achieve the above object, the present invention is directed to an elastic store memory which writes serial data to a memory at a predetermined cycle and reads out the memory with a required phase from the memory. In the failure detection device, when data is written to the memory, a holding unit that temporarily holds data to be written to the memory in a register, and a read cycle that reads and outputs the data written to the memory every required cycle. And a comparing unit for reading data corresponding to the data held in the register from the memory and comparing the read data with the data held in the register, and detecting a failure in the memory based on a comparison result of the comparing unit. There is a configuration to do.

[0007] The elastic store memory writes serial data to the memory at a predetermined cycle and reads out the memory with a required phase to generate serial output data. The holding unit temporarily holds the data to be written to the memory in the register when writing the data to the memory. The comparing means reads data corresponding to the data held in the register from the memory and compares the data with the data held in the register during a read cycle in which the data written in the memory is read and output every required cycle. I do. When a failure occurs in the memory, the comparison means causes a mismatch between the data held in the register and the data read from the memory.

According to this configuration, the data to be written to the memory is temporarily stored in the register, and the data is sequentially read out and compared, so that it is possible to share the register for serial data. Therefore, regardless of the capacity of the memory, a failure of the memory can be detected with a small-capacity register, and the circuit scale can be reduced.

According to a second aspect of the present invention, there is provided a fault detecting device for an elastic store memory which writes serial data to a memory at a predetermined period and reads out the memory from the memory with a required phase. Holding means for temporarily holding write data and a write address to the memory in a register;
Reading means for reading data written to an address corresponding to a write address held in the register from the memory during a read cycle of reading and writing data written to the memory at every required cycle; And comparing means for comparing the data read by the reading means with the data held in the register, and detecting a fault in the memory based on a comparison result of the comparing means.

The elastic store memory writes serial data to the memory at a predetermined period and reads out the memory from the memory at a required phase to generate serial output data. When writing data to memory,
The holding unit temporarily holds the write data and the write address to the memory in the register. The readout unit reads out, from the memory, data written at an address corresponding to the write address held in the register during a read cycle in which data written to the memory is read and output at required cycles. The comparing means compares the data read by the reading means with the data held in the register. When a failure occurs in the memory, the comparison means causes a mismatch between the data held in the register and the data read from the memory.

According to this configuration, since the data to be written to the memory is temporarily stored in the register and sequentially read out and compared, the register can be shared for serial data. Therefore, regardless of the capacity of the memory, a failure of the memory can be detected with a small-capacity register, and the circuit scale can be reduced.

According to a third aspect of the present invention, in the fault detecting apparatus for an elastic store memory, serial data is written to a memory in synchronization with a write clock and read from the memory at a required phase in synchronization with the clock. When serial data is converted from serial data to parallel data and written to the memory, a holding unit for temporarily holding data to be written to the memory and a write address in a register; / Comparing means for reading data corresponding to the write address held in the register from the memory during a read cycle for serial / conversion output, and comparing the read data with the data held in the register. Of the memory is detected based on the comparison result of There as formed.

The elastic store memory writes serial data to the memory in synchronization with a write clock and reads out the memory at a required phase in synchronization with the clock to generate serial output data. The holding unit temporarily holds data to be written to the memory and a write address in the register when serial data is converted from serial data to parallel data and written to the memory. The comparing means reads data corresponding to the write address held in the register from the memory and holds the data in the register during a read cycle in which data written in the memory is read and converted into parallel / serial at predetermined intervals and output. And compare the data. When a failure occurs in the memory, the comparison means causes a mismatch between the data held in the register and the data read from the memory.

According to this configuration, the data to be written to the memory is temporarily stored in the register, and the data is sequentially read out and compared, so that the register can be shared for serial data. Therefore, regardless of the capacity of the memory, a failure of the memory can be detected with a small-capacity register, and the circuit scale can be reduced.

According to a fourth aspect of the present invention, there is provided a serial / parallel conversion circuit for converting serial data into parallel data, a write control circuit for designating an address for writing an output of the serial / parallel conversion circuit to a memory, A first memory for storing data output from the first-stage output port of the serial / parallel conversion circuit at an address designated by the write control circuit; a first data register for temporarily holding data stored in the first memory; A second memory for storing data output from a second-stage output port of the serial / parallel conversion circuit at an address designated by the write control circuit, and a second memory for temporarily storing data stored in the second memory. A data register, an address register for temporarily holding an address specified by the write control circuit, and an output data A read control circuit that specifies an address when reading data stored in the first memory and the second memory to generate data, an address held in the address register, and a read control circuit that specifies the address. A read address selecting circuit for selecting one of the selected addresses, and reading the data read from the first memory and the second memory when the address specified by the read control circuit is selected in the read address selecting circuit. A parallel / serial conversion circuit that converts the data into serial data and outputs the converted data; and the first read memory selects data read from the first memory when the address held in the address register is selected by the read address selection circuit. A first comparison circuit that compares the data with data held in a data register; A second comparison circuit that compares data read from the second memory with data held in the second data register when an address held in the address register is selected in the memory address selection circuit. When at least one of the first comparison circuit and the second comparison circuit has a data mismatch, the occurrence of a memory failure is detected.

The serial data is converted into parallel data by a serial / parallel conversion circuit. The data output from the first output port of the serial / parallel conversion circuit is stored in the first memory,
Data output from the second-stage output port of the parallel conversion circuit is stored in the second memory. At this time, the addresses of the first memory and the second memory where the data is written are specified by the write control circuit.

The first data register temporarily holds data stored in the first memory, the second data register temporarily holds data stored in the second memory, and the address register is instructed by the write control circuit. Hold the address temporarily. The read address selection circuit selects one of the address held in the address register and the address specified by the read control circuit, and when the address specified by the read control circuit is selected in the read address selection circuit, The data read from the first memory and the second memory is converted into serial data by the serial / serial conversion circuit to be output data.

When the address held in the address register is selected in the read address selection circuit,
The data read from the first memory by the first comparison circuit and the first data
The data stored in the data register is compared with the data held in the data register, and the data read from the second memory by the second comparison circuit is compared with the data held in the second data register. When data mismatch occurs in at least one of the first comparison circuit and the second comparison circuit, it is possible to detect that a memory failure has occurred.

According to this configuration, the write data to the first memory is temporarily stored in the first register, the write data to the second memory is temporarily stored in the second register, and these are sequentially read and compared. Therefore, it is possible to share a register for serial data. Therefore, regardless of the capacity of the memory, a failure of the memory can be detected with a small-capacity register, and the circuit scale can be reduced.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 denotes a serial / parallel conversion circuit for converting serial information data DIN into parallel data. A signal (write data) output from the first-stage output port (Q0) of the serial / parallel conversion circuit 1 is a first two-port RAM as a first memory.
(Random access memory) 2
A signal (write data) output from the second-stage output port (Q1) of the parallel conversion circuit 1 is input to a second two-port RAM 3 as a second memory.

The write control circuit 4 includes a first two-port RA
A write address of write data (an output signal of the serial / parallel conversion circuit 1) is specified for the M2 and the second two-port RAM 3, and the output signal (write address) of the first two-port RAM 2, Second
Are input to the two-port RAM 3 and the address register 7.

A signal (write data) output from the first-stage output port (Q0) of the serial / parallel conversion circuit 1 is input to the first data register 5, and the first data register 5 is connected to the first two ports. The write data stored in the RAM 2 is temporarily held. Further, a signal (write data) output from the output port (Q1) of the second stage of the serial / parallel conversion circuit 1 is input to the second data register 6, and the second data register 6 is connected to the second two ports. The write data stored in the RAM 3 is temporarily held. The address register 7 temporarily holds the write address output from the write control circuit 4.

An output signal of a read control circuit 8 for generating a read address and controlling reading is input to an input port a of a read address selection circuit 9. The output signal of the address register 7 is supplied to the read address selection circuit 9.
Is input to the input port b. The read address selection circuit 9 selects one of the addresses output from the read control circuit 8 and the address register 7 and transfers the data written to the selected address to the first 2
The data is read from the port RAM 2 and the second two-port RAM 3.

At this time, when data is read from the first two-port RAM 2 and the second two-port RAM by the read address output from the read control circuit 8,
The read data is converted by the parallel / serial conversion circuit 10 into serial data. That is, the parallel data read from the first two-port RAM 2 and the second two-port RAM 3 is converted into serial data by the parallel / serial conversion circuit 10 to generate output data DOUT.

When data is read from the first two-port RAM 2 and the second two-port RAM 3 based on the address held in the data register 7, the data read from the first two-port RAM 2 is the first data. Data input to the comparison circuit 11 and read from the second two-port RAM 3 is input to the second comparison circuit 12.

The first comparison circuit 11 includes a first two-port RA
The output of the first data register 5 is input in addition to the data read from M2, and it is determined whether the data read from the first two-port RAM 2 matches the data held in the first data register 5. . Second comparison circuit 12
Is input of the output of the second data register 6 in addition to the data read from the second two-port RAM 3,
The data read from the port RAM 3 is compared with the data held in the second data register 6 to determine whether they match. When data mismatch occurs in at least one of the first comparison circuit 11 and the second comparison circuit 12, a failure signal ERR is output.

The read data check control circuit 13 detects a failure in the data read from the first two-port RAM 2 and the second two-port RAM 3 so as to detect a failure in the read address selection circuit 9, the first comparison circuit 11, and the second comparison circuit. Circuit 12
Controls the operation of. Next, the operation of the present embodiment will be described with reference to FIGS. FIG. 2 is a time chart showing the operation timing on the write side of the present embodiment shown in FIG. 1, and FIG. 3 is a time chart showing the operation timing on the read side of the present embodiment.

The serial information data D shown in FIG.
When IN is input to the serial / parallel conversion circuit 1 in synchronization with the input clock, as shown in FIGS. 2B and 2C, the first-stage output (Q0) and the second output of the serial / parallel conversion circuit 1 are output. From the stage output (Q1), serial information data is output with a predetermined phase difference from the information data DIN. Also, from the write control circuit 4, FIG.
As shown in (d), the write address is output in synchronization with the input clock.

As shown in FIG. 2 (e), the data channels (data channel numbers output from the first stage output (Q0) of the serial / parallel conversion circuit 1 are shown in FIG.
At the timing when (b), (c), (e) and (f) are indicated by numerals), the data of the first-stage output (Q0) of the serial / parallel conversion circuit 1 is converted to the first channel.
2F, and at the same time, as shown in FIG. 2F, the data of the second-stage output (Q1) of the serial / parallel conversion circuit 1 is written into the second 2-port RAM 3 and the first data register 5. 2 Write to the data register 6. That is, data is written to the second two-port RAM 3 and the second data register 6 at the timing when the data channel output from the second-stage output (Q1) of the serial / parallel conversion circuit 1 becomes an odd channel. Is done.

At this time, the data is transferred to the first two-port RAM 2 and the second two-port RA 2 according to the write address (see FIG. 2D) output from the write control circuit 4.
Written to M3. At the same time, the write address is stored in the address register 7 as shown in FIG.
Are sequentially written to Here, the first two-port R
As shown in FIGS. 2E and 2F, the data written to the AM2 and the second two-port RAM 3 is reduced to half the speed of the information data DIN.

As shown in FIG. 3A, the read control circuit 8 synchronizes the read address AD with the output clock.
Generate R. Further, the write address held in the address register 7 is sequentially updated in accordance with the above-described write operation to the address register 7, as shown in FIG. The read address selection circuit 9 is as shown in FIG.
As shown in (1), the input port a and the input port b are alternately selected in synchronization with the output clock.

As a result, as shown in FIG. 3 (f), the addresses input to the first two-port RAM 2 and the second two-port RAM 3 are the read address ADR generated by the read control circuit 8 and the address register. 7 are alternately selected.

Therefore, as shown in FIG. 3G, the data corresponding to the read address ADR generated by the read control circuit 8 and the address held in the address register 7 are output from the first two-port RAM 2. Are read alternately. Further, as shown in FIG. 3H, the read control circuit 8 is output from the second two-port RAM 3.
The data corresponding to the read address ADR and the data corresponding to the address held in the address register 7 are alternately read.

The read data check control circuit 13 outputs data (address AD) corresponding to the read address ADR generated by the read control circuit 8 among the data read from the first two-port RAM 2 and the second two-port RAM 3.
R) is converted into serial data by the parallel / serial conversion circuit 10, and the output data D
OUT (see FIG. 3 (j)). In addition, the read data check control circuit 13 outputs the data (address register 7) corresponding to the address held in the address register 7 among the data read from the first two-port RAM 2.
Is input to the first comparison circuit 11 and the data (address register) corresponding to the address held in the address register 7 among the data read from the second two-port RAM 3 is input. 7) is input to the second comparison circuit 12.

In the first comparison circuit 11, a first two-port R
The data read from AM2 is compared with the data held in the first data register 5. Here, the data held in the first data register 5 is as shown in FIG.
As shown in (1), the data is sequentially updated according to the above-described write operation to the first data register 5, and is data corresponding to the address held in the address register 7. Therefore, if a failure has not occurred in the first two-port RAM 2, the data read from the first two-port RAM 2 matches the data held in the first data register 5.

In the second comparison circuit 12, the second two-port R
The data read from the AM 3 is compared with the data held in the second data register 6. Here, the data held in the second data register 6 is as shown in FIG.
As shown in (1), the data is sequentially updated in accordance with the above-described write operation to the second data register 6, and is data corresponding to the address held in the address register 7. Therefore, if no failure has occurred in the second two-port RAM 3, the data read from the second two-port RAM 3 and the data held in the second data register 6 match.

The first comparison circuit 11 or the second comparison circuit 12
In the case where the data mismatch occurs, the failure signal ERR is output because a failure has occurred in either the first two-port RAM 2 or the second two-port RAM 3. For example, when the data of the data channel number n + 6 held in the second data register 6 and the data of the data channel number n + 6 stored in the second two-port RAM 3 do not match, FIG. A failure signal ERR is output as shown in FIG.

As described above, according to the present embodiment, the first two-port RAM 2 and the second two-port RAM
When writing data to the data register 3, the data is held in the first data register 5 and the second data register 6, and the write address is also held in the address register 7. Also, during a read cycle in which data is read from the first two-port RAM 2 and the second two-port RAM 3 and output data is generated, the first data register 5 and the second data register 5 are read based on the address held in the address register 7. The data corresponding to the data held in the data register 6 is stored in a first two-port RAM 2 and a second two-port RAM 3
Read from If the data held in the first data register 5 and the data read from the first two-port RAM 2 do not match, or if the data held in the second data register 6 and the second two-port RAM 3
If the data read from the
It is configured to output R.

Therefore, the data held in the first data register 5, the second data register 6, and the data register 7 can be sequentially updated in accordance with the data write operation to the first two-port RAM 2 and the second two-port RAM 3. , Memory (first two-port RAM2 and second two-port RA2)
Registers required for the failure detection in M3) can be shared with serial input data. Thus, even if the capacity of the memories (the first two-port RAM 2 and the second two-port RAM 3) for storing the input data is large, the capacity of the register can be reduced, which is necessary for detecting a failure in the memory. The circuit scale can be reduced.

[0040]

As described above, according to the first to third aspects of the present invention, the data to be written to the memory is temporarily stored in the register, and the data is sequentially read out and compared. Can be shared. Therefore, regardless of the capacity of the memory, a failure of the memory can be detected with a small-capacity register, and the circuit scale can be reduced.

According to the fourth aspect of the present invention, the write data to the first memory is temporarily stored in the first register, the write data to the second memory is temporarily stored in the second register, and these are sequentially read out. The comparison makes it possible to share the register for serial data. Therefore, regardless of the capacity of the memory, a failure of the memory can be detected with a small-capacity register, and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing operation timing on the write side according to the embodiment of the present invention;

FIG. 3 is a time chart illustrating an operation timing on a reading side according to the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 serial / parallel conversion circuit 2 first two-port RAM (first memory) 3 second two-port RAM (second memory) 4 write control circuit 5 first data register 6 second data register 7 address register 8 read control Circuit 9 Read address selection circuit 10 Parallel / serial conversion circuit 11 First comparison circuit 12 Second comparison circuit 13 Read data check control circuit

Claims (4)

(57) [Claims] 1. An elastic store memory fault detecting device for writing serial data to a memory at a predetermined cycle and reading the serial data from the memory with a required phase, wherein when writing data to the memory, the data is written to the memory. Holding means for temporarily holding data in a register; and reading data corresponding to the data held in the register from the memory during a read cycle in which data written to the memory is read and output every required cycle. A comparing means for comparing the data stored in the register with the data, and detecting a fault in the memory based on a comparison result of the comparing means. 2. A fault detecting device for an elastic store memory which writes serial data to a memory at a predetermined period and reads the serial data from the memory at a required phase. Holding means for temporarily holding data and a write address in a register; and a read cycle in which data written to the memory is read and output in a required cycle from the memory to a write address held in the register. Reading means for reading data written at a corresponding address; and comparing means for comparing the data read by the reading means with the data held in the register. Elasty characterized by detecting obstacles Click store memory of the fault detection apparatus. 3. A fault detecting device for an elastic store memory which writes serial data to a memory in synchronization with a write clock and reads out the memory with a required phase in synchronization with the clock. Holding means for temporarily holding data and a write address to be written to the memory in a register when the data is written to the memory after performing a parallel conversion; reading data written to the memory at predetermined intervals; And comparing means for reading data corresponding to the write address held in the register from the memory and comparing the read data with the data held in the register during the read cycle. Elastomer characterized by detecting a memory failure Fault detector for physical store memory. 4. A serial / parallel conversion circuit for converting serial data into parallel data, a write control circuit for specifying an address for writing an output of the serial / parallel conversion circuit to a memory, and a serial / parallel conversion circuit. A first memory for storing data output from the first-stage output port at an address specified by the write control circuit, a first data register for temporarily storing data stored in the first memory, and a serial / parallel conversion circuit A second memory for storing data output from the second-stage output port at an address specified by the write control circuit; a second data register for temporarily storing data stored in the second memory; An address register that temporarily holds the address specified by the circuit, and an output register A read control circuit that specifies an address when reading data stored in the first memory and the second memory; and one of an address held in the address register and an address specified by the read control circuit. A read address selecting circuit to be selected, and converting the data read from the first memory and the second memory into serial data when an address specified by the read control circuit is selected in the read address selecting circuit. A parallel / serial conversion circuit as output data, the first address when the address held in the address register is selected in the read address selection circuit;
A first comparison circuit for comparing data read from a memory with data held in the first data register; and a second comparison circuit when the address held in the address register is selected in the read address selection circuit.
A second comparison circuit that compares data read from a memory with data held in the second data register, and when data mismatch occurs in at least one of the first comparison circuit and the second comparison circuit A memory failure detection device for detecting a failure in a memory.