JP2962246B2 - Operational amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier and, more particularly, to a field effect transistor (hereinafter referred to as "MOSFE").
T ") in the operational amplifier.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an example of a circuit configuration of a differential amplifier circuit portion in an operational amplifier using a conventional MOSFET.

Referring to FIG. 7, the sources of P-channel MOS transistors 1 and 2 forming a differential pair are connected in common, and the common connection point is connected to a constant current source 5 having one end connected to a higher power supply VCC. Connected to the other end 5i, the P channel M
The gates of the OS transistors 1 and 2 are connected to differential input terminals 1g and 2g, respectively.

The drains of P-channel MOS transistors 1 and 3 are connected to the drains of N-channel MOS transistors 3 and 4, respectively, and the gates of N-channel MOS transistors 3 and 4 are commonly connected to the drain of N-channel MOS transistor 3. It is connected. The source 3s of the N-channel MOS transistor 3 is connected via the resistor 11 and the source 4s of the N-channel MOS transistor 4.
Is connected to the lower power supply VEE via the resistor 12. N
The channel MOS transistors 3 and 4 form a current mirror circuit, and act as active loads of the differential pair transistors 1 and 2.

[0005] The constant current source 5 is a circuit for supplying a constant current from the higher power supply VCC.

Then, the P-channel MOS transistor 2
The output of the differential amplifier circuit is taken out from a terminal 2d connected to a connection point between the drain of the N channel MOS transistor 4 and the drain of the N channel MOS transistor 4.

By the way, when an operational amplifier formed as a semiconductor integrated circuit (referred to as "IC") in which a differential amplifier circuit is configured as shown in FIG. 7 is used in a certain system, an output of the differential amplifier circuit is used. It is necessary to remove the offset voltage generated at the terminal 2d.

In the prior art, as an offset adjusting means, a variable resistor such as a potentiometer or a micrometer as shown in FIG. 8 is connected to terminals 3s and 4s shown in FIG. 7 from outside the operational amplifier IC. The container 13 is connected.

Further, as a technique to which the above technique is applied, a plurality of diffusion resistance elements or polysilicon resistance elements 13-1 as shown in FIG. 9 are connected to terminals 3s and 4s shown in FIG. , 13-2,..., 13-n are connected in series, and a switch 14 is provided which can arbitrarily select ON / OFF between respective connection points between these resistance elements and the lower power supply VEE (Japanese Patent Application Laid-Open No. 61-1986). -224710,
See JP-A-7-111425). MOSF
As a prior art of an offset adjustment circuit in an operational amplifier using ET, Japanese Patent Application Laid-Open No. 61-224710 discloses a technique in which a plurality of diffused resistance elements or a plurality of diffusion resistance elements are provided between source electrodes of two transistors constituting a load transistor. There has been proposed a configuration of an operational amplifier in which polysilicon resistance elements are connected in series, a selection switch is connected between each connection point between the resistance elements and a power supply, and offset adjustment is performed by selecting the switch. ing. In addition, Japanese Patent Application Laid-Open
JP-A-1111425 discloses a nonvolatile transistor memory in which a plurality of resistance elements are connected between the sources of two transistors constituting a load transistor, and which operates as a selection switch between each connection point of the resistance elements and a negative power supply. An operational amplifier having a configuration including an address transistor has been proposed.

The two offset adjusting means shown in FIGS. 8 and 9 are exactly the same in the principle of adjusting the offset voltage, and are as follows.

The load N-channel MOS in the differential amplifier circuit shown in FIG. 7 is supplied by the midpoint terminal connected to the lower power supply VEE as shown in FIG. 8 or by setting the selection switch 14 as shown in FIG. Resistors 11, 12, 13 connected to the sources 3s, 4s of the transistors 3, 4
Is a circuit connection as shown in FIG.

As shown in FIG. 10, resistors 11 and 13A are connected in parallel.
Are connected in parallel.

Since the resistors 13A and 13B shown in FIG. 10 are two divided resistors of the variable resistor 13, the circuit configuration of FIG. 10 is equivalently equivalent to two variable resistors (FIG. 11). The circuit connection is represented by trimming resistors 15 and 16.

Accordingly, the offset voltage of the differential amplifier circuit is adjusted by appropriately adjusting the two trimming resistors 15 and 16 shown in FIG.

As a specific example, it is assumed that the two trimming resistors 15 and 16 shown in FIG. 11 are respectively constituted by variable resistors that can be adjusted from 0Ω to 2 kΩ.

The above setting is realized by setting the (fixed) resistors 11 and 12 in FIG. 7 to 4 KΩ and the combined resistance of the resistor element array (trimming resistor) 13 shown in FIG. 9 to 4 kΩ.

In this specific example, the range in which the offset voltage of the differential amplifier circuit of the operational amplifier can be adjusted is a range in which two trimming resistors can be adjusted and a change equivalent to 4 kΩ.

Although the principle of adjusting the offset voltage in the above two means is the same as described above, FIG.
The means for providing a variable resistor for offset adjustment inside the operational amplifier IC as shown in (1) can make the system compact and monolithic.

[0019]

The means for providing a variable resistor for offset adjustment inside the operational amplifier IC as shown in FIG. 9 is based on the fact that the polarity of the parasitic offset voltage of the differential amplifier circuit of the operational amplifier is either positive or negative. In this case, both of the trimming resistors 15 and 16 shown in FIG.

Incidentally, the resistors 11 and 12 used in the operational amplifier IC as shown in FIG. 7 and the resistor element array 13 as shown in FIG. 9 are made of a diffusion resistor or a polysilicon resistor.

Since the offset voltage is a parasitic offset voltage peculiar to each operational amplifier IC, the offset voltage can be adjusted in a wider range or finer in resolution. , The resistance value of the resistors 11 and 12 (see FIG. 7) of the differential amplifier circuit and the combined resistance value of the resistor element array 13 for offset adjustment (see FIG. 9) are increased or the resistance element array 1 is increased.
It is necessary to reduce the resistance value (unit resistance value) of the unit element 3 and increase the number of unit elements.

Therefore, in order to satisfy the above condition, the area occupied by the diffusion resistance or the polysilicon resistance increases.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide an IC for an offset adjustment circuit composed of a diffusion resistor or a polysilicon resistor.
An object of the present invention is to provide an operational amplifier in which the area occupied by the device is greatly reduced (preferably less than about half of the prior art), and the offset adjustment capability equivalent to that of the related art is maintained. Also, the present invention provides an operational amplifier IC having an offset adjustment circuit.
Alternatively, in an IC incorporating a similar operational amplifier, miniaturization of the IC and miniaturization of the system are achieved.
It is another object of the present invention to provide an operational amplifier that achieves an improvement in the productivity of the above.

[0024]

To achieve the above object, the present invention relates to an operational amplifier including a differential amplifier circuit, wherein the differential amplifier is connected to a power source via first and second switches, respectively. Are connected to the first and second load transistors, between the sources of the first and second load transistors, are a plurality of resistance elements connected in series, and each of the resistance elements A series of switches connected in parallel with each other to control the offset voltage by controlling on / off of the first switch, the second switch, and the switch series. And so on.

Further, according to the present invention, in an operational amplifier including a differential amplifier circuit, the differential amplifier has a source connected to a constant current source connected to a power supply via first and second switches, respectively. An input stage differential pair comprising first and second transistors; a resistor element row in which a plurality of resistor elements are connected in series between the sources of the first and second transistors; And a switch train formed by connecting switches connected in parallel. The offset voltage is adjusted by controlling on / off of the first switch, the second switch, and the switch train. It is characterized by being constituted as follows.

[0026]

Embodiments of the present invention will be described below. According to a preferred embodiment of the present invention, the offset adjustment circuit of the differential amplifier circuit of the operational amplifier includes a switch (6, 7 in FIG. 1) for switching a current inflow route depending on the polarity of the parasitic offset voltage, and an offset voltage adjustment circuit. One trimming resistor to be made (8 in FIG. 1)
Is provided.

In the embodiment of the present invention, when operating with a parasitic offset voltage, the trimming resistor (8 in FIG. 1) is placed on the side where the current of the differential amplifier circuit largely flows due to the offset voltage. The switches (6 and 7 in FIG. 1) are switched so that the current flows through.

Thereafter, the trimming resistor (8 in FIG. 1) is
The switch array (9 in FIG. 1) is turned on / off and adjusted to an appropriate size to equalize the current flowing through the differential amplifier circuit.
Thereby, the offset voltage is adjusted.

The embodiment of the present invention will be described in more detail. FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

Referring to FIG. 1, in the embodiment of the present invention, the differential amplifier circuit of the operational amplifier comprises a first load transistor 3 having a source connected to a power supply VEE via a first switch 6, A second load transistor 4 having a source connected to the power supply VEE via a second switch 7;
And a resistance element array 8 in which a plurality of resistance elements are connected in series between the sources of the first and second load transistors 3 and 4.
And a switch array 9 connected in parallel to each of the resistance elements. The first switch 6, the second switch 7, and the on / off of the switch array 9 are controlled to adjust the offset voltage.

FIG. 2 is a diagram showing the configuration of the embodiment of the present invention. Referring to FIG. 4, in another embodiment of the present invention, the differential amplifier has a source connected to a constant current source 5 connected to a power supply VCC via first and second switches 6, 7, respectively. First and second transistors 1, 2
, A resistance element array 8 in which a plurality of resistance elements are connected in series between the sources of the first and second transistors 1 and 2, and a switch connected in parallel to each of the resistance elements in series. Switch row 9 connected to the
By controlling ON / OFF of the switch 6, the second switch 7, and the switch array 8, the offset voltage is adjusted.

In the embodiment of the present invention, the switches used for the offset adjustment are preferably analog switches such as a polysilicon fuse capable of selecting from short to open and a transfer gate capable of selecting between short and open. An element having such a structure is used.

In the embodiment of the present invention, preferably, a circuit for controlling ON / OFF of the switch is built in the operational amplifier IC.

[0034]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[0035]

Embodiment 1 FIG. 1 is a diagram showing a configuration of a differential amplifier circuit in an operational amplifier according to one embodiment of the present invention. Referring to FIG. 1, in the present embodiment, P
The sources of the channel MOS transistors 1 and 2 are connected in common, and the common connection point is connected to the other end of the constant current source 5 whose one end is connected to the higher power supply VCC.
The gates of the S transistors 1 and 2 are connected to differential input terminals 1g and 2g, respectively. The drains of P-channel MOS transistors 1 and 2 are connected to the drains of N-channel MOS transistors 3 and 4, respectively. The gates of N-channel MOS transistors 3 and 4 are commonly connected and connected to the drain of N-channel MOS transistor 3. I have.

Then, the N-channel MOS transistor 3
Source 3s through switch 6 and N channel M
The source 4s of the OS transistor 4 is connected to the lower power supply VEE via the switch 7.

Further, the source 3s of the N-channel MOS transistor 3 and the source 4s of the N-channel MOS transistor 4 are connected via a resistor element array 8 in which a plurality of resistor elements are connected in series.

Switch elements are connected in parallel between the terminals of each resistance element in the resistance element row 8, and the plurality of switch elements are connected in series to form a switch row 9.

The constant current source 5 is a circuit for supplying a constant current from the higher power supply VCC.

The output of the differential amplifier circuit is taken out from a terminal 2d connected to a connection point between the drain of the P-channel MOS transistor 2 and the drain of the N-channel MOS transistor 4.

In the differential amplifier circuit having the above configuration, the differential amplifier circuit is formed by a combination of ON / OFF of the current inflow route changeover switches 6 and 7 and the switch array 9 for controlling the resistor array 8 as a trimming resistor. Can be adjusted.

Next, in the dynamic amplifying circuit according to the present embodiment, the switches 6, 7, 9 for adjusting the parasitic offset voltage
Will be described below with reference to FIGS. 2 and 3.

The circuit shown in FIG. 2 is a diagram showing the circuit connection of only the switches 6, 7, 9 and the trimming resistor 8 of the differential amplifier circuit shown in FIG.

In the circuit shown in FIG. 2, for the sake of convenience, a plurality of resistor elements constituting the trimming resistor 8 are assumed to be connected in series with n pieces, and 8-1 and 8-
2, ..., 8-n.

In the circuit shown in FIG. 2, a plurality of switches forming the switch row 9 are connected to the resistance elements 8-1 and 8-8.
9-1, 9- according to -2, ..., 8-n
2, ..., 9-n.

First, as shown in FIG. 2, all the switches 6, 7, 9 (9-1, 9-2,..., 9-n)
All are in the ON state (closed state) and this is the initial state.

In this initial state, the differential amplifier circuit in the operational amplifier of this embodiment operates by generating a parasitic offset voltage unique to each operational amplifier IC.

In the circuit shown in FIG. 1, adjustment of the offset voltage when the polarity of the parasitic offset voltage represented by the voltage difference between one differential input terminal 1g and another differential input terminal 2g indicates the positive direction. The method will be described below.

In the initial state, in the circuit shown in FIG. 2, the current flowing to the source of P-channel MOS transistor 2 is larger than the current flowing to the source of P-channel MOS transistor 1.

As a process (step) 1, P shown in FIG.
Current flowing to the source of the channel MOS transistor 2,
That is, the source 4s of the N-channel MOS transistor 4
The switch 7 is turned off (open) to limit the current flowing through the switch (the switch 6 remains closed).

When the switches 9-1, 9-2,..., 9-n in FIG. 2 are sequentially turned off (open) after the process 1, a current path flowing to the source 4s of the N-channel MOS transistor 4 has a resistance. Elements 8-1, 8-2, ..., 8
−n are sequentially added, so that this is
If it is considered to be equivalent to 0, it can be represented by a circuit as shown in FIG.

In the circuit shown in FIG.
If the variable resistor 10 is increased until the current flowing to the source 4s of the S transistor 4 becomes equal to the current flowing to the source 3s of the N-channel MOS transistor 3, the parasitic offset voltage disappears.

That is, in step 2, referring to FIG. 2, switches 9-1, 9-2,..., 9-n are sequentially turned off until the parasitic offset voltage of the differential amplifier circuit disappears.

As described above, the offset voltage in the positive direction of the differential amplifier circuit according to the present embodiment is adjusted in steps 1 and 2 from the initial state.

Next, in the case where the polarity of the parasitic offset voltage represented by the voltage difference between one differential input terminal 1g and another differential input terminal 2g in the differential amplifier circuit shown in FIG. 1 indicates a negative direction. The method of adjusting the offset voltage will be described below.

In the initial state in the above case, in the circuit shown in FIG. 2, the current flowing to the source of P-channel MOS transistor 2 is
Smaller than the current flowing to the source.

As the process 3, the P-channel MO shown in FIG.
The switch 6 is turned off (open) in order to limit the current flowing to the source of the S transistor 1, that is, the current flowing to the source 3s of the N-channel MOS transistor 3.

Thereafter, as described above, the offset voltage in the negative direction of the differential amplifier circuit in this embodiment is adjusted through the process 2.

As a specific example, it is assumed that the trimming resistor 8 in FIG. 1 is a resistor element array that can be adjusted from 0Ω to 2 kΩ.

In this specific example, the range in which the offset voltage of the differential amplifier circuit of the operational amplifier can be adjusted is 4 kΩ in both positive and negative directions by switching the switches 6 and 7 of the differential amplifier circuit.
This is a considerable change.

[0061]

Embodiment 2 FIG. 4 shows a circuit configuration of a differential amplifier circuit of an operational amplifier according to another embodiment of the present invention.

Referring to FIG. 4, the differential amplifier circuit of the operational amplifier according to the present embodiment is configured such that the other terminal 5i of the constant current source 5 having one end connected to the higher power supply VCC is connected to the P-channel It is connected to the source 1s of the MOS transistor 1 and to the source 2s of the P-channel MOS transistor 2 via the switch 7. The gates of P-channel MOS transistors 1 and 2 are differential input terminals 1g and 2g, respectively.
It is connected to the.

The drains of P-channel MOS transistors 1 and 2 are connected to the drains of N-channel MOS transistors 3 and 4, respectively. The gates of N-channel MOS transistors 3 and 4 are commonly connected and connected to the drain of N-channel MOS transistor 3. The sources of the N-channel MOS transistors 3 and 4 are commonly connected and connected to the lower power supply VEE.

In this embodiment, the source 1 s of the P-channel MOS transistor 1 and the source 2 s of the P-channel MOS transistor 2 are connected via a resistor element array 8 in which a plurality of resistor elements are connected in series.

Switch elements are connected in parallel between the terminals of each resistance element in the resistance element row 8, and the plurality of switch elements are connected in series to form a switch row 9.

A terminal 2d connected to the drain of the P-channel MOS transistor 2 is an output terminal of the differential amplifier.

In the differential amplifier circuit having the above-described configuration, the first embodiment is realized by a combination of on / off of the current inflow route changeover switches 6 and 7 and the switch array 9 for controlling the resistor array 8 as a trimming resistor. Similarly, the parasitic offset voltage can be adjusted.

The switching process of the switches 6, 7, and 9 for adjusting the parasitic offset voltage in the differential amplifier circuit according to the present embodiment will be described below with reference to FIGS.

The circuit shown in FIG. 5 is a circuit diagram showing only the switches 6, 7, 9 and the trimming resistor 8 of the differential amplifier circuit shown in FIG.

In the circuit shown in FIG. 5, for the sake of convenience, it is assumed that n pieces of resistance elements constituting the trimming resistor 8 are connected in series, and the n pieces of resistance elements are 8-1, 8-2, ..., 8-n. Further, in the circuit shown in FIG. 5, a plurality of switches constituting the switch array 9 are adjusted to 9-1, 9-2,..., Respectively, according to the resistance elements 8-1, 8-2,. , 9-n.

First, as shown in FIG. 5, all the switches 6, 7, 9 (9-1, 9-2,..., 9-n) are all in an on state (closed state). State.

Thereafter, by selecting a switch to be opened by the parasitic offset voltage in the same process as in the first embodiment, the offset voltage of the differential amplifier circuit in the present embodiment is adjusted.

FIG. 6 shows the circuit configuration shown in FIG. 3 referred to in the description of the offset voltage adjustment in the first embodiment.
FIG. 3 is a diagram illustrating a circuit configuration applied to the present embodiment.

As a specific example, it is assumed that the trimming resistor 8 in FIG. 5 is a resistor element array that can be adjusted from 0Ω to 2 kΩ.

In this specific example, the range in which the offset voltage of the differential amplifier circuit of the operational amplifier can be adjusted is a change equivalent to 4 kΩ in positive and negative directions by switching the switches 6 and 7 of the differential amplifier circuit of this embodiment. Become.

In the present embodiment, the trimming resistor 8 is connected to one of the source terminals 1 s and 2 s of the P-channel MOS transistors 1 and 2 which are the input differential pair for receiving the differential input signal voltage of the differential amplifier circuit. Is done.

On the other hand, in the first embodiment, the trimming resistor 8 is a load transistor N of the differential amplifier circuit.
Source terminals 3s of the channel MOS transistors 3 and 4;
4s (see FIG. 1).

The range in which the offset voltage can be adjusted is a variation equivalent to 4 kΩ in both the present embodiment and the first embodiment.
Normally, the input differential pair transistor is designed to have a larger current capability than the load transistor. Therefore, in the present embodiment, the actual adjustment range of the offset voltage is larger than in the configuration of the first embodiment.

As described above, according to the above embodiments, it is possible to precisely adjust the offset voltage of the differential amplifier circuit by two.
This is possible only by using one switch and one trimming resistor.

In the above prior art, as shown in the specific example, each of the resistors 11 and 12 in FIG.
Ω, and the resistance element row 13 in FIG. 9 requires a total of 4 kΩ.

On the other hand, according to the present invention, as shown in the above embodiment, the trimming resistor 8 in FIG. 1 requires a total of 2 kΩ.

Generally, the diffusion resistance and the polysilicon resistance used in the IC have a specific resistance of several tens Ω to several hundreds Ω. The occupied area increases.

The size of the switch used in the above embodiment is sufficiently smaller than the above resistor and can be ignored.

In consideration of the above points, the present invention makes it possible to realize the same accuracy as the offset voltage adjustment of the prior art with an offset adjustment circuit having an area less than half that of the above prior art. Further, it is possible to further reduce the size of the system using the operational amplifier IC including the differential amplifier circuit.

In the above embodiment, the differential amplifier circuit of the operational amplifier has been described with respect to an example in which the differential pair transistors having the differential input signals as inputs are constituted by P-channel MOS transistors. The present invention is also applied to a differential amplifier circuit of an operational amplifier when this differential pair is an N-channel MOS transistor. In this case, the load transistors constituting the active load of the differential pair are P-channel MOS transistors.

[0086]

As described above, according to the present invention,
It is possible to precisely adjust the offset voltage of the differential amplifier circuit by using only two switches and one trimming resistor. According to the present invention, it is possible to realize the same accuracy as the offset voltage adjustment of the above-described conventional technology with an offset adjustment circuit having an area of, for example, half or less of that of the above-described conventional technology. Thus, it is possible to reduce the size of the operational amplifier IC including the above, and to further reduce the size of the system using the operational amplifier IC.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a configuration of an offset adjustment circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining an operation of the offset adjustment circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of an offset adjustment circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining the operation of the offset adjustment circuit according to the second embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a differential amplifier circuit in an operational amplifier according to the related art.

FIG. 8 is a diagram showing a configuration of a conventional variable resistor for offset adjustment.

FIG. 9 is a diagram illustrating an offset adjustment circuit using a trimming resistor of a differential amplifier circuit in an operational amplifier according to the related art.

FIG. 10 is a diagram for explaining an operation of a conventional offset adjustment circuit.

FIG. 11 is a diagram equivalently showing a circuit for explaining the operation of the conventional offset adjustment circuit.

[Explanation of symbols]

Reference Signs List 1 P-channel MOS transistor 1 g Gate terminal of transistor 1 1 s Source terminal of transistor 1 2 P-channel MOS transistor 2 g Gate terminal of transistor 2 2 s Source terminal of transistor 2 d Drain terminal of transistor 2 3 N-channel MOS transistor 3 s Source of transistor 3 Terminal 4 N-channel MOS transistor 4s Source terminal of transistor 4 5 Constant current source 5i Terminal for supplying constant current of constant current source 5 6 Short / open switch 7 Short / open switch 8 Trimming resistors 8-1, 8 -2, 8-n Unit resistance elements constituting the trimming resistor 8 9 Short / open changeover switch row 9-1, 9-2, 9-n Unit switch elements of the switch row 9 10 Variable resistor 11 resistor Reference Signs List 12 resistance 13 variable resistance 13-1, 13-2, 13-n unit resistance element constituting variable resistance 13 13A one resistance obtained by dividing variable resistance 13 13B the other resistance obtained by dividing variable resistance 13 14 arbitrary terminal Switch that can be selected open / short circuit 15 Trimming resistor 16 Trimming resistor VCC High power supply VEE Low power supply

Claims (8)

(57) [Claims] 1. An operational amplifier including a differential amplifier circuit, wherein: the differential amplifier includes first and second load transistors each having a source connected to a power supply via first and second switches; 1, a resistor string in which a plurality of resistive elements are connected in series between the sources of the transistors of the second load, and a switch row in which switches connected in parallel to the respective resistive elements are connected in series; An operational amplifier, comprising: adjusting an offset voltage by controlling on / off of the first switch, the second switch, and the switch array. 2. An operational amplifier including a differential amplifier circuit, wherein the differential amplifier has first and second sources connected to a constant current source connected to a power supply via first and second switches, respectively. An input stage differential pair including two transistors, a resistance element row in which a plurality of resistance elements are connected in series between sources of the first and second transistors, and a resistance element connected in parallel to each of the resistance elements. And a switch array formed by connecting switches in series, wherein the first switch, the second switch, and on / off of the switch array are controlled to adjust an offset voltage. An operational amplifier characterized by being performed. 3. The method according to claim 1, wherein the first and second switches and the switch row are formed of polysilicon fuses, and switching control from on to off is performed by selecting the polysilicon fuse from short to open. The operational amplifier according to claim 1 or 2, wherein: 4. The operational amplifier according to claim 1, wherein said first and second switches and said switch array are formed of analog switches acting as transfer gates. 5. The operational amplifier according to claim 1, wherein the first and second switches and a circuit for controlling on / off of the switch array are built in a semiconductor integrated circuit. 6. A differential pair comprising first and second transistors having a control terminal to which a differential input signal is inputted, and third and fourth transistors constituting an active load of the differential pair. An operational amplifier including a differential amplifier circuit provided, wherein each one signal terminal of the first and second transistors is connected to a constant current source via first and second switches, and A resistor element composed of a plurality of resistance elements connected in series between the one signal terminal of the second transistor, and a switch row formed by connecting in series a switch connected in parallel between the terminals of the resistance element; An operational amplifier characterized in that the operational amplifier is inserted. 7. A differential pair comprising first and second transistors having a control terminal to receive a differential input signal, and third and fourth transistors forming an active load of the differential pair. An operational amplifier including a differential amplifier circuit provided, wherein one signal terminal of each of the third and fourth transistors is connected to a power supply via first and second switches,
A switch formed by serially connecting a resistor element including a plurality of resistor elements connected in series between the one signal terminal of the third and fourth transistors and a switch connected in parallel between the terminals of the resistor element. An operational amplifier characterized by inserting a row and a row. 8. An operational amplifier including an offset voltage adjusting circuit of a differential amplifier circuit, wherein first and second switches are inserted into two current paths of an input-stage differential pair of the differential amplifier circuit, respectively. The two current paths are connected by a trimming resistor, and the current flows through the trimming resistor to the side where the current of the input-stage differential pair largely flows in accordance with the polarity of the offset voltage polarity of the differential amplifier circuit. After the first and second switches are switched so as to flow, the trimming resistor is adjusted to an appropriate size to equalize the current flowing through the input stage differential pair, thereby adjusting the offset voltage. An operational amplifier characterized by being configured as follows.