JP2961188B2 - Method for manufacturing SOI substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention [relates] to a method for manufacturing an SOI substrate having an SOI (S ilicon O n I nsulator ) structure obtained by forming a single-crystal silicon film on an insulating film.

[Conventional technology]

A structure in which a single-crystal silicon layer is formed over an insulating film (including an insulating substrate) is called an SOI structure, and has a SOI structure.
The I-substrate is known as a substrate capable of easily performing element isolation in a narrow region and achieving high integration or high speed.
Semiconductor integrated circuits in which devices are fabricated on such an SOI substrate can have improved characteristics as compared with conventional semiconductor integrated circuits in which devices are fabricated on a silicon substrate. Research is ongoing.

As a method for forming a single crystal silicon film on the insulating film, there is a solid-phase growth (S olid P hase E pitaxy, SPE) method. This is to form an insulating film on a single crystal silicon substrate,
This insulating film is selectively etched to expose a part of the substrate surface, and an amorphous silicon film (hereinafter referred to as an a-Si film) is deposited on the exposed portion of the substrate and the insulating film. in by annealing, as the seed exposed portions of the substrate surface, first longitudinal solid phase growth to (V ertical S olid P
hase E pitaxy, V-SPE) is, lateral solid phase growth subsequently (L ateral S olid P hase E pitaxy, L-SPE)
Thus, the a-Si film is made into a single crystal.

However, the deposited a-Si film is non-doped a-Si film.
In the case of a Si film, the lateral solid phase growth distance (L-SPE distance) is about 5 μm, and there is a disadvantage that the size of the SOI region to be formed is limited. As a method for extending the L-SPE distance, there is known a method in which P ⁺ ions are implanted at a high concentration into an a-Si film on an insulating film and then an annealing treatment is performed (Japanese Journal of Applied Physics Vol. 25, No. .Five
(1986) 667). However, one P ⁺ ion is contained in the a-Si film.
Since doping is performed at a high concentration of about 3 × 10 ²⁰ cm ⁻³ , the impurity (P) concentration in the single-crystal silicon film grown by solid phase becomes extremely high. It is difficult to manufacture a desired semiconductor element.

[Problems to be solved by the invention]

As described above, in the conventional solid-phase growth method (SPE method), a lateral growth distance (L-SPE distance) does not increase, and a large-area SOI substrate suitable for manufacturing a semiconductor element can be obtained. In some cases, the desired semiconductor element cannot be manufactured due to the high impurity concentration in the single crystal silicon film.

The present invention has been made in view of such circumstances, and L
An object of the present invention is to provide a method for manufacturing an SOI substrate which can manufacture an SOI substrate having a larger area by extending the SPE distance.

[Means for solving the problem]

In the method for manufacturing an SOI substrate according to the present invention, an insulating film is formed over a single crystal semiconductor base, and an opening is selectively formed in the insulating film so as to expose the single crystal semiconductor base. An amorphous silicon film is deposited on the insulating layer including the surface of the single crystal semiconductor base, and the single crystal silicon film is epitaxially grown by annealing the amorphous silicon film.
In the method of manufacturing an I-substrate, the deposition of the amorphous silicon film is performed in two stages, and the first-stage deposition temperature is lower than the second-stage deposition temperature.

[Action]

In the method for manufacturing an SOI substrate of the present invention, the a-Si film is deposited in two stages, and the deposition temperature in the first stage is reduced to the second stage.
Lower than the step deposition temperature. Then, generation of crystal defects and polycrystalline nuclei at the interface between the single crystal silicon film and the insulating film, which has hindered the extension of the L-SPE distance, is suppressed.
As a result, the L-SPE distance is extended and the SOI region is expanded, and in addition, the crystallinity of the SOI substrate is improved.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments.

FIG. 1 shows a configuration of a CVD apparatus used in the manufacturing method of the present invention and capable of maintaining an ultrahigh vacuum state in a reaction chamber. In the figure, reference numerals 11 and 12 denote a reaction chamber and a sample preparation chamber, respectively. The reaction chamber 11 and the sample preparation chamber 12 are opened and closed by opening and closing a gate valve 13.
The state is switched to the communication state and the cutoff state.

In the reaction chamber 11, a gas such as SiH ₄ or Ar is introduced from a gas introduction pipe 14 and exhausted from an exhaust pipe 15. In addition, the exhaust of the reaction chamber 11 and the exhaust of the sample preparation chamber 12 when the gas is not introduced are performed through the exhaust pipe 16. Gas inlet pipe 17 in sample preparation chamber 12
Nitrogen is introduced from the vacuum chamber to leak from the vacuum. The sample (substrate) set on the susceptor 18 is transferred into the reaction chamber 11 by the transfer system 19 and set together with the susceptor 18 on the susceptor holder 20. Heating the sample (substrate)
The temperature is monitored by an infrared lamp 21, monitored by a thermocouple 22, and controlled by a temperature control circuit 23.

A sample (substrate) is set in the reaction chamber 11 as follows. First, with the gate valve 13 closed, the inside of the reaction chamber 11 is evacuated, and the gas introduction pipe 17 is inserted into the sample preparation chamber 12.
To introduce nitrogen to perform leakage. After that, the sample (substrate) is set on the susceptor 18 and put into the sample preparation chamber 12,
The inside of the sample preparation chamber 12 is evacuated from the exhaust pipe 16, the gate valve 13 is opened, and the susceptor 18 is moved by the transfer system 19 to the susceptor holder.
Set to 20. Then, the transfer system 19 is returned into the sample preparation chamber 12, and the gate valve 13 is closed. When removing the sample (substrate), the sample preparation chamber 12 is evacuated, the gate valve 13 is opened, the susceptor 18 is carried into the sample preparation chamber 12 by the transport system 19, and the gate valve 13 is closed again. Then, the sample (substrate) is taken out in a state where nitrogen is introduced into the sample preparation chamber 12 and the atmospheric pressure is reached.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of the embodiment of the present invention.

Figure 1 is a (100) is a single crystal silicon substrate surface as a single crystal semiconductor base having a major surface, the SiO ₂ film 2 having a film thickness of about 0.1μm as an insulating film on its surface, thermal oxidation or CVD
It is formed by a method (FIG. 2A). Next, an opening 2a is selectively formed in the SiO ₂ film 2 by a known photolithography technique in order to expose the surface of the silicon substrate (seed portion 1a) as a seed (FIG. 2 ( b)).

Single crystal silicon substrate 1 on which SiO ₂ film 2 is patterned
Is chemically cleaned by the RCA method, and then the CVD shown in FIG.
It is set in the reaction chamber 11 of the device. 1 × 10 ^-7 inside the reaction chamber 11
Exhaust to a vacuum of about Torr, and infrared lamp 21
To 450 to 500 ° C. and heating heating, after the temperature is constant, SiH ₄
A gas is supplied at a flow rate of 200 cc / min and a pressure of 5 Torr, and the gas is supplied on the silicon substrate surface (seed portion 1a) exposed from the opening 2a and
On the SiO ₂ film 2, a first-stage lower a-Si film 3a is formed to a thickness of 0.
Deposit about 1 μm (FIG. 2C). A-Si of lower layer
When the deposition of the film 3a is completed, the supply of the SiH ₄ gas is stopped, the SiH ₄ gas is purged with Ar gas for several minutes, and then the inside of the reaction chamber 11 is again evacuated to about 1 × 10 ⁻⁷ Torr. And heated to 550 ° C with an infrared lamp 21 to make the temperature constant, then flow SiH ₄ gas at a flow rate of 200 cc / min and a pressure of 5 Torr.
Then, an upper a-Si film 3b of the second stage is deposited to a thickness of about 1.5 μm on the lower a-Si film 3a (FIG. 2 (d)).

SiH ₄ supply of gas is stopped, after the purge of the SiH ₄ gas in an Ar gas for a few minutes, 600 ° C. at an N ₂ atmosphere
The solid-phase growth of the a-Si films 3a, 3b is performed by annealing at a temperature of about the same temperature to form a single-crystal silicon film 4 in which the a-Si films 3a, 3b are monocrystallized (FIG. 2 ( e)).

Although a single crystal silicon substrate is used as the single crystal semiconductor base in the above-described embodiment, a substrate with single crystal silicon formed on the surface may be used as the single crystal semiconductor base.

Conventionally, in the solid-phase growth method, crystal defects and polycrystalline nuclei generated near the interface between the grown single crystal silicon and the SiO ₂ film as an insulating film reduce the L-SPE distance or grow the single crystal silicon film. There is a problem that the crystallinity of the material is lowered (J. Appl. Phys. 54 (5), May (1983) 284).
7), (Jpn. J. Appl. Phys. Vol. 25, No. 10 (1986) L81
Four). By the way, when the deposition temperature is lowered when depositing the a-Si film, it is possible to suppress the generation of crystal defects and polycrystalline nuclei, but in this case, a practical deposition rate can be obtained. Or the problem of high impurity concentration (Jpn. J. Appl. Phys. Vol. 21, No. 10 (1982) 143)
1).

Under such circumstances, in the present invention, the deposition process of the a-Si film is divided into two stages, and the respective deposition temperatures are made different. Specifically, the first stage, that is, the deposition of the lower a-Si film 3a (about 0.1 μm thick) near the interface with the insulating film (SiO ₂ film 2) is performed at a low temperature of about 450 to 500 ° C. To suppress the generation of crystal defects and polycrystalline nuclei, and to deposit the upper a-Si film 3b (film thickness) on the lower a-Si film 3a deposited in the second step, that is, the first step. (About 1.5 μm) is a deposition temperature of 550 ° C. (Jpn.J.Appl.Phy.)
s.Vol.21, No.10 (1982) 1431). By doing so, the conventional problems can be solved, and the thickness of the practical a-Si film as a whole (Appl. Phys. Lett. 52 (21), 23)
May (1988) 1788), and a large-area SOI region with good crystallinity can be obtained.

FIG. 3 is a graph showing the relationship between the annealing time and the L-SPE distance. The horizontal axis represents the annealing time (hour), the vertical axis represents the L-SPE distance (μm), and the numerical value in the graph represents the growth rate (Å).
/ Sec), and-●-and-○-represent the present invention example and the conventional example, respectively. As is clear from the graph shown in FIG. 3, an L-SPE distance of 10 μm, which is about twice that of the conventional example, can be obtained by using the manufacturing method of the present invention.

〔The invention's effect〕

As described above, in the method for manufacturing an SOI substrate of the present invention, a
By performing the deposition of the Si film in two stages, and making the deposition temperature of the first stage lower than the deposition temperature of the second stage,
Generation of crystal defects and polycrystalline nuclei near the interface with the insulating film can be suppressed, and a larger-area SOI substrate can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a CVD apparatus used to carry out the method of manufacturing an SOI substrate of the present invention, FIG. 2 is a cross-sectional view showing steps of the method of manufacturing an SOI substrate of the present invention, and FIG. It is a graph which shows the relationship between the annealing time and L-SPE distance in the invention example and the conventional example. 1 ... Single-crystal silicon substrate (single-crystal semiconductor base), 1a ...
... Seed part, 2 ... SiO ₂ film (insulating film), 2a ...
3a: lower a-Si film, 3b: upper a-Si film, 4 ...
Single crystal silicon film

Claims (1)

(57) [Claims] An insulating film is formed on a single crystal semiconductor base, and an opening is selectively formed in the insulating film to expose the single crystal semiconductor base. A method of depositing an amorphous silicon film on the insulating layer including the surface and epitaxially growing a single crystal silicon film by annealing the amorphous silicon film to produce a SOI substrate, A method for manufacturing an SOI substrate, wherein the deposition is performed in two stages, and the first stage deposition temperature is lower than the second stage deposition temperature.