JPH05234887A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve throughput by increasing an area of a faucet grown region in {110} having little dislocation, shortening an annealing time for solid epitaxially growing and omitting the number of steps. CONSTITUTION:An insulating film 2 made of an SiO2 film, etc., is formed on a surface of a single crystalline Si substrate 1, and selectively etched to form an opening window 3 in which a partial surface of the substrate is exposed. After an amorphous Si film 4 having a thickness of 0.5mum or more is deposited on the surface of the substrate 1 and the surface of the film 2 exposed in the window 3, it is annealed at 625 deg.C or lower of a substrate temperature, and solid epitaxially grown with the Si single crystal of the substrate 1 exposed in the window 3 as a seed. Then, the film 4 is single crystallized to form a single crystalline Si film 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an SOI (Silicon-On-Insulator) structure having a semiconductor layer on the surface of an insulator.

[0002]

2. Description of the Related Art The so-called SOI structure, in which a single crystal Si film is formed on an insulating film or an insulating material such as an insulating substrate, allows easy element isolation, high integration, and high signal transmission speed of the device. Further, active research and development are being conducted because the characteristics can be improved as compared with a conventional semiconductor integrated circuit (IC) or the like in which elements are manufactured on a Si substrate.

As a method for forming a single crystal Si film on the surface of an insulating film, a conventional solid phase epitaxy method (Solid Phase Epi
taxy) is known (Japanese Patent Laid-Open No. Sho 63-192223). FIG. 1 is an explanatory view of a general solid phase epitaxial growth process,
In the figure, 1 indicates a single crystal Si substrate and 2 indicates an insulating film. An insulating film 2 made of SiO ₂ or the like is formed on a single crystal Si substrate 1, the insulating film 2 is selectively etched to form an opening window 3, and a part of the single crystal Si surface is formed in the opening window 3. After exposing, the amorphous Si film 4 is deposited on the entire surface by the vapor deposition method.
By using the exposed Si single crystal as a seed by annealing at a low temperature of about 00 ° C, first in the vertical direction, that is, [100]
Solid phase epitaxial growth (V-SPE) is performed in the azimuth direction, and the solid phase epitaxial growth (L
-SPE) to form an SOI structure.

This method is a low-temperature process, has a high throughput, and can be carried out by using a conventional apparatus, and has a low manufacturing cost, as compared with the conventionally known beam annealing method and SIMOX (Separation by Implanted Oxygen) method. It has features such as.

[0005]

By the way, in the conventional method as described above, in the lateral solid-phase epitaxial growth process, {111} -fasset is grown up to the middle, but {111} -facet is grown from the middle. After that, the growth in {111} frasset gradually became dominant, and thereafter, the amorphous Si film was converted into polysilicon as shown in Fig. 1 (b), and the lateral solid phase epitaxial growth was interrupted. There was a problem that it would end up.

In the case of manufacturing a normal device, if many dislocations are present in the substrate on which the device is prepared, junction leaks and scattering centers will be caused, and device characteristics will be deteriorated. Therefore, dislocations are reduced as much as possible. It is desirable to do. Comparing the case of {110} frasset growth region and the case of {111} frasset growth region in the solid phase epitaxial growth layer, the former dislocation density is about 10 ⁸ / cm ² and the latter dislocation density is maximum. Is about 10 ¹⁰ / cm ^{2 at} maximum, and the dislocation density in the growth region of the former is lower than that of the latter. Therefore, it is desirable to use the {110} -fasset growth region with good crystallinity for the device formation surface, and it is necessary to obtain the {110} -fasset growth region as large as possible in the solid phase epitaxial growth process. To be done.

FIG. 2 is an explanatory diagram when the growth of {110} -fasset is switched to the growth of {111} -facet in the lateral solid-phase epitaxial growth process. As shown in a) {11
Only the growth of 0} asset is generated, but as shown in Fig. 2 (b), {111} asset is partially generated,
After that, as the growth progresses, as shown in Fig. 2 (c), {111
} The number of assets will increase, and finally only growth in {111} assets will occur as shown in Fig. 2 (d). In the conventional method, the lateral solid phase epitaxial growth distance is about 5 μm at 600 ° C., 8 μm at 575 ° C. and 15 μm at 500 ° C., but the lower the temperature, the slower the growth rate. The time required at 500 ℃ is about 45 days, which is unrealistic. Further, in the conventional method, an amorphous Si film is formed by vapor deposition.However, the amorphous Si film formed by this method has poor step coverage with respect to the opening window, and after the film is deposited, Solid phase epitaxial growth must be performed after sintering at ~ 500 ° C.
There was also a problem that the man-hour increased.

The present invention has been made in view of the above circumstances, and its purpose is to delay the generation of {111} flaps in the lateral solid phase epitaxial growth process.
Expanding the {110} -fasset growth region and optimizing the time required for the annealing process based on the solid phase epitaxial growth rate and the final growth distance to improve efficiency.
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can improve the step coverage with respect to an opening window at the time of forming a Si film and omit the baking step, and can significantly improve the throughput.

[0009]

A method for manufacturing a semiconductor device according to the present invention comprises forming an insulating film on a single crystal Si surface and selectively etching the insulating film to expose a part of the single crystal Si surface. After depositing an amorphous Si film with a thickness of 0.5 μm or more by the CVD method over the exposed single crystal Si surface and the insulating film surface,
Characterized in that it includes a step of performing a solid phase epitaxial growth using the exposed Si single crystal as a seed by performing an annealing treatment at a temperature equal to or lower than, and forming the single crystal Si film by single crystallizing the amorphous Si film. To do.

[0010]

According to the present invention, the Si single crystal whose surface is covered with the insulating film except a part thereof and the insulating film are amorphous.
After depositing the Si film to a thickness of 0.5 μm or more, 625 ℃
1} Less dislocation density than Fasset growth region {110
} The area of the fasset growth region becomes large, the annealing time can be greatly shortened, and the throughput can be improved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings. FIG. 3 is an explanatory view showing the main steps of the method for manufacturing a semiconductor device according to the present invention, in which 1 is a single crystal Si substrate and 2 is SiO _2.
An insulating film formed of a film or the like is shown. First, as shown in FIG. 3 (a), a main surface of a single crystal Si substrate 1 having a (100) plane orientation is coated with SiO _{2 of a} predetermined thickness by oxidation treatment of the surface.
A film 2 is formed, and then an opening window 3 is formed by selective etching as shown in FIG. 3 (b).
0) Expose the surface. Such a sample substrate is, for example, RCA
After cleaning by the method, ultra high vacuum C as shown in Fig. 6 to be described later
An amorphous Si film 4 is deposited to a thickness of at least 0.5 μm by the CVD method using a VD device.

Next, such a material substrate is annealed at a temperature of 625 ° C. or less at atmospheric pressure in an N ₂ atmosphere using an electric furnace, for example, and the exposed Si single crystal is used as a seed.
As shown in (d), first, vertical solid phase epitaxial growth is caused along the opening direction of the opening window 3, and then lateral solid phase epitaxial growth is caused to form the single crystal Si film 5.

The reason why the deposited thickness of the amorphous Si film 4 is 0.5 μm or more is as follows. FIG. 4 is a graph showing the relationship between the thickness of an amorphous Si film deposited by a thermal decomposition method using Si ₂ H ₆ (disilane) gas and the {110} -fasset growth distance. The thickness (μm) of the high-quality Si film and the vertical axis represent the {110} -fasset growth distance (μm). As is clear from this graph, the amorphous Si film thickness is 0.5 μ
The growth distance of {110} frasses is substantially constant at m or more, but if the amorphous Si film thickness is less than 0.5 μm, the thinner the amorphous Si film thickness, the shorter the growth distance of {110} frasses. I understand. Therefore, {110} Fasset growth distance (μ
In order to increase m), it is desirable that the amorphous Si film thickness be 0.5 μm or more.

The reason for setting the annealing temperature to 625 ° C. or lower is as follows. FIG. 5 is a graph showing the relationship between the {110} -fasset growth distance and the annealing temperature, with the abscissa representing the annealing temperature (° C.) and the ordinate representing the {110} -fasset growth distance (μm). .. As is clear from this graph, the higher the annealing temperature is above 625 ℃, the shorter the growth distance of {110} fasset, but below 625 ℃, the growth distance of {110} fasset is almost constant and the temperature dependence is almost constant. It turns out that it is not accepted. In addition,
The lower limit of the annealing temperature is not particularly limited, but it is preferably in the range of 625 ° C to 575 ° C considering the growth rate and the maximum growth distance. Therefore, the annealing temperature is 625 ° C.
Hereafter, it is preferably maintained in the range of 625 to 575 ° C.

FIG. 6 is a schematic view of an ultra-high vacuum CVD apparatus which is an apparatus for carrying out the method of the present invention. In the figure, 11 is a growth chamber which is always kept in an ultra-high vacuum state (about 5 × 10 ⁻⁸ Torr). , 12 are load lock chambers, and 13 is a gate valve for connecting and blocking the growth chamber 11 and the load lock chamber 12 from each other. A susceptor holder 14 is provided in the growth chamber 11, and a transfer rod 15 also provided with a susceptor 15a is provided in the load lock chamber 12. The transfer rod 15 is a growth chamber for the sample substrate when the gate valve 13 is open.
It is configured so that it can be transferred onto the susceptor holder 14 in 11 and the sample substrate can be removed from the susceptor holder 14 and taken out to the load lock chamber 12 side.

An infrared lamp 16 is installed outside the growth chamber 11 so as to face the outside of the susceptor holder 14. A controller 17 controls the voltage applied to the infrared lamp 16 and the susceptor holder 14. 18 is a gas supply system for the growth chamber 11, 19 is a gas (N ₂ ) supply system for the load lock chamber 12, and 20 and 21 are gas discharge systems from the growth chamber 11 and the load lock chamber 12, respectively. , 21 are equipped with turbo molecular pumps 20a, 21a and rotary pumps 20b, 21b, respectively.

Next, the operation procedure of such an ultra-vacuum CVD apparatus will be described. First, as shown in FIG. 1 (b), the insulating film 2 is selectively removed by etching to form an opening window 3, and a single crystal is formed.
The sample substrate with a part of the Si substrate 1 exposed is cleaned by the RCA method and then transferred to the transfer rod in the load lock chamber 12.
Set on susceptor 15a at 15. Gas supply system 19
N ₂ gas is supplied from the above, and after purging air, the inside of the load lock chamber 12 is evacuated to about 10 ⁻⁷ Torr by the turbo molecular pump 21 a and the rotary pump 21 b, and then the gate valve 13 is opened and the transfer rod 15 is opened. The sample substrate is advanced into the growth chamber 11 and the sample substrate is transferred onto the susceptor holder 14 in the growth chamber 11. The inside of the growth chamber 11 is constantly evacuated by the turbo molecular pump 20a and the rotary pump 20b to maintain an ultrahigh vacuum.

The infrared lamp 16 is controlled by the controller 17 to raise the temperature of the sample substrate to 500 ° C., the Si ₂ H ₆ gas is introduced from the gas supply system 18 at 100 ccm into the growth chamber 11 for about 10 minutes, Deposition rate: about 500Å / min Thickness as shown in Fig. 1 (c)
An amorphous Si film 4 of 0.5 μm or more is deposited. This amorphous
The thickness of the Si film 4 is set to be the same as the thickness of the single crystal Si layer 6 later.

After the deposition, 100 g of an inert gas such as Ar gas is added.
flow through the growth chamber 11 for 5 minutes, purge the Si ₂ H ₆ gas remaining in the growth chamber 11, lower the substrate temperature to 150 ° C. or less, and use the transfer rod 15 to reverse the setting procedure to set the sample substrate. It is taken out to the load lock chamber 12, and then taken out to the outside. The sample substrate taken out was N ₂ by using an electric furnace.
Annealing is performed at 625 ° C or less at atmospheric pressure in the atmosphere, and first the vertical solid-phase epitaxial growth and then the lateral solid-phase epitaxial growth are performed to produce the single crystal Si film 5 as shown in Fig. 1 (d). To form.

Next, the comparison test results by the method of the present invention and the conventional method will be shown. Figure 7 shows the thickness of the amorphous Si film is 0.2 μm,
This is a graph showing a comparison of lateral solid phase epitaxial growth (L-SPE) distance (μm) when changing to 0.5 μm and 1.5 μm.
Also, the ● marks are the same, and the dotted line shows the case of 0.2 μm. Amorphous as seen from this graph
The method of the present invention in which the thickness of the Si film is 0.5 μm or more is 0.2
Compared with the case of μm, the growth distance is significantly improved,
It is speculated that the {110} asset growth area is also widened accordingly.

FIG. 8 shows annealing temperatures of 590 ° C. and 625, respectively.
This is a graph showing the comparison of the lateral solid phase epitaxial growth (L-SPE) distance (μm) when the temperature is changed to 650 ° C and 650 ° C. In the graph, ○ indicates 625 ℃, ● indicates 590 ℃, and the dotted line indicates 650 ℃.
It shows the case of ° C. As is clear from this graph, the growth distance of the method of the present invention in which the annealing temperature is 625 ° C. or lower is significantly improved as compared with the case of the annealing temperature of 650 ° C., and the {110} fasset growth region is widened accordingly. Presumed to exist.

It was manufactured using the method of the present invention as described above.
As a result of manufacturing an n-type MOSFET on the SOI substrate,
Its field effect mobility is 600 cm ² / (V · sec), and the source-drain leakage current is 0.07 PA / μm, which means that the conductivity type fabricated on a normal bulk is not inferior to that of an n-type MOSFET. Was obtained. Although the above-mentioned embodiment has described the structure in which the insulating film 2 is formed on the single crystal Si substrate 1,
It goes without saying that the insulating film 2 may be formed on the single crystal Si film instead of the single crystal Si substrate 1.

[0023]

As described above, in the method of the present invention, the insulating film is formed with a part of the single crystal Si surface exposed.
After depositing an amorphous Si film with a thickness of 0.5 μm or more on the exposed single crystal Si surface and the insulating film, anneal this at a temperature of 625 ° C or less to perform solid phase growth, and Since the single crystal Si film is formed by single crystallizing the Si film, the area of the growth region with few dislocations can be expanded, the device quality can be improved, the annealing time can be shortened, and the amorphous Since the Si film was formed by the CVD method, it was a single crystal.
The present invention has excellent effects such as excellent coverage with respect to steps around the Si surface, unnecessary baking process after film formation, reduction of man-hours, and faster throughput.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a conventional process for manufacturing a substrate having an SOI structure.

FIG. 2 {11 in the conventional SOI structure substrate manufacturing process.
It is an explanatory view of a process of generating {111} assets from 0} assets.

FIG. 3 is a process explanatory view showing a main manufacturing process according to the present invention.

FIG. 4 is a graph showing the relationship between {110} fasset growth distance and amorphous Si film thickness.

FIG. 5 is a graph showing the relationship between {110} frasset growth distance and annealing temperature.

FIG. 6 is a schematic partially cutaway front view showing an ultra-high vacuum CVD apparatus used in the method of the present invention.

FIG. 7 is a graph showing the relationship between the annealing treatment time and the lateral solid phase epitaxial growth (L-SPE) distance.

FIG. 8 is an explanatory diagram showing a relationship between an annealing treatment time and a lateral solid phase epitaxial growth (L-SPE) distance.

[Explanation of symbols]

 1 Single crystal Si substrate 2 Insulating film 3 Opening window 4 Amorphous Si film 5 Single crystal Si film

Claims (1)

[Claims] 1. An insulating film is formed on a single crystal Si surface, the insulating film is selectively etched to expose a part of the single crystal Si surface, and the exposed single crystal Si surface and the surface of the insulating film are formed by a CVD method. After depositing an amorphous Si film with a thickness of 0.5 μm or more,
Characterized in that it includes a step of performing a solid phase epitaxial growth using the exposed Si single crystal as a seed by performing an annealing treatment at a temperature equal to or lower than, and forming the single crystal Si film by single crystallizing the amorphous Si film. Method for manufacturing semiconductor device.