JP2959810B2 - Pulse width modulation amplifier - Google Patents
Pulse width modulation amplifierInfo
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- JP2959810B2 JP2959810B2 JP2151841A JP15184190A JP2959810B2 JP 2959810 B2 JP2959810 B2 JP 2959810B2 JP 2151841 A JP2151841 A JP 2151841A JP 15184190 A JP15184190 A JP 15184190A JP 2959810 B2 JP2959810 B2 JP 2959810B2
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- voltage
- power supply
- signal
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明はオーディオ再生装置等に用いられるパルス
幅変調（PWM）増幅器に関し、特に復調出力の歪率が改
善されたパルス幅変調増幅器に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation (PWM) amplifier used for an audio reproducing apparatus and the like, and more particularly to a pulse width modulation amplifier with improved distortion rate of demodulated output. is there.
第３図は例えば特開昭60−89109号公報に示された従
来のパルス幅変調増幅器の回路図である。なお、この第
３図は上記公報における従来例のものであるが、この公
報における実施例もこの従来回路を用いており、後述す
る問題点を解決するものではないので、ここでは第３図
の従来例で説明する。第３図において、１は増幅すべき
音楽信号などの入力信号、２は入力信号１をパルス幅変
調するためのキャリア信号を発生するキャリア発生回
路、３は入力信号１と上記キャリヤ信号との電圧比較を
行う電圧比較器、４は電圧比較器３の出力により下記パ
ワースイッチング素子をON/OFFさせるスイッチ駆動回
路、５はパワースイッチング素子素子としてのＮチャネ
ルMOS型FET、６はパワースイッチング素子としてのＰチ
ャネルMOS型FET、７は復調出力を得るローパスフィル
タ、８は復調出力を音声化するスピーカである。FIG. 3 is a circuit diagram of a conventional pulse width modulation amplifier disclosed in, for example, JP-A-60-89109. Although FIG. 3 is a conventional example in the above-mentioned publication, the embodiment in this publication also uses this conventional circuit and does not solve the problems described later. A description will be given of a conventional example. In FIG. 3, 1 is an input signal such as a music signal to be amplified, 2 is a carrier generation circuit for generating a carrier signal for pulse width modulation of the input signal 1, and 3 is a voltage between the input signal 1 and the carrier signal. A voltage comparator for comparison, 4 is a switch drive circuit for turning on / off the following power switching element by the output of the voltage comparator 3, 5 is an N-channel MOS FET as a power switching element, and 6 is a power switching element. A P-channel MOS FET, 7 is a low-pass filter for obtaining a demodulated output, and 8 is a speaker for converting the demodulated output into audio.
次にこの従来例の動作について説明する。第４図に示
すように入力信号ei（１）とキャリア発生回路２からの
キャリア信号ecとを電圧比較器３で比較して、その電圧
比較器３の出力に入力信号eiのレベルに比例したPWM信
号esを得て、このPWM信号でスイッチ駆動回路４を駆動
させる。スイッチ駆動回路４はFET5,6をON/OFFし、FET
5,6の接続点からは電力変換されたPWM信号es′を得る。
このPWM信号es′をローパスフィルタ７に通すことによ
り、キャリア信号ecが取り除かれた入力信号eiとほぼ同
等な復調出力e0を得る。Next, the operation of this conventional example will be described. As shown in FIG. 4, the input signal e i (1) and the carrier signal e c from the carrier generation circuit 2 are compared by the voltage comparator 3 and the output of the voltage comparator 3 is the level of the input signal e i . to obtain a PWM signal e s proportional to drives the switch driving circuit 4 in the PWM signal. The switch drive circuit 4 turns ON / OFF the FETs 5 and 6, and the FET
From the connection points 5 and 6, a power-converted PWM signal e s ′ is obtained.
By passing this PWM signal e s ' through the low-pass filter 7, a demodulated output e 0 substantially equal to the input signal e i from which the carrier signal e c has been removed is obtained.
従来のパルス幅変調増幅器は以上のように構成されて
いるので、例えば平均出力電圧が小さくても瞬時電圧が
大きい鐘やドラムの音や爆破音などが含まれる音楽信号
（入力信号ei）の振幅は、キャリア信号ecの振幅より大
きくなることがあり、次のような問題点があった。即
ち、第５図に示すように入力信号eiの方がキャリア信号
ecの振幅より大きくなると、PWM信号のパルス幅は入力
信号eiの振幅に比例せずキャリア信号の同期と同じ幅で
一定値になりPWM信号の振幅は入力信号eiの振幅がキャ
リア信号ecの振幅より小さい場合と同様にハイレベルあ
るいはローレベルになり、このため復調出力eoは電源電
圧でクリップされてしまうという問題点があった。Since the conventional pulse width modulation amplifier is configured as described above, for example, a music signal (input signal e i ) including a bell, a drum sound, a blast sound, and the like having a large instantaneous voltage even though the average output voltage is small. amplitude can be larger than the amplitude of the carrier signal e c, there are the following problems. That is, as shown in FIG. 5, the input signal e i is the carrier signal.
becomes greater than the amplitude of e c, the pulse width of the PWM signal amplitude of the PWM signal becomes a constant value in the same width as the synchronization of the carrier signal not proportional to the amplitude of the input signal e i is the input signal e i amplitude carrier signal There is a problem that the demodulated output eo is clipped by the power supply voltage, as in the case where the amplitude is smaller than the amplitude of e c , which becomes high level or low level.
この発明は上記のような問題点を解決するためになさ
れたもので、瞬時電圧が大きい音楽信号などの入力信号
に対しても、クリップされることなく復調出力を得るこ
とができるパルス幅変調増幅器を提供することを目的と
する。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a pulse width modulation amplifier capable of obtaining a demodulated output without clipping even for an input signal such as a music signal having a large instantaneous voltage. The purpose is to provide.
この発明に係るパルス幅変調増幅器は、増幅すべき入
力信号をパルス幅変調する変調回路16と、この変調回路
16でパルス幅変調された変調信号から復調出力を得る復
調回路（ローパスフィルタ７）と、上記入力信号の瞬時
値又は上記復調回路（ローパスフィルタ７）の出力信号
の瞬時値を検出するレベル検出回路18と、上記変調回路
16の前段に設けられ上記レベル検出回路18の出力レベル
に応じて利得が変わる前置増幅回路15と、上記レベル検
出回路18の出力レベルが所定値より小さい場合に上記変
調回路16の出力段素子（FET5あるいは６）に電源（31あ
るいは32）を接続するとともに上記出力段素子への出力
端子（35あるいは36）とグランド間にコンデンサ（33あ
るいは34）を接続して該コンデンサに充電を行わせ、か
つ、上記レベル検出回路の出力レベルが所定値より大き
い場合に上記充電されたコンデンサのグランド側（33の
−側あるいは34の＋側）に接続された端子を上記電源に
接続して上記出力段素子への電源電圧を変える電源電圧
可変回路17とを備えたものである。A pulse width modulation amplifier according to the present invention includes a modulation circuit 16 for pulse width modulation of an input signal to be amplified, and a modulation circuit
A demodulation circuit (low-pass filter 7) for obtaining a demodulated output from the modulated signal pulse-width modulated by 16, and a level detection circuit for detecting the instantaneous value of the input signal or the instantaneous value of the output signal of the demodulation circuit (low-pass filter 7) 18 and the above modulation circuit
A preamplifier circuit 15 provided before the stage 16 and having a gain that changes according to the output level of the level detection circuit 18, and an output stage element of the modulation circuit 16 when the output level of the level detection circuit 18 is smaller than a predetermined value. A power supply (31 or 32) is connected to (FET5 or 6) and a capacitor (33 or 34) is connected between the output terminal (35 or 36) to the output stage element and the ground to charge the capacitor. And when the output level of the level detection circuit is higher than a predetermined value, a terminal connected to the ground side (-side of 33 or + side of 34) of the charged capacitor is connected to the power supply and the output is output. And a power supply voltage variable circuit 17 for changing a power supply voltage to the stage element.
変調回路16は増幅すべき入力信号をパルス幅変調す
る。復調回路（ローパスフィルタ７）は変調回路16でパ
ルス幅変調された変調信号から復調出力を得る。レベル
検出回路18は上記入力信号の瞬時値あるいは上記復調回
路の出力信号の瞬時値を検出する。前置増幅回路15はレ
ベル検出回路18の出力レベルに応じて利得が変わる。電
源電圧可変回路17はレベル検出回路18の出力レベルに応
じて変調回路16の出力段素子（FET5,6）への電源電圧を
変える。即ち、電源電圧可変回路17は、入力信号が小さ
いときにはコンデンサが電源に並列接続されて充電さ
れ、入力信号が大きいときは充電したコンデンサを電源
に直列に挿入して出力段素子へ供給する電圧値を高くす
る。The modulation circuit 16 performs pulse width modulation on an input signal to be amplified. The demodulation circuit (low-pass filter 7) obtains a demodulated output from the modulated signal pulse-width modulated by the modulation circuit 16. The level detection circuit 18 detects the instantaneous value of the input signal or the instantaneous value of the output signal of the demodulation circuit. The gain of the preamplifier circuit 15 changes according to the output level of the level detection circuit 18. The power supply voltage variable circuit 17 changes the power supply voltage to the output stage elements (FETs 5 and 6) of the modulation circuit 16 according to the output level of the level detection circuit 18. That is, when the input signal is small, the capacitor is connected in parallel to the power supply and charged, and when the input signal is large, the charged voltage is inserted in series with the power supply and supplied to the output stage element. Higher.
第１図はこの発明の一実施例によるパルス幅変調増幅
器の回路図である。第１図において、変調回路16は増幅
すべき入力信号（音楽信号）１をパルス幅変調するもの
で、前述したようにキャリア発生回路２、電圧比較器
３、スイッチ駆動回路４、及びFET5,6を備えている。ロ
ーパスフィルタ７は変調回路16でパルス幅変調された変
調信号から復調出力を得る復調回路である。スピーカ８
は上記復調出力を音声化するものである。電圧レベル検
出回路18は上記入力信号１の瞬時電圧値を検出するもの
で、整流用ダイオード18a〜18d、抵抗20a〜20d、差動増
幅器20,21、及び直流電圧源19を備えている。前置増幅
回路15は変調回路16の前段に設けられ電圧レベル検出回
路18の出力レベルに応じて利得が変わるもので、抵抗10
〜13、差動増幅器９、及びＮチャネルMOS型FET14を備え
ている。この前置増幅回路15はこの実施例の場合２つの
電圧利得をとる。抵抗11は入力信号１に接続されてい
る。R1は抵抗12の抵抗値、（ｎ−１）R1は抵抗11の抵抗
値、R2は抵抗13の抵抗値、R3は抵抗10の抵抗値を示す。
電源電圧可変回路17は電圧レベル検出回路18の出力レベ
ルに応じて変調回路16の出力段素子であるFET5,6への電
源電圧を変えるものである。電源電圧可変回路17におい
て、Vccは電源電圧であり、ｎ＝２の場合の詳細な回路
図を第２図に示す。第２図において、22は電圧レベル検
出回路18の差動増幅器21の出力端子に接続される制御信
号入力端子、38は入力端子22に接続されるＮチャネルMO
S形FET、23,24は抵抗、25はＰチャネルMOS形FET27とＮ
チャネルMOS形FET28を駆動させる駆動回路、26はＰチャ
ネルMOS型FET29とＮチャネルMOS型FET30を駆動させる駆
動回路、39,40はダイオード、31,32は直流電源、33,34
はコンデンサ、35は変調回路16のFET5に接続される出力
端子、36は変調回路16のFET6に接続される出力端子であ
る。FIG. 1 is a circuit diagram of a pulse width modulation amplifier according to one embodiment of the present invention. In FIG. 1, a modulation circuit 16 performs pulse width modulation of an input signal (music signal) 1 to be amplified. As described above, a carrier generation circuit 2, a voltage comparator 3, a switch driving circuit 4, and FETs 5 and 6 are provided. It has. The low-pass filter 7 is a demodulation circuit that obtains a demodulated output from a modulated signal that has been pulse width modulated by the modulation circuit 16. Speaker 8
Is for converting the demodulated output into audio. The voltage level detecting circuit 18 detects the instantaneous voltage value of the input signal 1 and includes rectifying diodes 18a to 18d, resistors 20a to 20d, differential amplifiers 20 and 21, and a DC voltage source 19. The preamplifier circuit 15 is provided before the modulation circuit 16 and changes the gain in accordance with the output level of the voltage level detection circuit 18.
13, a differential amplifier 9, and an N-channel MOS FET 14. The preamplifier circuit 15 has two voltage gains in this embodiment. The resistor 11 is connected to the input signal 1. Resistance of R 1 is the resistance 12, showing the resistance value of the (n-1) R 1 is the resistance 11, the resistance value of R 2 is the resistance 13, the resistance value of R 3 is resistor 10.
The power supply voltage variable circuit 17 changes the power supply voltage to the FETs 5 and 6 which are the output stage elements of the modulation circuit 16 according to the output level of the voltage level detection circuit 18. In the power supply voltage variable circuit 17, Vcc is a power supply voltage, and a detailed circuit diagram when n = 2 is shown in FIG. 2, reference numeral 22 denotes a control signal input terminal connected to the output terminal of the differential amplifier 21 of the voltage level detection circuit 18, and reference numeral 38 denotes an N-channel MO connected to the input terminal 22.
S-type FETs, 23 and 24 are resistors, 25 is P-channel MOS FET 27 and N
A driving circuit for driving the channel MOS FET 28, a driving circuit 26 for driving the P-channel MOS FET 29 and the N-channel MOS FET 30, diodes 39 and 40, DC power supplies 31 and 32, 33 and 34
Is a capacitor, 35 is an output terminal connected to the FET 5 of the modulation circuit 16, and 36 is an output terminal connected to the FET 6 of the modulation circuit 16.
次にこの実施例の動作について説明する。前置増幅回
路15は、例えば２つの電圧利得A1とA2を切り換えて用
い、A1＞A2の関係がある。電圧利得A1とA2の切り換え
は、入力信号としての音楽信号をei,キャリア信号の振
幅をEcとしたときei×A1＜Ecのとき電圧利得A1に切り換
り,ei×A1≧Ecのとき電圧利得A2に切り換る。ここで、
変調回路16に入力される音楽信号eiがキャリア信号の振
幅Ecより大きくならないように電圧利得A2を決めるとPW
M信号のパルス幅に常に音楽信号eiに比例する。Next, the operation of this embodiment will be described. Preamplifier circuit 15, for example using switching two voltage gain A 1 and A 2, A 1> a relationship of A 2. Switching of the voltage gain A 1 and A 2 are cut music signal as an input signal e i, the voltage gain A 1 when e i × A 1 <E c when the amplitude of the carrier signal is a E c換Ri, When e i × A 1 ≧ E c , switch to voltage gain A 2 . here,
PW the music signal e i that is input to the modulation circuit 16 determines the voltage gain A 2 so as not to be greater than the amplitude E c of the carrier signal
The pulse width of the M signal is always proportional to the music signal e i .
ここで、PWM（パルス幅変調）増幅器の電圧利得につ
いて考える。PWM増幅器出力段スイッチ素子（変調回路1
6のFET5,6）のPWM信号の振幅をEs′とすればPWM増幅器
の電圧利得は第（１）式で示せる。Here, consider the voltage gain of a PWM (pulse width modulation) amplifier. PWM amplifier output stage switch element (modulation circuit 1
Assuming that the amplitude of the PWM signal of the FETs 5 and 6) is E s ′, the voltage gain of the PWM amplifier can be expressed by the following equation (1).
このPWM増幅器をオーディオ用アンプとして用いる場
合、G1＝G2でなければならない。しかし、A1≠A2かつ
Es′が一定のため、G1≠G2である。そこで、G1＝G2にな
るようにE3を切り換える。出力段のPWM信号は電源電圧
まで振れるので電源電圧がEs′になる。前置増幅回路15
の電圧利得がA1のときの電源電圧をVcc1,前置増幅回路1
5の電圧利得がA2のときの電源電圧をVcc2とすればG1＝G
2と置くことにより、次の第（２）式の関係を満足させ
ればよいことがわかる。 When this PWM amplifier is used as an audio amplifier, G1 must be equal to G2. However, A 1 ≠ A 2 and
Since E s ′ is constant, G1 ≠ G2. Therefore, switching the E 3 so that G1 = G2. Since the PWM signal of the output stage swings up to the power supply voltage, the power supply voltage becomes E s '. Preamplifier circuit 15
Voltage gain of the power source voltage when the A 1 V cc1, preamplifier 1
If the voltage gain of 5 to the power supply voltage when the A 2 and V cc2 G1 = G
It can be seen that setting the value to 2 satisfies the relationship of the following equation (2).
A1×Vcc1＝A2×Vcc2 …（２） 以上のようにA1×ei＞EcのときA2×ei＜Ecを満すA2に
切り換え、第（２）式を満す電源電圧Vcc2に切り変える
ことにより、クリップによる復調出力の歪をなくするこ
とができる。 A 1 × V cc1 = A 2 × V cc2 ... (2) As described above A 1 × e i> switches the A 2 × e i <E c when E c fully to be A 2, the (2) by changing cut the full to the supply voltage V cc2, it can be eliminated distortion of the demodulated output by the clip.
更にこのような動作について詳しく説明する。 Further, such an operation will be described in detail.
入力信号（音楽信号）１の電圧レベルが所定レベルよ
り小さいとき、電圧レベル検出回路18内の差動増幅器20
の出力電圧の大きさは直流電源19の電圧Vsよりも小さ
い。よって、差動増幅器21の出力電圧はローレベルであ
る。そのため前置増幅回路15内のＮチャネルMOS型FET14
のゲート電圧はローレベルであり、スイッチとしてはOF
F状態として働く。よってこのとき前置増幅回路15の電
圧利得A1は次の第（３）式で示せる。When the voltage level of the input signal (music signal) 1 is smaller than a predetermined level, the differential amplifier 20 in the voltage level detection circuit 18
The magnitude of the output voltage is less than the voltage V s of the DC power supply 19. Therefore, the output voltage of the differential amplifier 21 is at a low level. Therefore, the N-channel MOS FET 14 in the preamplifier 15
Gate voltage is low level and the switch is OF
Works as F state. Therefore the voltage gain A 1 In this case the preamplifier circuit 15 can show in the equation (3) below.
ここでR2＞＞R1に選べば第（３）式は第（４）式で近
似できる。 Here, if R 2 >> R 1 is selected, Expression (3) can be approximated by Expression (4).
また、差動増幅器21の出力がローレベルのとき電源電
圧可変回路17は、±Vccの値をとる。このときの第
（２）式の左辺A1×Vcc1は、第（４）式とVcc1＝2Vccよ
り となる。 When the output of the differential amplifier 21 is at a low level, the power supply voltage variable circuit 17 takes a value of ± Vcc . At this time, the left side A 1 × V cc1 of the expression (2) is obtained from the expression (4) and V cc1 = 2V cc . Becomes
次に入力信号（音楽信号）１の電圧レベルが大きくな
ると差動増幅器20の出力電圧が大きくなり、ついにはキ
ャリア信号の振幅よりも大きくなる。Vs＝Ecに設定すれ
ば、このとき差動増幅器21の出力電圧はハイレベルにな
り、ＮチャネルMOS型FET14のゲート電圧がハイレベルに
なり、スイッチとしてON状態で働く。このため抵抗12は
アースに接続され、入力信号（音楽信号）１はR1＜＜R2
とすれば、抵抗11と抵抗12により分圧されて抵抗13に入
力される。このため前置増幅回路15の電圧利得A2は第
（６）式で示せる。Next, when the voltage level of the input signal (music signal) 1 increases, the output voltage of the differential amplifier 20 increases, and eventually becomes larger than the amplitude of the carrier signal. Is set to V s = E c, this time the output voltage of the differential amplifier 21 goes high, the gate voltage of the N-channel MOS type FET14 becomes high level, working in the ON state as a switch. Therefore, the resistor 12 is connected to the ground, and the input signal (music signal) 1 is R 1 << R 2
In this case, the voltage is divided by the resistors 11 and 12 and input to the resistor 13. Therefore the voltage gain A 2 of the preamplifier circuit 15 can show in equation (6).
また、差動増幅器21の出力電圧がハイレベルになる
と、前置増幅回路15の電圧利得がA1からA2に変わると同
時に、電源電圧可変回路17のスイッチが切換りFET5と６
に接続された直流電圧源が±nVccの値をとるのでVcc2＝
2nVccである。このとき第（２）式の右辺A2×Vcc2は、V
cc2＝2nVccと第（６）式より第（７）式で示せる。 When the output voltage of the differential amplifier 21 becomes a high level, before the voltage gain of the amplifier circuit 15 is changed from A 1 to A 2 at the same time, switch on the power voltage variable circuit 17 Setsu換Ri FET5 6
Takes a value of ± nV cc , so that V cc2 =
2 nV cc . At this time, A 2 × V cc2 on the right side of equation (2) is V
cc2 = 2nV cc and the (6) first from the equation (7) can show in equation.
よって第（５）式と第（７）式から第１図の回路は、
第（２）式を満足している。 Therefore, from the equations (5) and (7), the circuit of FIG.
The formula (2) is satisfied.
次に第１図の電源電圧可変回路17でｎ＝２の場合につ
いて説明する。第１図の差動増幅器21の出力は第２図の
制御信号入力端子22に接続されている。制御信号入力端
子22にローレベルの電圧が入っていると、ＮチャネルMO
S型FET38はOFF状態になるので抵抗23と24で電圧降下が
生じない。ここで、駆動回路25と26は、例えば非反転増
幅器を用いるとする。駆動回路25の入力はハイレベルな
ので、出力はハイレベルとなり、ＰチャネルMOS型FET27
はOFF状態に、ＮチャネルMOS型FET28はON状態になり、
コンデンサ33はマイナス端子がアース電位になる。この
ときコンデンサ33は、直流電源31によりダイオード39を
通してほぼ電圧Vccに充電される。。このとき出力端子3
5の電圧はVccになる。また駆動回路26の入力はローレベ
ルになるので、出力電圧はローレベルになりＰチャネル
MOS型FET29はON状態に、ＮチャネルMOS型FET30はOFF状
態になり、コンデンサ34はプラス端子がやはりアース電
位になる。このときコンデンサ34は直流電源32によりダ
イオード40を通してほぼ電圧Vccに充電される。このと
き出力端子36の電圧は−Vccになる。Next, the case where n = 2 in the power supply voltage variable circuit 17 of FIG. 1 will be described. The output of the differential amplifier 21 of FIG. 1 is connected to the control signal input terminal 22 of FIG. When a low level voltage is applied to the control signal input terminal 22, the N-channel MO
Since the S-type FET 38 is turned off, no voltage drop occurs at the resistors 23 and 24. Here, it is assumed that the drive circuits 25 and 26 use, for example, non-inverting amplifiers. Since the input of the drive circuit 25 is at a high level, the output is at a high level and the P-channel MOS FET 27
Is in the OFF state, the N-channel MOS FET 28 is in the ON state,
The negative terminal of the capacitor 33 has the ground potential. At this time capacitor 33 is charged to approximately voltage V cc through the diode 39 by the DC power supply 31. . At this time, output terminal 3
The voltage of 5 becomes Vcc . Also, since the input of the drive circuit 26 is at a low level, the output voltage is at a low level and the P-channel
The MOS FET 29 is turned on, the N-channel MOS FET 30 is turned off, and the positive terminal of the capacitor 34 is also at the ground potential. At this time, the capacitor 34 is charged by the DC power supply 32 to approximately the voltage Vcc through the diode 40. The voltage of the output terminal 36 this time is -V cc.
次に制御信号入力端子22にハイレベル信号が入るとＮ
チャネルMOS型FET38はON状態になり、抵抗23と24はアー
ス電位になる。駆動回路25にはローレベルの信号に入力
されるので出力はローレベルになり、ＰチャネルMOS型F
ET27はON状態に、ＮチャネルMOS型FET28はOFF状態にな
るため、コンデンサ33の−側が直流電源31の＋側に接続
される。このときコンデンサ33は電圧Vccの直流電源と
考えられるので電圧Vccの直流電源が２つ直列に接続さ
れたのと同じであるから、出力端子35には2Vccの電圧が
生じる。このときダイオード39は逆バイアスになってい
るので、コンデンサ33は直流電源31に電流を流し込まな
い。Next, when a high level signal is input to the control signal input terminal 22, N
The channel MOS FET 38 is turned on, and the resistors 23 and 24 are set to the ground potential. Since the driving circuit 25 receives a low-level signal, the output becomes low, and the P-channel MOS type F
Since the ET 27 is turned on and the N-channel MOS FET 28 is turned off, the negative side of the capacitor 33 is connected to the positive side of the DC power supply 31. Since this time the capacitor 33 is the same as the DC power supply voltage V cc it is considered that the DC power supply voltage V cc is connected to two series, resulting the voltage of 2V cc to the output terminal 35. At this time, since the diode 39 is reverse-biased, the capacitor 33 does not supply current to the DC power supply 31.
また駆動回路26の入力がハイレベルなので出力はハイ
レベルであり、ＰチャネルMOS型FET29はOFF状態に、Ｎ
チャネルMOS型FET30はON状態になるので、コンデンサ34
の＋側は直流電源32の−側に接続される。コンデンサ34
を電圧Vccの直流電源と考えられるので、Vccの電圧源が
２つ直列に接続されたのと同じであるから、出力端子36
には−2Vccの電圧が生じる。このときダイオード40は逆
バイアスなので、コンデンサ34は直流電源32に電流を流
し込まない。このような動作により得られた出力端子3
5,36の電圧は、変調回路16のFET5,6に与えられ、FET5,6
の電源電圧として作用する。Also, since the input of the drive circuit 26 is at a high level, the output is at a high level.
Since the channel MOS FET 30 is turned on, the capacitor 34
Is connected to the negative side of the DC power supply 32. Capacitor 34
The it is considered that the DC power supply voltage V cc, because the voltage source V cc is the same as that connected to the two series, the output terminal 36
Generates a voltage of -2 Vcc . At this time, since the diode 40 is reverse-biased, the capacitor 34 does not supply current to the DC power supply 32. Output terminal 3 obtained by such operation
The voltage of 5,36 is supplied to the FETs 5,6 of the modulation circuit 16 and the FETs 5,6
Acts as the power supply voltage for
以上説明したように、この実施例のパルス幅変調増幅
器は、入力信号１の瞬時電圧値を電圧レベル検出回路18
で検出し、入力信号１の瞬時電圧値が電源電圧の大きさ
になると、前置増幅回路15の電圧利得を小さくすると同
時に、変調回路16のFET5,6に接続された電源電圧を昇圧
して電源電圧以上の電源電圧を出せるようにし、また入
力信号１の瞬時電圧値が昇圧する前の電源電圧の大きさ
よりも小さくなると、前置増幅回路15の電圧利得と電源
電圧を元に戻すように動作する。なお、上記実施例では
電圧レベル検出回路18の入力を入力信号（音楽信号）１
に接続したがローパスフィルタ７の出力端子、即ちパル
ス幅変調増幅器の出力端子に接続してもよい。このと
き、電圧レベル検出回路18内の直流電源19はVs＝Vccに
設定する。As described above, the pulse width modulation amplifier of this embodiment uses the instantaneous voltage value of the input signal 1 as the voltage level detection circuit 18.
When the instantaneous voltage value of the input signal 1 becomes the magnitude of the power supply voltage, the voltage gain of the preamplifier circuit 15 is reduced, and at the same time, the power supply voltage connected to the FETs 5 and 6 of the modulation circuit 16 is boosted. A power supply voltage higher than the power supply voltage can be output, and when the instantaneous voltage value of the input signal 1 becomes smaller than the power supply voltage before boosting, the voltage gain and the power supply voltage of the preamplifier circuit 15 are restored. Operate. In the above embodiment, the input of the voltage level detection circuit 18 is the input signal (music signal) 1
May be connected to the output terminal of the low-pass filter 7, that is, the output terminal of the pulse width modulation amplifier. At this time, the DC power source 19 in the voltage level detection circuit 18 is set to V s = V cc.
以上のように本発明によれば、入力信号の瞬時値ある
いは復調回路の出力信号の瞬時値を検出するレベル検出
回路と、このレベル検出回路の出力レベルに応じて利得
が変わる前置増幅回路と、上記レベル検出回路の出力レ
ベルに応じて変調回路の出力段素子への電源電圧を変え
る電源電圧可変回路とを設けて構成したので、音楽信号
などの入力信号が変調回路のキャリア信号より相対的に
大きくなることがなくなり、これにより復調出力がクリ
ップされずに、復調出力の歪率が少なくなり、精度の高
い音声などを出力できるという効果が得られるととも
に、１つの電源で駆動回路の電源電圧を可変できる構成
としたので、複数の電源は必要なく、回路構成が簡単に
なり、IC化に適したパルス幅変調増幅器が得られる。As described above, according to the present invention, a level detection circuit that detects an instantaneous value of an input signal or an instantaneous value of an output signal of a demodulation circuit, a preamplifier circuit whose gain changes according to the output level of the level detection circuit, And a power supply voltage variable circuit that changes the power supply voltage to the output stage element of the modulation circuit in accordance with the output level of the level detection circuit, so that an input signal such as a music signal is relative to a carrier signal of the modulation circuit. As a result, the demodulated output is not clipped, the distortion rate of the demodulated output is reduced, and the effect of outputting high-precision audio and the like is obtained. Is variable, a plurality of power supplies are not required, the circuit configuration is simplified, and a pulse width modulation amplifier suitable for IC integration can be obtained.
第１図はこの発明の一実施例によるパルス幅変調増幅器
の回路図、第２図は第１図中の電源電圧可変回路の詳細
な回路図、第３図は従来のパルス幅変調増幅器の回路
図、第４図（ａ）〜（ｃ）は第３図の回路の動作を説明
するための信号波形図、第５図（ａ）〜（ｃ）は第３図
の回路でクリップを生じる場合の信号波形図である。 １……入力信号、７……ローパスフィルタ（復調回
路）、15……前置増幅回路、16……変調回路、17……電
源電圧可変回路、18……電圧レベル検出回路。FIG. 1 is a circuit diagram of a pulse width modulation amplifier according to an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of a power supply voltage variable circuit in FIG. 1, and FIG. 3 is a circuit of a conventional pulse width modulation amplifier. FIGS. 4 (a) to 4 (c) are signal waveform diagrams for explaining the operation of the circuit of FIG. 3, and FIGS. 5 (a) to 5 (c) show the case where clipping occurs in the circuit of FIG. 3 is a signal waveform diagram of FIG. 1 ... input signal, 7 ... low-pass filter (demodulation circuit), 15 ... preamplifier circuit, 16 ... modulation circuit, 17 ... power supply voltage variable circuit, 18 ... voltage level detection circuit.
フロントページの続き (56)参考文献 特開 昭56−131210（ＪＰ，Ａ) 特開 昭58−84509（ＪＰ，Ａ) 特開 昭59−17710（ＪＰ，Ａ) 特開 昭60−89109（ＪＰ，Ａ) 特開 昭62−60306（ＪＰ，Ａ) 特開 昭62−274906（ＪＰ，Ａ) 特開 平２−164113（ＪＰ，Ａ) 実開 昭56−87719（ＪＰ，Ｕ) 欧州特許出願公開32335（ＥＰ，Ａ１) (58)調査した分野(Int.Cl.6，ＤＢ名) H03F 1/32 H03F 3/217 H03G 3/30 Continuation of the front page (56) References JP-A-56-131210 (JP, A) JP-A-58-84509 (JP, A) JP-A-59-17710 (JP, A) JP-A-60-89109 (JP, A) , A) JP-A-62-60306 (JP, A) JP-A-62-274906 (JP, A) JP-A-2-164113 (JP, A) Japanese Utility Model Application No. 56-87719 (JP, U) European patent application Published 32335 (EP, A1) (58) Fields investigated (Int. Cl. 6 , DB name) H03F 1/32 H03F 3/217 H03G 3/30
Claims (1)
調回路と、この変調回路でパルス幅変調された変調信号
から復調出力を得る復調回路とを備えたパルス幅変調増
幅器において、 上記入力信号の瞬時値又は上記復調回路の出力信号の瞬
時値を検出するレベル検出回路と、 上記変調回路の前段に設けられ上記レベル検出回路の出
力レベルに応じて利得が変わる前置増幅回路と、 上記レベル検出回路の出力レベルが所定値より小さい場
合に上記変調回路の出力段素子に電源を接続するととも
に上記出力段素子への出力端子とグランド間にコンデン
サを接続して該コンデンサに充電を行わせ、かつ、上記
レベル検出回路の出力レベルが所定値より大きい場合に
上記充電されたコンデンサのグランド側に接続された端
子を上記電源に接続して上記出力段素子への電源電圧を
変える電源電圧可変回路とを設けたことを特徴とするパ
ルス幅変調増幅器。1. A pulse width modulation amplifier comprising: a modulation circuit for pulse width modulating an input signal to be amplified; and a demodulation circuit for obtaining a demodulated output from a modulation signal pulse width modulated by the modulation circuit. A level detection circuit that detects an instantaneous value of the demodulation circuit or an instantaneous value of an output signal of the demodulation circuit; a preamplifier circuit provided before the modulation circuit, the gain of which changes according to the output level of the level detection circuit; When the output level of the detection circuit is smaller than a predetermined value, a power supply is connected to the output stage element of the modulation circuit, and a capacitor is connected between the output terminal to the output stage element and ground, and the capacitor is charged, When the output level of the level detection circuit is higher than a predetermined value, a terminal connected to the ground side of the charged capacitor is connected to the power supply. Pulse width modulation amplifier, characterized in that a power supply voltage variable circuit for changing a power supply voltage to the output stage element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2151841A JP2959810B2 (en) | 1990-06-11 | 1990-06-11 | Pulse width modulation amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2151841A JP2959810B2 (en) | 1990-06-11 | 1990-06-11 | Pulse width modulation amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0443706A JPH0443706A (en) | 1992-02-13 |
| JP2959810B2 true JP2959810B2 (en) | 1999-10-06 |
Family
ID=15527462
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2151841A Expired - Fee Related JP2959810B2 (en) | 1990-06-11 | 1990-06-11 | Pulse width modulation amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2959810B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100704859B1 (en) * | 1998-11-12 | 2007-04-09 | 래리 키른 | Multi-reference, high-accuracy switching amplifier |
| JP2003051724A (en) * | 2001-08-08 | 2003-02-21 | Sony Corp | Digital power amplifier and digital/analog converter |
| JP2009049671A (en) * | 2007-08-20 | 2009-03-05 | Rohm Co Ltd | Output-limiting circuit, class d power amplifier, sound apparatus |
| TWI339008B (en) * | 2007-12-05 | 2011-03-11 | Ite Tech Inc | Class-d amplifier and multi-level output signal generated method thereof |
| JP5444795B2 (en) * | 2008-07-29 | 2014-03-19 | 株式会社リコー | Image reading apparatus, image forming apparatus, amplitude adjusting method, and computer program |
| WO2011001591A1 (en) * | 2009-06-29 | 2011-01-06 | パナソニック株式会社 | Class d amplification device |
| JP5291572B2 (en) * | 2009-08-18 | 2013-09-18 | 株式会社アドバンテスト | Power supply device, test device, and control method |
| CN102656799B (en) * | 2009-10-19 | 2016-01-13 | 麦耶声音实验室股份有限公司 | For reducing circuit and the method for the noise of D audio frequency amplifier |
| CN115107552A (en) * | 2022-06-17 | 2022-09-27 | 广州南方电力集团科技发展有限公司 | Charging connection state detection method and system of charging device |
-
1990
- 1990-06-11 JP JP2151841A patent/JP2959810B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0443706A (en) | 1992-02-13 |
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