JP2956921B2 - Mark rate 1/2 pattern regenerator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention, for example, used to measure the error rate, the mark ratio is from pattern <br/> emissions of 1/2 ^n, reproduces the pseudo-random pattern corresponding thereto mark It relates to a rate 1/2 pattern regenerator.

[0002]

2. Description of the Related Art FIG . 9 shows a conventional error rate detector. Input data from the terminal 11 is supplied to one terminal of the exclusive OR circuit 12. A clock synchronized with the input data from the clock terminal 13 is supplied to the pattern generator 15 through the skip circuit 14. This pattern generator 15
, A reference pattern synchronized with the input clock is generated. At the same time, the clock
Counted at 6. The reference pattern from the pattern generator 15 is supplied to the other input terminal of the exclusive OR circuit 12, so that the exclusive OR circuit 12 outputs a logical 1 when the input pattern does not match the reference pattern. The output of the exclusive OR circuit 12 is supplied to the synchronization control circuit 17. The synchronization control circuit 17 operates in synchronization with the input clock of the pattern generator 15, and is reset and activated by an activation signal from the terminal 18. Exclusive OR circuit 12
When the number of inconsistencies from the data reaches a predetermined number, the synchronization control circuit 1
A reset signal is output from a terminal 19 of the counter 7 to reset the counter 16 and control the skip circuit 14 to block one clock or apply one more pulse. Thereby, the phase of the pattern generated from the pattern generator 15 is shifted by one bit. In this way, the phase of the pattern generated by the pattern generator 15 is sequentially shifted until the input pattern matches the reference pattern of the pattern generator 15 .

The pattern generator 15 usually includes a pseudo-random pattern generator constructed by feeding back the exclusive OR of the last stage and intermediate stages of the shift register and each output to the input side. In the case of 1/2, the output pattern of the pseudo-random pattern generator is directly used as the reference pattern, and when the mark rate is not 1/2, for example, 1
In the case of / 4, a logical product of sequentially adjacent bits of the generated pseudo-random pattern is taken as a reference pattern having a mark rate of 1/4. Pattern generator 1 when mark rate is 1/2
If the number of the down-shifting the pseudo random pattern generator 5 is n-stage, n times if the successive error free in state is detected, a reference pattern is <br/> synchronized with an input pattern that occurred It will be in the state of having done.

[0004]

As described above, the reference pattern synchronized with the input pattern is generated, and the error rate of the input pattern is checked by using the generated reference pattern. Before that, it is necessary to synchronize the reference pattern with the input pattern. is there. If the synchronization operation is synchronized by shifting one bit at a time,
It takes a long time to be synchronized. When the target pattern is a pseudo-random pattern, the input pattern is sequentially taken into the pseudo-random pattern generator in the pattern generator 15, and the self-propelled state is obtained with the input pattern taken in all the shift stages. Synchronization can be obtained in a short time. However, the mark ratio of the target pattern is 1 /
There are various cases such as 4 or 1/8 or 3/4,
In these cases, the input pattern cannot be taken into the pattern generator 15 to be in a self-running state.
Therefore, it was necessary to shift the generation reference pattern by one bit in order to synchronize the generation reference pattern with the input pattern. Therefore, for example, when the shift stage is 23, the period of this pattern is 2 ²³ -1 bits, and if the clock frequency is 100 MHz, the worst case for synchronization is 83.9 mS. If the number of shift stages is 31,
The pattern period is 2 ³¹ -1 bits, so it takes 21.5 seconds at worst until synchronization is established.

An object of the present invention is to provide a pattern reproducer capable of reproducing a pseudo random pattern having an original mark ratio of 1/2 corresponding to an input pattern having a mark ratio of not 1/2. I do. If a pattern with a mark rate of 1/2 corresponding to the input pattern can be reproduced in this way, the reproduced pattern with a mark rate of 1/2 is put into a pseudo-random pattern generator to generate the pseudo-random pattern. When the reference pattern and the input pattern are compared with the input pattern from the pseudo random pattern generated by the pseudo random pattern generator, and the reference pattern is compared with the input pattern, the input pattern is A synchronized reference pattern can be obtained.

[0006]

According to the present invention, inputted input pattern data is partially reproduced in a mark ratio reproducing circuit by calculating the logical sum of the input pattern and the shifted pattern. A temporary reproduction pattern having a mark ratio of 1/2 is generated. The provisional reproduction pattern is input to the pseudo-random pattern generation circuit in the form of feedback data, and 1 in the provisional reproduction pattern is used as data indicating true as a cyclic shift having the same number of shift stages as the pseudo-random pattern generation circuit. The data is input to a true data storage circuit including a register. When it is detected that each data of the feedback stage and the final stage in the pseudo random pattern generation circuit is true, the feedback data of the pseudo random pattern generation circuit is fed back to the input side only at that time, and the true data storage circuit True data is written to the input side. It is determined whether or not the reproduction of the pattern having the mark rate of 1/2 has been established based on the state of the stored data in the true data storage circuit. If it is determined that the reproduction has been established, the pseudo-random pattern generation circuit outputs the feedback data. Is switched to the self-propelled type.

First, the principle of the present invention will be described.
You. Pseudo-random patterns have the same ratio of 1 to 0
Therefore, the mark ratio is considered to be 1/2. Actually, one cycle
Because the bit length is odd, it is slightly different from 1/2
I have. Next to a pseudo-random pattern with a mark ratio of 1/2
When the logical AND is calculated for the two bits that match, the mark ratio becomes 1
/ 4 pattern, and successive 3 bits
When the logical product is taken, the mark rate becomes 1/8 pattern.
You. That is, as shown in FIG.
Each bit of the_{twenty one}, D_{twenty two}, D_{twenty three}, D_{twenty four}, D_{twenty five}When
Each of these bits is 1, 0 as shown in the figure.
Value, the mark rate corresponding to this value is 1/4
Each bit of the turn is D₄₁, D₄₂, D₄₃, D₄₄When
Then, the pattern becomes as shown in the figure. Where D₄₁=
D_{twenty one}・ D_{twenty two}, D₄₂= D_{twenty two}・ D_{twenty three}, D ₄₃= D_{twenty three}・ D_{twenty four}......
It is. Also, each bit of the pattern whose mark rate is 1/8
To D ₈₁, D₈₂, D₈₃..., the mark ratio is 1 /
The figure is shown when the mark ratio corresponding to the pattern No. 2 is 1/8.
Become like Where D₈₁= D_{twenty one}・ D_{twenty two}・ D_{twenty three}And D
₈₂= D_{twenty two}・ D_{twenty three}・ D_{twenty four}And D₈₃= D_{twenty three}・ D_{twenty four}・ D_{twenty five}
And so on.

[0008] Because in this context, that the bit D ₄₁ of the pattern of the mark ratio conversely 1/4 is 1, bit D ₂₁ and D of the pattern of the original mark ratio is 1/2 ₂₂ must both be 1 Similarly, the mark rate is 1
If the bit D ₈₁ of the / 8 pattern is 1, the bits D ₂₁ , D _22, and D ₂₃ of the pattern having the original mark ratio of 共 に must be 1. Therefore, if a pattern having a mark rate of 1/4 is sequentially ORed with respect to adjacent patterns of each bit, a part of the pattern having a mark rate of 1/2 is reproduced. Similarly, if a logical sum is sequentially obtained for three adjacent bits of a pattern having a mark rate of ８, a part of the pattern having a mark rate of さ れ る is reproduced.

From the relationship shown in FIG. 10, when the pattern reproduced at the mark rate of 1/2 is 1, this is true, so this information is held in the true data storage circuit, and this true data is generated by the pseudo random pattern generation. If the shift stage and the final stage of the true data storage circuit corresponding to the feedback stage of the pseudo random pattern generation circuit and the shift stage and the end stage of the corresponding true data storage circuit are both true data, the pseudo random pattern generation at that time is performed. Since the feedback data of the circuit is also true, the feedback data of the pseudo-random pattern generation circuit at that time is fed back to its input side, and data indicating true data is input to the true data storage circuit, and If all the stored data in the true data storage circuit indicates a true state, the data in the pseudo-random pattern generation circuit is correct in accordance with the input pattern. Will be acquired a pattern of rate 1/2, a pseudo random pattern generating circuit may be set to the free-running state in this state.

[0010]

FIG. 1 shows an embodiment of the present invention. Input terminal 1
An input pattern having a mark rate of 1/2 ⁿ from 1 is input to the mark rate reproducing circuit 21. In the mark rate reproducing circuit 21, the logical sum of the input pattern and the shifted pattern is calculated, and the mark rate 1 corresponding to the input pattern is obtained.
/ 2 is provisionally reproduced into a pattern of / 2, and this provisionally reproduced pattern is supplied to the pseudo random pattern generation circuit 22. The pseudo-random pattern generation circuit 22 operates in synchronization with the clock of the terminal 13, that is, in bit synchronization with the input pattern. In the initial state, the temporary reproduction pattern is input to the pseudo-random pattern generation circuit 22 as data. Further, a true data storage circuit 23 is provided. The true data storage circuit 23 is composed of a cyclic shift register having the same shift stage as the pseudo-random pattern generation circuit 22, and is shifted by the clock of the terminal 13. Information in which the bit in the temporary reproduction pattern is 1 from the mark rate reproduction circuit 21 is input to the true data storage circuit as true data. If both the data at the shift stage and the last stage corresponding to the feedback stage of the pseudo-random pattern generation circuit 22 in the true data storage circuit 23 are true, this is detected by the AND circuit 24, and the pseudo-random pattern generation circuit 22
Then, the true data storage circuit 23 is notified of this fact, and only then is the pseudo random pattern generation circuit 22 fed back its own feedback data to the input side instead of the temporary reproduction pattern, and in the true data storage circuit 23, , Ie, 1 is input.

The output of the AND circuit 24 is counted by a counter 25. When it is detected that the count value is a predetermined value, that is, that all the shift stages of the true data storage circuit 23 are all 1, a pseudo random pattern is generated. The input of the circuit 22 is switched from the temporary reproduction pattern to its own feedback data, and the circuit 22 is brought into a free running state. This means that a pattern corresponding to the input pattern and having a mark rate of 1/2 has been reproduced.

When the error rate is detected, the pseudo-random pattern for which pattern reproduction has been established from the pseudo-random pattern generation circuit 22 is applied to the reference pattern conversion circuit 3.
1 and converted into a reference pattern of a pattern having the same mark rate as the input pattern, and this is supplied to the exclusive OR circuit 12. On the other hand, the mark rate reproducing circuit 21
The input pattern that has passed through is shifted by the shift register 32 in the reference pattern conversion circuit 31 and then supplied to the exclusive OR circuit 12 to detect a mismatch with the reference pattern, that is, an error.

FIG. 2 shows a specific example of the mark ratio reproducing circuit 21. The input pattern from the input terminal 11 is the polarity control circuit 3
7 to the shift register 38. The shift register 38 is a two-stage shift register, and includes a first stage 38a and a last stage 38b. An output from the last stage 38b is supplied to an input terminal D ₀ of a selector 39.
The logical sum with the output of the first stage 38 a is obtained by the OR circuit 41, and the output of the OR circuit 41 is input to the input terminal D _{1 of the} selector 39.
Supplied to The OR of the output of the OR circuit 41 and the input of the shift register 38 is calculated by the OR circuit 42 and supplied to the input terminal D ₂ of the selector 39. Selector 39
Control signal A of terminals 43, 44, B outputs the input terminals D ₀ when both of the low level L, the control signal A is high H, when the control signal B is at the low level L input terminal D ₁ outputs of the input, the control signal a is at a low level, the control signal B is at high level and outputs the input of the input terminal D _2. Input terminal D
Signal from ₀ is the same as the input pattern, which is the mark ratio of the input pattern is the input terminal D ₀ when 1/2 is selected.

The output of the OR circuit 41 is obtained by sequentially taking the logical sum of adjacent bits, and a part of the input pattern having the mark rate of 1/4 is reproduced into a pattern having the mark rate of 1/2.
Therefore, when the mark rate is 1/4 of the input pattern input terminal D ₁ is selected. The output of the OR circuit 42 is
The logical sum of the two bits is sequentially shifted, so that a part of the input pattern having the mark rate of 1/8 is reproduced by the OR circuit 42 as a pattern having the mark rate of 1/2, and the input pattern having the mark rate of 1/8 is input. If pattern input terminal D ₂ is selected. When the mark ratio of the input pattern is 3/4, the polarity of the input pattern is inverted by the exclusive OR circuit of the polarity control circuit 37 by setting the polarity control terminal 45 to the high level, and the mark ratio is converted to a pattern of 1/4. Shift register 38
To supply. Similarly, when the mark ratio of the input pattern is 7/8, the polarity of the input pattern is inverted by setting the terminal 45 to the high level H and supplied to the shift register 38 as a pattern with the mark ratio of 1/8. The output of the selector 39 is supplied to the pseudo random pattern generation circuit 22 as the output of the mark ratio reproduction circuit 21. The output of the shift register 38 is supplied to the shift register 32 as an input pattern having passed through the mark rate reproducing circuit 21.

The pseudo-random pattern generation circuit 22 has _N shift stages of 46 _{1 to} 46 _N , for example, as shown in FIG.
A shift register 46 is provided, and an exclusive OR of an output of the N-th stage 46 _{N and} an output of the K-th stage 46 _K is obtained by a circuit 47. either the temporary reproduction pattern than 21 is supplied is selected in the first stage 46 _1.

Next, referring to FIG.
A specific example 3 will be described. The true data storage circuit 23 comprises a circulating shift register 51, the shift stage 51 ₁ to 51 _N is equal to the number of shift stages N of the pseudo random pattern generator circuit 22, and is shifted at the clock terminal 13 . The output of the final stage 51 _N is connected to an OR circuit 52.
It is fed back to the input side of the stage 51 ₁ through, and is configured as a circular shift register. The provisional reproduction pattern of the mark ratio reproduction circuit 21 is provided as one input of an AND circuit 53, and the output of the AND circuit 24 is inverted and supplied through the OR circuit 26 as the other input of the AND circuit 53. Therefore, the output of the AND circuit 24 becomes 0
In the state (1), bit 1 of the provisional reproduction pattern is true data, so the first shift stage 51 _{1 is} passed through the AND circuit 53 and the OR circuit 52.
Is input as data indicating true. Feedback stage 46 of pseudo-random pattern generation circuit 22 of true data storage circuit 23
The output of the same shift stage 51 _K and _K, and the output of the final stage 51 _N is supplied to the AND circuit 24. If the data both indicate true, and if 1, the feedback data of the pseudo-random pattern generation circuit 22, that is, the exclusive OR circuit 4
The output of 7 is also true. Therefore, these shift stages 51 _K ,
51 When _N data is true, the output becomes 1 of the AND circuit 24, AND circuit 53 by the 1 is inhibited and data 1 stage shift stage 51 indicating the true through the OR circuit 52 in place ₁ Is input to

Each time the feedback data of the pseudo-random pattern generation circuit 22 is detected to be true, the feedback data at that time is also sent to the pseudo-random pattern generation circuit 22 through the input selection circuit. It is fed back to the input side of 46. When it is detected that the feedback data is true, this is detected by the counter 25 in FIG.
Thus, when all the shift stages in the true data storage circuit 23 have all become 1, the data of each shift stage of the pseudo random pattern generation circuit 22 has also become true. At this time, the pattern having the mark rate of 1/2 is reproduced, and in this state, the pseudo random pattern generating circuit 22 is switched to the self-running state.

The reference pattern conversion circuit 31 is, for example, as shown in FIG.
It is configured as shown in FIG. That is, the pseudo-random pattern from the pseudo-random pattern generation circuit 22 in the state where the pattern reproduction is established is supplied to the two-stage shift register 64, which is shifted by the clock from the terminal 13, and the last shift stage 64 output ₂ is supplied to the input terminal D ₀ of the selector 65, which together with the logical product of the output of the first shift stage 64 ₁ is taken in the circuit 66, the input terminal D ₁ of the output selector 65 of the circuit 66 The AND of the output of this circuit 66 and the input of the shift register 64 is obtained by the circuit 67, and the output is supplied to the input terminal D ₂ of the selector 65. The input of the selector 65 is selected by the control signals A and B of the terminals 43 and 44, and the selection of this input is performed in the same manner as the selection of the selector 39 in FIG. The output of the selector 65 is supplied to the exclusive OR circuit 12 as a reference pattern.

In the AND circuit 66, the logical product of adjacent two bits is sequentially obtained and output as a pattern having a mark rate of 1/4. In the AND circuit 67, the three adjacent logical products are sequentially obtained and output as a pattern having a mark rate of 1/8. The reference pattern thus obtained and the input pattern are compared in the exclusive OR circuit 12.

Next, a specific example of the synchronization control circuit 17 will be described with reference to FIG. The start signal from the terminal 18 is the OR circuit 6
8 to the terminal 19 as a reset signal.
On the other hand, the output of the exclusive OR circuit 12, which is an error detection circuit, is supplied to an enable terminal of the counter 71, and when an error is detected, the counter 71 is enabled.
The clock from the terminal 13 is supplied to the counters 71 and 73 through the gate 72 as a count input. The counter 73 is always operable, and therefore counts the number of clocks, that is, the number of bits of the input pattern. However, the counter 71 can count only when an error is detected. An incorrect number of bits will be counted. When the count value of the counter 71 becomes larger than a predetermined value, its output is supplied to the terminal 19 as a reset signal through the OR circuit 68, and each unit is reset. That is, if the number of errors is extremely large, it is determined that the reference pattern and the input pattern are not synchronized, and the state is returned to the initial state. The output of the counter 71 is supplied to the D
The flip-flop 75 is also supplied to the D flip-flop 75 by the next clock.
The output of 1 is taken in, and the output is supplied to the reset terminals of the counters 71 and 73 through the OR circuit 76, and these are reset. The OR circuit 76 is also supplied with a start signal from the terminal 18. When the counter 73 reaches a predetermined value, the predetermined count value is significantly larger than the predetermined count value of the counter 71, and when the counter value reaches the predetermined value, an output is generated from the counter 73, which is supplied to the OR circuit 74. At the same time, the D-type flip-flop 77 is triggered, and its high level is captured by the D-type flip-flop 77, and the D-type flip-flop 77 outputs a synchronization establishment signal to the terminal 78.

[0021] From the relationship of FIG. 10 indicated above, regeneration if any bit D _K pattern 1 is true, as mentioned above, also, because even if it was 0 in the first neighbor is true After all, the condition that this arbitrary bit _DK is true is only required that the logical sum of the previous bit _DK-1 , the relevant bit _DK and the next bit _{DK + 1} is 1. Therefore, as shown in FIG. 7A with the same reference numerals given to the parts corresponding to FIG. 1, the provisional reproduction pattern from the mark rate reproduction circuit 21 is input to the 3-bit shift register 54, and the output of the middle shift stage is pseudo. In addition to supplying to the random pattern generation circuit 22, the outputs of the three shift stages of the shift register 54 are supplied to the OR circuit 55, and the output of the OR circuit 55 is supplied to the true data storage circuit 23. In this way, true data is also determined from before and after the bit of interest. That is, even when the data of interest is 0, it is regarded as true data if its neighbor is 1, and 1 is input to the true data storage circuit 23. Thus, it becomes faster for each shift stage in the true data storage circuit 23 to become 1 than in the case of FIG.

As shown in FIG. 7B by assigning the same reference numerals to parts corresponding to those in FIG.
And a circuit 57-bit feedback shift stage 46 _K detects the data of the circuit 56 and output stage 46 _N for detecting that the true is true provided, the true detection circuit 56 and 57 are both true When it is detected that the data is present, the feedback data of the pseudo-random pattern generation circuit 22 at that time is true.
The AND of the outputs of the circuits 56 and 57 is obtained by the AND circuit 58 so that the feedback data is fed back, and the pseudo-random pattern generation circuit 22
Is switched from the temporary reproduction pattern to the feedback data side only at that time, and the true data storage circuit 23 also inputs 1.
Further, As is true also for the embodiment of the case shown above, by taking the logical product of all the data of all the shift stages 51 ₁ to 51 _N of the true data storage circuit 23 in this example an AND circuit 59 When the output of the AND circuit 29 is at a high level, the pseudo-random pattern generation circuit 22 is brought into a self-running state. Note that when the operation is performed from the initial state, the inside of the pseudo-random pattern generation circuit 22 is all 0. In this state, the reset signal from the terminal 19 is used so that the true detection circuits 56 and 57 do not erroneously detect true. The counter 61 is reset, and the counter 61 counts the clock at the terminal 13. When the counter 61 counts the number of shift stages N of the pseudo random pattern generation circuit 22, the true detection circuits 56 and 57 are enabled by the output of the counter 61. I do.

FIG. 8 shows a specific example of the true detection circuits 56 and 57.
You. Each shift stage 4 of the pseudo-random pattern generation circuit 22
6_K-2To 46_{K + 2}Each data, D_K-2Or D_{K + 2}Enters
Forced, its D_K-1And D_KAnd D_{K + 1}OR is OR times
Taken at road 81, D_K-2And D _K-1AND with AND
Taken at road 82, D_K-1And D_{K + 1}AND with AND
Taken at road 83, D_{K + 1}And D_{K + 2}AND of AND circuit
84 and the outputs of AND circuits 82, 83, 84 and D
_KIs ORed with OR circuit 85, and OR circuit 81,
85 is supplied to gates 86 and 87, respectively, and
6 is opened by the control signal A of the terminal 43, that is, in this case,
In the case where the input pattern has a mark rate of 1/4, the gate 4
7 is opened by the control signal B of the terminal 44, and in this case, the input
In the case where the turn has a mark rate of 1/8, the gates 86 and 8
7 is supplied to a gate 89 through an OR circuit 88.
You. Gate 89 is disabled by the output of counter 61.
The output of the OR circuit 88 is output.
To be done. Last stage 46_NThat the data is true
Is also configured in the same manner as in FIG.
If the input data is D_K-2Or D_{K + 2}Against D
_N-2Or D_{N + 2}Is input. So this place
In this case, the final stage
46_NNeed to connect two shift stages in series after
There is.

[0024] While the input pattern of the present invention in the above has been described for the case of the mark rate 1 / 4,1 / 8,3 / 4,7 / 8, also adapted to the case of general 1/2 ^n, in this case In the mark ratio reproducing circuit, the input pattern and the pattern shifted by one bit each are n
What is necessary is just to create a pattern sequence of columns and take the logical sum of the corresponding ones.

[0025]

As described above, according to the present invention, an input pattern is reproduced into a pattern having a mark rate of 1/2, which is input to a pseudo-random pattern generating circuit.
Whether or not this is true is stored in correspondence with each shift stage of the pseudo-random pattern generation circuit, and when it is detected that the feedback data in the pseudo-random pattern generation circuit is true, the true data is correspondingly stored. Is then fed back to the pseudo-random pattern generation circuit, and when all the shift stages in the true data storage circuit represent true data in the true data storage circuit, the pseudo-random pattern generation circuit Is a pattern with a mark rate of 1/2 corresponding to the input pattern data, and the pseudo-random pattern generation circuit is in a self-running state. Therefore, when the reference data having the mark ratio corresponding to the input data is further generated, it is not necessary to shift each bit, and the reference data can be generated in a very short time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of a mark ratio reproducing circuit 21 in FIG. 1;

FIG. 3 is a block diagram showing a specific example of a pseudo random pattern generation circuit 22 in FIG. 1;

FIG. 4 is a block diagram showing a specific example of a true data storage circuit 23 in FIG. 1;

FIG. 5 is a block diagram showing a specific example of a reference pattern conversion circuit 31 in FIG. 1;

FIG. 6 is a block diagram showing a specific example of a synchronization control circuit 17 in FIG. 1;

FIG. 7 is a block diagram showing another embodiment of the present invention.

FIG. 8 is a logic circuit diagram showing a specific example of a true value detection circuit 56 in FIG. 7B.

FIG. 9 is a block diagram showing a conventional bit error rate detection circuit.

FIG. 10 is a diagram showing an example of the relationship between a conventional pattern having a mark rate of ２ and a corresponding pattern having a mark rate of 、 and a mark rate of ８.

Continuation of front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H03K 3/84

Claims (1)

(57) [Claims] 1. A pattern reproducing device for inputting a pattern having a mark rate of 1/2 ⁿ and reproducing a pattern having a mark rate of 1/2 corresponding thereto, wherein the input pattern and a pattern obtained by shifting the input pattern A mark rate reproducing circuit for generating a temporary reproduction pattern having a mark rate of 1/2 by taking the logical sum of the above, a pseudo random pattern generating circuit for generating a pseudo random pattern in bit synchronization with the input pattern, and a pseudo random pattern And a cyclic shift register having the same shift stage as the above, shifted in synchronization with the pseudo-random pattern generation circuit, and a true data storage circuit into which 1 in the provisional reproduction pattern from the mark rate reproduction circuit is input as true data. If the data at the feedback stage and the final stage of the pseudo random pattern generation circuit are both true data, the pseudo random pattern at that time is true. Means for feeding back the feedback data of the turn generation circuit in place of the temporary reproduction pattern and writing the true data in the true data storage circuit; and when all shift stages of the true data storage circuit become true data, Means for switching the input of the pseudo-random pattern generation circuit from the temporary reproduction pattern to the feedback data to make the pseudo-random pattern generation circuit self-running.