JP2953936B2 - Duty discrimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a beauty discriminating circuit for discriminating a magnitude relation between a ratio (that is, duty) of a leading portion to a period of an input signal whose level periodically changes and a threshold value.

[0002]

2. Description of the Related Art A conventional duty discriminating circuit includes:
A description will be given by taking an example used in a home VTR (Video Tape Recorder).

In a home VTR of the VHS standard, for example, various codes represented by bit information such as an index code and an address code may be recorded on a video tape. As a method of recording such bit information on a video tape, there is a method of using a control signal recorded on the video tape for phase matching of the video tape. This means that 1-bit recording information "0" and "1"
Are represented by one-cycle pulse signals having different duties. Usually, the duty of “0” is set to 60%, and the duty of “1” is set to 27.5%. When reading such bit information, the duty discrimination circuit determines the magnitude relationship between the duty of the reproduced control signal and a threshold value, which will be described later, to determine whether the reproduced signal is “0”. It is determined whether it is "1".

FIG. 9 is a block diagram showing a configuration example of a conventional duty discriminating circuit. FIG. 10 is a timing chart showing the operation of the duty determination circuit. Here, the leading portions 81a and 82a of the reproduction control signals 81 and 82 in one cycle are set to the high level, and the following portions 81b and 82b are set to the low level.

First, a description will be given of the duty determination of the reproduction control signal 81 having a duty of 27.5%.

[0006] The sequencer 71 detects the rise 81c of the reproduced control signal 81, and outputs the sampling signal SA ₈₁ and a reset signal R _81.

The counter circuit 72 outputs the reset signal R
It is reset at ₈₁ and starts counting the number of reference clocks input from a reference clock generation circuit (not shown) (that is, measuring the elapsed time from the rise of the leading portion 81a).

[0008] Next, the sequencer 71 detects a fall 81d of the reproduced control signal 81, and outputs a latch signal L _81.

[0009] The latch circuit 73 inputs the latch signal L _81, latches the output and count value C ₁ of the counter circuit 72. Then, the latch data C ₂ is input to the shift circuit 74, the data is output after being shifted by one bit in the direction of increasing. Thus, the output value C ₃ of the shift circuit 74 is twice the latch data C _2.

The magnitude comparison circuit 75 includes a count value C ₁ output from the counter circuit 72 and an output value C _{3 from the} shift circuit 74.
To determine the magnitude relationship between the two. And C ₁ <
When the C ₃ to an output signal to a low level. When the count value C ₁ increases and C ₁ ≧ C ₃ , the output signal goes high.

Subsequently, the output signal C ₄ of the magnitude comparison circuit 75
Is input to the data flip-flop 76. The data flip-flop 76 generates a signal according to a sampling signal SA ₈₂ output when the sequencer 71 detects a rising edge 82 c of the next reproduction control signal 82.
And it outputs the signal C ₄ input from the magnitude comparator circuit 75 as a duty determination result C _5.

Here, when the duty of the reproduction control signal is less than 50%, the time of the preceding part is shorter than the time of the following part, so that the entire time of the one-bit reproduction control signal is the time of the preceding level. Is greater than twice. Therefore, when the sequencer 71 detects the next rising edge 82c, C ₁ ≧ C ₃ (= 2C ₂ ), so that the duty discrimination result C ₅ is at a high level, indicating that the duty is 27.5%.

Next, a description will be given of the duty determination of the reproduction control signal 82 having a duty of 60%.

Similarly to the above case, when the sequencer 71 detects the rising edge 82c of the reproduction control signal ₈₂ and outputs the reset signal _R82 together with the sampling signal SA82, the counter circuit 72 is reset and starts counting the reference clock number. I do. When the outputs of the latch signal L ₈₂ detects the edge 82d sequencer 71 stands,
The latch circuit 73 latches the count value C ₁ and the shift circuit 7
4 and outputs the latched data C ₂ inputted by one bit shift as an output value C _3.

Here, the duty of the reproduction control signal is 60%, which is larger than 50%, so that the time of the preceding part becomes longer than the time of the following part.
The time of the entire reproduction control signal 82 is smaller than twice the time of the preceding part. Therefore, the sequencer 71
When the next rising edge 83c is detected, C ₁ <C ₃ , so that the duty determination result C ₅ is at a low level, indicating that the duty is 60%.

As described above, in the conventional duty discriminating circuit, the counter is operated at the rise of the signal whose duty is to be discriminated, and the ratio of the count number of the preceding portion to the count number of one cycle is determined as the duty, and this is determined. It is determined whether the value is more or less than the value of 50%.

[0017]

However, the threshold value of the duty discriminating circuit is a value exactly intermediate between two types of duties used for recording bit information, that is, (27.5 + 60) / 2 = 43. Ideally, it is 5 [%].

When the video tape is reversed, the leading and trailing portions are reversed, so that the duties of the reproduction control signal are 72.5% and 40%, respectively. 72.5 + 40) /2=56.25 [%].

As described above, the threshold value (50%) used in the conventional duty discriminating circuit has deviated greatly from the ideal value. For this reason, when the reproducibility of the reproduction control signal is poor, such as when a video tape is being sent at a high speed, there is a possibility that an erroneous determination may be made.

In general, the current VTR generally employs 27.5% and 60% as the duty. However, if a different duty is adopted in the future, a duty other than 50% may be used. The appearance of a discrimination circuit is desired.

Techniques for solving such problems include:
A technology disclosed in Japanese Patent Application Laid-Open No. 1-228919 is known. This is to determine the duty by using an arbitrary threshold value by using different measurement clocks for the preceding level and the succeeding level. However, this duty discrimination circuit requires a complicated calculation for discrimination of the duty, and thus has a disadvantage that the circuit scale becomes large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and provides a duty discriminating circuit having a simple circuit configuration and capable of setting a threshold value close to an optimum value according to the duty. The purpose is to provide.

According to a first aspect of the present invention, there is provided a duty discriminating circuit for discriminating a magnitude relationship between a duty of an information signal whose level periodically changes and a threshold value, wherein a time of a preceding part and a following part of the information signal are referred to. A counter circuit for detecting by counting clocks, and a shift circuit for shifting the preceding partial time data (binary number) obtained by the counter circuit by a factor of 2- ⁿ (n is zero or a natural number) times and outputting the result. A discrimination circuit for determining a discrimination point by comparing the time of a succeeding portion of the information signal with the provisional threshold using the shift data obtained by the shift circuit as a provisional threshold; An output circuit for outputting a duty discrimination signal based on the relationship between the output point and the succeeding portion is provided.

[0024]

According to a second aspect of the present invention, there is provided a duty discriminating circuit for discriminating a magnitude relation between a duty of an information signal whose level periodically changes and a threshold value, wherein a leading portion of the information signal is detected to output a sampling signal. And a sequencer that detects a succeeding portion and outputs a latch signal, detects both portions and outputs a reset signal, and outputs a shift signal for obtaining an optimum threshold value, and is reset by the reset signal, A counter circuit that counts a reference clock; a latch circuit that latches count data counted as preceding partial time data by the counter circuit in accordance with the latch signal; and a latch circuit that latches based on the shift signal output from the sequencer. 2 ^{-n (n} is zero or a natural number latched the count data was by bitwise shift in circuit A shift circuit that shifts and outputs the data twice, and compares the shift data output from the shift circuit with the count data output from the counter circuit as a provisional threshold value. A comparison circuit that outputs a comparison result signal when the value is larger, and an output circuit that outputs the comparison result signal as a determination result signal based on a level of the information signal and a sampling signal.

It is preferable that the output circuit outputs the comparison result signal with respect to the information signal input in a previous cycle in response to the input of the sampling signal.

The sequencer outputs the shift signal and the second shift signal in response to the fall of the leading portion of the information signal when the signal indicating the traveling direction of the signal indicates the reverse direction. And the second
It is preferable that a threshold value close to a desired value is obtained by a combination of shift data values obtained by the shift signal of (1).

According to a third aspect of the present invention, there is provided a duty discriminating circuit for discriminating a magnitude relation between a duty of an information signal whose level periodically changes and a threshold value, wherein a leading portion of the information signal is detected and a sampling signal is detected. And output
A sequencer that detects a succeeding portion and outputs a latch signal, detects both portions and outputs a reset signal, a counter circuit that is reset by the reset signal and counts a reference clock, and a preceding portion in the counter circuit. A latch circuit for latching the count data counted as time data in accordance with the latch signal; comparing the latch data output from the latch circuit with the count data output from the counter circuit; A comparison circuit that outputs a comparison result signal when the count data is large, and an output circuit that outputs the comparison result signal as a determination result signal based on a level of the information signal and a sampling signal. Is what you do.

[0029]

The duty discriminating circuit according to the present invention obtains the time of the leading portion of the information signal whose level changes periodically by counting the reference clock with a counter, and converts the leading portion time data thus obtained into a shift circuit. Then, a discrimination point is determined by comparing the shifted data with a succeeding portion of the information signal as a provisional threshold value, and duty discrimination is performed from the positional relationship between the discrimination point and the following portion. In such a circuit, the duty can be determined by a single clock without performing complicated calculations. The value of the provisional threshold can be changed by changing the shift amount.

In the case of a fixed duty ratio, the shift circuit can be omitted.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a duty determination circuit according to a first embodiment of the present invention.

In FIG. 1, a sequencer 11 receives a reproduction control signal and a forward / reverse signal. Here, when the signal sequencer 11 detects the rise of the reproduction control signal, it outputs a sampling signal and a reset signal, and sets the enable signal to low level. When the fall of the reproduction control signal is detected, the reset signal and the latch signal are output when the normal rotation / reverse rotation signal indicates the normal rotation (here, high level), and the normal rotation / reverse rotation is performed. When the signal is at a low level, the second shift signal is output together with the reset signal and the latch signal. Furthermore, the magnitude comparison circuit 15 to be described later, and inputs the signal C ₄ indicating the comparison result, when the signal C ₄ becomes high level, when the reset signal and the shift signal (forward / reverse rotation signal is at the high level The first shift signal is output, and when the signal is at a low level, the second shift signal is output. Then, the signal C ₄ is and playback controls signal at a high level when the low level, the enable signal to the high level.

The counter circuit 12 counts the number of reference clocks input from a reference clock generation circuit (not shown) and outputs this count value C _{1. When a} reset signal is input from the sequencer 11, to reset the count value C _1. This makes it possible to measure the time that has elapsed since the reset was performed.

The latch circuit 13 includes the sequencer 11 described above.
When the latch signal is input from the counter circuit 12, the count value C ₁ output from the counter circuit 12 is latched.

The shift circuit 14 receives the latch data C ₂ from the latch circuit 13. When the first shift signal is input from the sequencer 11, the latch data C _2, the output value, and outputs the shifted meiotic direction so that 1/4 of the latch data C _2. Moreover, when entered the second shift signal from the sequencer 11, the output value C ₃ and outputs the shifted so that 1/2 of the latch data C _2.

The magnitude comparison circuit 15 receives the count value C ₁ output from the counter circuit 12 and the output value from the shift circuit 14 and determines the magnitude relation between them. And C ₁ <C ₃
To the output signal C ₄ to a low level when. When the count value C ₁ increases and C ₁ ≧ C ₃ , the output signal C _{4 is set} to a high level.

When the enable signal input from the sequencer 11 is at a high level, the AND circuit 16 outputs the signal C ₄ input from the magnitude comparison circuit 15 as a discrimination threshold signal C ₅ . Also, when the enable signal is at a low level, fixes the discrimination threshold signal C ₅ to a low level.

FIG. 2 is a circuit diagram showing a detailed configuration of the sequencer 11 in FIG. Three-stage D flip-flop 1
Numerals 03, 104 and 105 are connected in series, and one of a reproduction control signal and an inverted signal from the inverter 101 is selected and input to the D input terminal of the first stage flip-flop 103 by a forward / reverse signal. . A clock input terminal of each flip-flop is supplied with a signal obtained by inverting a reference clock signal by an inverter 102.

The Q output of flip-flop 103 is supplied to one input terminal of AND gate 111 via AND gate 109 and inverter 108, and the Q output of flip-flop 104 is supplied to the other side of AND gate 109 via inverter 106. , One side of the AND gate 110, the other side of the AND gate 111, the NOR gate 11
4 is provided to the respective input terminals on one side, and the Q output of the flip-flop 105 is connected to the other side of the NOR gate 114,
The signal is supplied to the other side of the AND gate 110 and one side of the AND gate 112 via the inverter 107. The AND gate 109 outputs a sampling signal, and the AND gate 111 outputs a latch signal.

The reference clock signal is also supplied to three stages of D flip-flops 123, 124 and 125 connected in series, and a reset signal output from the AND gate 110 is supplied to these reset input terminals. The output signal of the magnitude comparison circuit is supplied to the D input terminal of the first-stage AND gate 123 via the AND gate 122, and the output of the AND gate 123 is supplied to the AND gates 127 and 128.
, The output of the AND gate 124 is on one side of the AND gate 129, and the output of the AND gate 125 is inverted by the inverter 126 to
8 and 129 are input to the other input terminals. The output of the AND gate 128 is supplied to the OR gate 113 together with the output of the AND gate 110 and the output of the AND gate 112, and the reset signal is extracted. The output of the AND gate 127 is supplied to the counter circuit 134 as a counter clock, and the outputs of the AND gates 112 and 129 are supplied to the latch circuit 133 as a shift data latch signal by the OR gate 130.

Storage units 131-1 to 131-n for storing arbitrary shift data 0 to n are provided, and one of the data taken out therefrom is selected by a switching circuit 132 and supplied to a latch circuit 133. , Are extracted from the latch circuit 133 as shift signals having various reduction rates.

The above-mentioned latch signal is supplied to the counter circuit 134 as a counter reset signal, and the count data output from the counter circuit is supplied to the switching circuit 13.
2 and the match detection circuit 135. This coincidence detection circuit 135 is compared with the threshold value to be switched extracted from the switching data storage unit 136, and the coincidence output is given to the set input terminal of the RS flip-flop 137 via the OR gate 137. The output of the AND gate 110 is given to the other input terminal of the OR gate 137. The RS flip-flop 137
The output signal of the AND gate 112 is provided to the reset input terminal of the AND gate 122, and the Q output signal thereof is inverted by the inverter 121 and applied to the other input terminal of the AND gate 122, and the output of the NOR gate 114 is provided to one side. The output of the AND gate 139 is input to the other side, and its output becomes an enable signal.

The data flip-flop 17 inputs the sampling signal from the sequencer 11, and outputs a determination threshold signal C ₅ input from the AND circuit 16 as a duty determination result C _6.

Next, the operation of the duty discriminating circuit according to this embodiment will be described.

FIG. 3 is a timing chart showing the circuit operation when the video tape rotates forward, that is, when the forward / reverse signal is at a high level. At this time, the leading part 21 of the one-cycle reproduction control signals 21 and 22
a, 22a are at a high level, and the following portions 21b, 22a
b is at a low level.

First, the determination of the duty of the reproduction control signal 21 having a duty of 27.5% will be described.

[0048] The sequencer 11 detects the rise 21c of the reproduced control signal 21, and outputs a sampling signal SA ₁ and the reset signal R _1, the enable signal to the low level.

The counter circuit 12 outputs the reset signal R
It is reset at ₁ and starts counting the number of reference clocks input from a reference clock generation circuit (not shown).

Next, the sequencer 11 detects a fall 21d of the reproduced control signal 21, first outputs a latch signal L _1, further outputs a reset signal R ₂ by shifting a predetermined time.

The latch circuit 13 inputs the latch signal L _1, for latching the output and count value C ₁ of the counter circuit 12. The counter circuit 12 is reset by a reset signal R _2, again counting the number of reference clocks.

The latch data C ₂ output from the latch circuit 13 is input to the shift circuit 14. At this time, since the shift circuit 14 has not received the shift signal, the output value C ₃ is equal to the latch data C ₂ . Have the same value.

Here, the output value C ₃ of the shift circuit 14 is constant until the sequencer 11 outputs the next latch signal, but the count value C ₁ output by the counter circuit 12 is constant.
Increase sequentially according to the reference clock. And C
_{When 1} ≧ C ₃ , the magnitude comparison circuit 15 sets the output signal C ₄ to a high level.

When the signal C ₄ goes high, the sequencer 11 resets the reset signal R ₃ and the first shift signal S
And it outputs the H _1. At this time, since the reproduction control signal 21 is at low level, the enable signal is set to high level.

[0055] The counter circuit 12 is reset by a reset signal R _3, again counting the number of reference clocks. Also,
The output value C ₃ of the shift circuit 14 is １ ／ of the latch data C ₂ input from the latch circuit 13. At this time, the output signal C ₄ of the magnitude comparison circuit 15 becomes the low level again. Therefore, even if the enable signal goes high, the discrimination threshold signal C
₅ remains low.

When C ₁ ≧ C ₃ again, the output signal C ₄ of the magnitude comparison circuit 15 goes high again, so that the discrimination threshold signal C ₅ output from the AND circuit 16 rises, and Become.

Here, the period of the preceding portion (high level) 21a is T _H , the period from the falling 21d until C ₁ = C ₃ first becomes T _L1 , and C ₁ = C ₃ first. Next, _assuming that a period until C ₁ = C ₃ is T _L2 , the discrimination threshold signal C starts from the rising edge 21c of the preceding portion 21a.
Period T _D to the rising of the ₅ becomes _{T D = T H + T L1} + T L2. Further, a _{T H = T L1 = 4T L2} . Threshold duty discriminating circuit according to the present embodiment is provided when the whole period and the period T _D of the reproduced control signal 21 matches. Therefore, the threshold is

[0058]

(Equation 1) Becomes That is, when the duty is 44.4% or less, the sequencer 11 outputs the next reproduction control signal 22
Determination threshold signal C ₅ upon detection of the rise 22c of is at the high level.

In the data flip-flop 17, the sequencer 11 outputs the second rising edge of the reproduction control signal 22.
Sampling signal SA ₂ output when 2c is detected
According to the duty determination result C ₆ to a high level.

Thus, the reproduction control signal 2
It can be seen that the duty of 1 is 27.5%.

Next, the determination of the duty of the reproduction control signal 22 having a duty of 60% will be described.

[0062] As with the above, the sequencer 11 outputs the reset signal R ₄ together with the sampling signal SA ₂ detects the rise 22c of the reproduced control signal 22, the counter circuit 12 starts counting of the reset reference clock number . Also, the enable signal becomes low level.

Then, the sequencer 11 falls 22
Upon detection of d, latch signal L ₂ is output and further output the reset signal R ₅ after a predetermined time. Accordingly, the latch circuit 13 latches the count value C _1, then,
Counter circuit 14 performs the reset count C _1. Therefore, C ₁ <C ₃ .

If C ₁ <C ₃ when the sequencer 11 detects the next rising edge 23c, A
Input of ND circuit 16 determines a threshold signal C ₅ becomes a low level because both at low level, therefore, the duty determination result C ₆ to output the data flip-flop 17 when the sampling signal SA ₃ is input row Level. This indicates that the duty is 60%. In this case, if C ₁ ≧ C ₃ due to poor reproducibility of the duty, the output signal C ₄ of the magnitude comparison circuit 15 goes high. Then, in the same manner as described above, the counter circuit 12
Is reset, the latch data C ₂ is reduced to １ ／, and the enable signal is set to a high level. But C
Since ₁ ≧ C ₃ and the discrimination threshold signal C ₅ if not not a high level, after all, the duty determination result C ₆
Becomes low level, and the duty is determined to be 60%.

As described above, in the duty discriminating circuit of this embodiment, the threshold value at which the video tape rotates forward is set to 4
It can be 4.4%. Since this value is very close to the ideal threshold value of 43.75%, it is possible to accurately determine the duty.

Next, the circuit operation when the video tape rotates in the reverse direction, that is, when the normal rotation / reverse rotation signal is at a low level will be described with reference to FIG. FIG. 4 is a timing chart showing the circuit operation in such a case. At this time, the leading levels 31a and 32a of the reproduction control signals 31 and 32 for one cycle are at a low level, and the following levels 31b and 32b are at a high level.

First, a description will be given of the duty determination of the reproduction control signal 31 in which the duty at the time of reverse rotation is 40% (that is, the duty at the time of normal rotation is 60%).

[0068] The sequencer 11 detects a fall 31c of the reproduced control signal 31, and outputs a sampling signal SA ₄ and the reset signal R _6, the enable signal to the low level. This reset signal R _6, the counter circuit 12 is reset.

Next, when detecting the rising 31d, the sequencer 11 first outputs a latch signal L _3, further shifted by a predetermined time and outputs a reset signal R ₇ and the second shift signal SH _2. Then, the latch circuit 13 latches the count value C ₁ by the latch signal L ₃ , and half the data of the latch data C ₂ at this time is output from the shift circuit 14 as the signal C ₃ . The counter circuit 12 is reset by a reset signal R _7.

Thereafter, when the count value C ₁ output from the counter circuit 12 increases and C ₁ ≧ C ₃ , the magnitude comparison circuit 1
5 is an output signal C ₄ to a high level.

When the sequencer 11 receives the signal C ₄ , the reset signal R ₈ and the first shift signal SH ₃
Is output, and the enable signal is set to a high level.

The counter circuit 12 is reset by the reset signal R ₈ , and the output value C ₃ of the shift circuit 14 becomes １ ／ of the latch data C ₂ input from the latch circuit 13. At this time, the output signal C ₄ of the magnitude comparison circuit 15
Since the low level again, discrimination threshold signal C ₅ remains at a low level.

When C ₁ ≧ C ₃ again, the output signal C ₄ of the magnitude comparison circuit 15 goes high again, and A
Determination threshold signal C ₅ for outputting the ND circuit 16 becomes high level.

Here, when the threshold value is obtained in the same manner as in the case of the above-described normal rotation, T _H = 2T _L1 = 4T _L2 .

[0075]

(Equation 2) Becomes That is, when the duty is 57.1% or less, the sequencer 11 outputs the next reproduction control signal 32
Determination threshold signal C ₅ when the falling 32c detects the is at the high level.

The data flip-flop 16 determines the duty determination result C according to the sampling signal SA _5.
Set ₆ to high level.

Thus, the reproduction control signal 3
It can be seen that the duty of 1 is 40%.

Next, a description will be given of the duty determination of the reproduction control signal 32 having a duty of 72.5% (that is, a duty at the time of normal rotation is 27.5%).

[0079] As with the above, the sequencer 11 outputs the reset signal R ₉ together with the sampling signal SA ₅ when detecting the falling edge 32c of the reproduced control signal 32, starts to count the reference clock counter circuit 12 is reset I do. Also, the enable signal becomes low level.

Then, the sequencer 11 rises 32
Upon detection of d, latch signal L ₄ is output and further output the reset signal R ₁₀ after a predetermined time. Accordingly, the latch circuit 13 latches the count value C _1, then,
Counter circuit 14 performs the reset count C _1. As a result, C ₁ <C ₃ .

If C ₁ <C ₃ when the sequencer 11 detects the next rising edge 33 c, A
Input of ND circuit 16 determines a threshold signal C ₅ becomes a low level because both at low level, therefore, the duty determination result C ₆ becomes low. This shows that the duty is 72.5%. In this case, if C ₁ ≧ C ₃ due to poor reproducibility of the duty, the output signal C ₄ of the magnitude comparison circuit 15 goes high. Then, the counter circuit 12 is reset in the same manner as described above, the latch data C ₂ is 1/4, further enable signal goes high. However, unless C ₁ ≧ C ₃ for the third time, the discrimination threshold signal C ₅ does not go to the high level, so that the duty discrimination result C ₆ goes to the low level, and it is judged that the duty is 72.5%. Is done.

As described above, in the duty discrimination circuit of this embodiment, the threshold value when the video tape is reversed is 5
7.1%. Since this value is very close to the ideal threshold value of 56.25%, it is possible to accurately determine the duty.

(Embodiment 2) Next, as a second embodiment of the present invention, using a duty discriminating circuit similar to that of FIG. 1, a sequence control different from the duty discriminating circuit of Embodiment 1 is performed by the sequencer 11. Thus, the first embodiment
A case where a threshold value different from the threshold value is obtained will be described.

FIG. 5 is a timing chart showing the operation of the duty discrimination circuit. Here,
The leading levels 41a and 42a of the reproduction control signals 41 and 42 for one cycle are set to the high level,
The case where b and 42b are at low level will be described as an example.

In this embodiment, the structure of the metal body is the same as that of FIG. 1. However, when the rising edge of the reproduction control signal is detected, the sequencer 11 outputs a sampling signal and a reset signal, and sets the enable signal to low level. When the fall of the reproduction control signal is detected, a reset signal, a latch signal, a shift signal for reducing the latch data to 1/2 are output, and the enable signal is set to a high level.

The structure of each of the other parts 12 to 17 is the same as that of the first embodiment.

The operation of the duty discriminating circuit according to this embodiment will be described below.

[0088] First, the sequencer 11 detects the rise 41c of the reproduced control signal 41, and outputs a sampling signal SA ₇ and the reset signal R _12, the enable signal to the low level. The counter circuit 12
Is reset by the reset signal R _12, starts counting the number of reference clocks.

[0089] Next, the sequencer 11 detects a fall 41d of the reproduced control signal 41, first outputs a latch signal L _5, enable with further outputs a reset signal R ₁₃ and the shift signal SH ₄ by shifting a predetermined time Set the signal to high level.

When the latch circuit 13 receives the latch signal L ₅ , it latches the count value C ₁ output from the counter circuit 12. The shift circuit 14 is connected to the latch circuit 13
The latch data C ₂ inputted from the 1/2 multiplied as the output signal C _3. Thus, by the high level of the enable signal the output of the shift signal SH _4, the count value C ₁ of the next time becomes 1/2 of the latch data C ₂ is a threshold.

The counter circuit 12 outputs a reset signal R
Reset at ₁₃ and restart counting the number of reference clocks.

Here, the period of the leading part (high level) 41a is T _H , and C ₁ = C from the start of the period of the following part 41b.
The period of ₃ until it comes to a T _L, the period T _D from the rise 41c of the preceding portion 41a until C ₁ = C ₃
Becomes _TD = _TH + _TL . Also, T _H = 2T _L. Therefore, the threshold is

[0093]

(Equation 3) Becomes That is, when the duty is 66.7% or less, the rising edge 42 of the next reproduction control signal 42
Before c, C ₁ ≧ C ₃ , and the output signal C ₄ of the magnitude comparison circuit 15 becomes high level. At this time, the enable signal is high level, the discrimination threshold signal C ₅ is a high level. Then, the data flip-flop 17 sets the duty determination result C ₆ to a high level according to the sampling signal SA ₂ output when the sequencer 11 detects the next rising edge 42 c of the reproduction control signal 42.

Thus, the reproduction control signal 4
It can be seen that the duty of 1 is smaller than 66.7%.

[0095] On the other hand, the next reproduction control signal 42, as in the case of playback controls signal 41 described above, the sequencer 11, the rising edge 42c of the reproduced control signal 41 outputs the reset signal R ₁₄ (same time the sampling signal SA ₈ Is also output), and the enable signal is set to low level. Subsequently, the latch signal L ₆ , the reset signal R _15, and the shift signal SH ₅ are output at the falling edge 42 d, and the enable signal is set to high level.

Since the duty of the reproduction control signal 42 is greater than 66.7%, C ₁ <C ₃ at the next rising edge 42 c of the reproduction control signal 42, and therefore the output signal C _{4 of the} magnitude comparison circuit 15. Goes low. Accordingly, since the determination threshold signal C ₅ becomes low, the duty determination result C ₆ also becomes a low level.

Thus, the reproduction control signal 4
It can be seen that the duty of 1 is greater than 66.7%.

As described above, according to the duty discriminating circuit of this embodiment, a threshold value different from that of the first embodiment can be obtained without changing the reference clock.

(Embodiment 3) Next, a third embodiment of the present invention will be described.

FIG. 6 is a block diagram showing a duty determination circuit according to this embodiment. The duty discriminating circuit of the present embodiment does not include the shift circuit of FIG.
This is different from the first and second embodiments described above. Therefore, the shift signal is not output from the sequencer 11.

FIG. 7 is a specific circuit diagram of a sequencer without such a shift circuit. Since there is no need to generate a shift signal, parts related to the shift circuit are omitted, and the circuit configuration is omitted. Is very simple. 7, the same components as those in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

The construction of each of the other parts 12, 13, 15 to 17 is the same as in the first embodiment.

FIG. 8 is a timing chart showing the operation of the duty discrimination circuit. Also here,
The leading portions 61a and 62a of the reproduction control signals 61 and 62 for one cycle are set to the high level, and the following portions 61b and
The case where 62b is at the low level will be described as an example.

In this embodiment, when the sequencer 11 detects the rising edge of the reproduction control signal, it outputs a sampling signal and a reset signal, sets the enable signal to low level, and detects the falling edge of the reproduction control signal. The latch signal and the reset signal are sequentially output, and when C ₁ ≧ C ₂ , the reset signal is output and the enable signal is set to a high level.

The operation of the duty discriminating circuit according to this embodiment will be described below.

[0106] First, the sequencer 11 detects the rise 61c of the reproduced control signal 61, and outputs a sampling signal SA ₁₀ and the reset signal R _17, the enable signal to the low level. The counter circuit 12
Is reset by the reset signal R _17, starts counting the number of reference clocks.

[0107] Next, the sequencer 11 detects a fall 61d of the reproduced control signal 61, first outputs a latch signal L _7, further outputs a reset signal R ₁₈ are shifted by a predetermined time.

[0108] The latch circuit 13 latches the output and count value C ₁ of the entering counter circuit 12 outputs a latch signal L _7. The counter circuit 12 is reset by a reset signal R _18, again counting the number of reference clocks.

Thereafter, when the count value C ₁ output from the counter circuit 12 increases to satisfy C ₁ ≧ C ₂ , the magnitude comparison circuit 1
5 is an output signal C ₄ to a high level.

[0110] The sequencer 11, when the signal C ₄ is at high level, the enable signal to the high level and outputs a reset signal R _19. At this time, since the reproduction control signal 61 is at low level, the enable signal is set to high level.

[0111] The counter circuit 12 is reset by a reset signal R _19, again counting the number of reference clocks. In addition,
At this time, the output signal C ₄ of the magnitude comparison circuit 15 becomes the low level again. Therefore, even when the enable signal is at a high level, the discrimination threshold signal C ₅ to the output of the AND circuit 16, remains at a low level.

Here, the period of the leading part (high level) 61a is T _H , and the period of the trailing part 61b is C
T _{L1 is} a period until ₁ = C _3, and T _{L1 is} a period from reset by the reset signal R ₁₉ until C ₁ = C _3.
When _L2, period T _D from rising 61c until C ₁ = C ₃ a second time preceding portion 61a becomes _{T D = T H + T L1} + T L2. Also, T _H = T _L1 = T _L2 . Therefore,
The threshold is

[0113]

(Equation 4) Becomes That is, when the duty is 33.3% or less, the rising edge 62 of the next reproduction control signal 62
Before c, C ₁ ≧ C ₃ , and the output signal C ₄ of the magnitude comparison circuit 15 becomes high level. At this time, the enable signal is high level, the discrimination threshold signal C ₅ is a high level. Then, the data flip-flop 16, the sequencer 11 in accordance with the sampling signal SA ₁₁ to be output when it detects a rising edge 62c of the next reproduced control signal 62, to the duty determination result C ₆ to a high level.

In this manner, the reproduction control signal 6
It can be seen that the duty of 1 is smaller than 33.3%.

[0115] On the other hand, the next reproduction control signal 62, as in the case of playback controls signal 61 described above, the sequencer 11, the rising edge 62c of the reproduced control signal 61 outputs the reset signal R ₂₀ (simultaneously sampling signal SA ₁₁ Is also output), and the enable signal is set to the low level. Subsequently, the latch signal L ₈ and the reset signal R ₂₁ are output at the falling edge 62d. Further, when the count value C ₁ output from the counter circuit 12 increases and again becomes C ₁ ≧ C ₃ , the sequencer 1
1 is an enable signal to the high level resets the count value C ₁ and outputs a reset signal R _22.

Since the duty of the reproduction control signal 62 is larger than 33.3%, C ₁ <C ₃ at the next rising edge 63c of the reproduction control signal 62, and therefore the output signal C _{4 of the} magnitude comparison circuit 15 is obtained. Goes low. Accordingly, since the determination threshold signal C ₅ becomes low, the duty determination result C ₆ also becomes a low level.

In this way, the reproduction control signal 6
It can be seen that the duty of No. 2 is larger than 33.3%.

In the duty discriminating circuit shown in FIG. 1, the same sequence control as that of the present embodiment is performed (that is, the shift circuit 14 is not used or the magnification is set to 1). Of course, the same duty determination can be performed. Therefore,
The shift circuit stores the latch data by two according to the shift signal.
^-n (n is zero or a natural number).

As described above, according to the duty discriminating circuit of this embodiment, it is possible to obtain a threshold value different from those of the first and second embodiments by using the same reference clock as in the first and second embodiments.

[0120]

As described in detail above, according to the present invention, it is possible to provide a duty discriminating circuit capable of setting a threshold value to an optimum value with a simple circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a duty determination circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a sequencer shown in FIG.

FIG. 3 is a timing chart illustrating an example of a circuit operation of the duty determination circuit illustrated in FIG. 1;

FIG. 4 is a timing chart showing another example of the circuit operation of the duty determination circuit shown in FIG.

FIG. 5 is a timing chart illustrating an example of a circuit operation of a duty determination circuit according to a second example of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a duty determination circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of the sequencer shown in FIG.

FIG. 8 is a timing chart illustrating an example of a circuit operation of the duty determination circuit illustrated in FIG. 5;

FIG. 9 is a block diagram illustrating a configuration example of a conventional duty determination circuit.

FIG. 10 is a timing chart illustrating an example of a circuit operation of the duty determination circuit illustrated in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Sequencer 12 Counter circuit 13 Latch circuit 14 Shift circuit 15 Size comparison circuit 16 AND circuit 17 Data flip-flop

────────────────────────────────────────────────── (5) Continuation of the front page (51) Int.Cl. ⁶ identification code FIG11B 27/28 A (56) References JP-A-3-229164 (JP, A) JP-A-2-194722 (JP, A) JP-A-63-236990 (JP, A) JP-A-63-149877 (JP, A) JP-A-63-113366 (JP, A) JP-A-5-307056 (JP, A) (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11B 15/087 101 G11B 27/28 G01R 29/02 H03K 5/04 H03K 5/153

Claims (5)

(57) [Claims] A duty discriminating circuit for discriminating a magnitude relation between a duty of an information signal whose level periodically changes and a threshold value, wherein a time of a leading part and a following part of the information signal are detected by counting a reference clock. A shift circuit that shifts the preceding partial time data (binary number) obtained by the counter circuit by a factor of 2− ⁿ (n is zero or a natural number) and outputs the result; A determination circuit for determining a determination point by comparing the time of a succeeding portion of the information signal with the provisional threshold value using the shift data obtained as a provisional threshold value, and an output point of the determination circuit And an output circuit for outputting a duty determination signal based on a relationship with a portion. 2. A duty discriminating circuit for discriminating a magnitude relation between a duty of an information signal whose level periodically changes and a threshold value, wherein a preceding part of the information signal is detected to output a sampling signal, and a succeeding part is outputted. , A latch signal is output, a reset signal is output by detecting both portions, and a sequencer that outputs a shift signal for obtaining an optimal threshold value.The sequencer is reset by the reset signal and counts a reference clock. A counter circuit that performs counting; a latch circuit that latches count data counted as preceding partial time data by the counter circuit in accordance with the latch signal; and a latch circuit that is latched by the latch circuit based on the shift signal output from the sequencer. the 2 ^-n by the shift of the count data bits ⁽ⁿ is zero or a natural number) is shifted to double A shift circuit for outputting, the shift data output from the shift circuit being compared with the count data output from the counter circuit as a temporary threshold value, and a comparison result when the count data is larger than the shift data. A duty discrimination circuit, comprising: a comparison circuit that outputs a signal; and an output circuit that outputs the comparison result signal as a discrimination result signal based on a level of the information signal and a sampling signal. 3. The duty discriminating circuit according to claim 2, wherein said output circuit outputs said comparison result signal with respect to said information signal input in a previous cycle in response to input of said sampling signal. . 4. The duty discriminating circuit according to claim 2, wherein the sequencer outputs a second shift signal when a signal indicating a traveling direction of the signal indicates a reverse direction due to a fall of a leading portion of the information signal. A duty discrimination circuit for obtaining a threshold value close to a desired value by a combination of shift data values obtained by the shift signal and the second shift signal. 5. A duty discriminating circuit for discriminating a magnitude relation between a duty of an information signal whose level changes periodically and a threshold value, wherein a preceding signal of said information signal is detected to output a sampling signal, and a succeeding signal is output. , A latch signal is output, a sequencer that detects both parts and outputs a reset signal, a counter circuit that is reset by the reset signal and counts a reference clock, and is used as preceding partial time data by the counter circuit A latch circuit that latches the counted data according to the latch signal, and compares the latch data output from the latch circuit with the count data output from the counter circuit.
A comparison circuit that outputs a comparison result signal when the count data is larger than the latch data; and an output circuit that outputs the comparison result signal as a determination result signal based on a level of the information signal and a sampling signal. Duty discrimination circuit.