JPH04182968A - Maximum likelihood decoding control system - Google Patents

Abstract

PURPOSE:To improve the error rate of decoding without increasing a circuit scale by executing the max. likelihood decoding by two-stage constitution of a 1st Viterbi decoder and a 2nd Viterbi decoder. CONSTITUTION:This system has the 1st Viterbi decoder 1 which makes temporally max. likelihood decoding of a sample value by an AD converter (A/D) 3 of the signal subjected to waveform interference and the 2nd Viterbi decoder 2 which makes max. likelihood decoding by being inputted with the output of this 1st Viterbi decoder 1 and the sample value. The interference quantity by the future quantity to the data of the present point of the time is estimated by using the output of the 1s Viterbi decoder 1 and the interference quantity by the past data to the data of the present point of the time is estimated by the contents of a path memory, by which the tentative sample value is determined. Decoding processing is executed by using this tentative sample value and the sample value. Two stages of error correction decoding are eventually executed in this way and the error rate is improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a maximum likelihood decoding control method for maximum likelihood decoding of a signal subjected to waveform interference, the present invention takes into account waveform interference due to past data as well as waveform interference due to future data. In a maximum likelihood decoding control method in which a signal subjected to waveform interference is decoded by a maximum likelihood decoding method with the aim of improving the decoding error rate, the first method is to perform maximum likelihood decoding using sample values of the signal. a Viterbi decoder; and a second Viterbi decoder that inputs the output of the first Viterbi decoder and the sample value and performs maximum likelihood decoding; Estimate the amount of interference caused by future data to the current data using the output of the Viterbi decoder 1, and estimate the amount of interference caused by past data to the current data based on the contents of the bus memory to obtain a hypothetical sample value; The decoding process is configured to be performed using the hypothetical sample value and the sample value.

[Industrial Application Field] The present invention relates to a maximum likelihood decoding control method for maximum likelihood decoding of a signal subjected to waveform interference.

In magnetic recording devices such as magnetic disk devices, reproduction signals are decoded using maximum likelihood decoding to improve error rates. The maximum likelihood decoding method selects and decodes the most probable data from a hypothetical data string, and a Viterbi decoder is commonly used.

[Prior Art] The configuration of a demodulation system in a conventional example of a magnetic recording device is, for example, a sixth
In the figure, 61 is a magnet for reproducing recorded data from a recording medium such as a magnetic disk, 62 is an amplifier, and 63 is a magnet.
is an equalizer, 64 is a pulse circuit, 65 is a phase locked loop (PLL), 66 is an equalizer, and 67 is an AD converter (
A/D), 68 is a Viterbi decoder.

The reproduced signal from the magnetic head 61 is amplified by an amplifier 62, equalized and amplified by equalizers 63 and 66 including filters, and subjected to noise removal, etc., and a pulse is formed by peak detection in a pulse generator 64. A clock signal that is phase-synchronized with the reproduced signal is obtained by the phase synchronization circuit 65, and this clock signal becomes a sampling clock signal of the AD converter 67, and the reproduced signal equalized by the equalizer 66 is sampled in the AD converter 67. , the sample values of the reproduced signal are applied to a Viterbi decoder 68 and decoded.

The Viterbi decoder is known as a maximum likelihood decoder for convolutional codes, and for example, as shown in FIG.
ACS circuits 72-1 to 72-4, bus memory 73,
It includes a normalization circuit 74 and a bus selector 75,
The branch metric value is calculated by the distributor 71 and the AC
It is distributed to S circuits 72-1 to 72-4. These ACS circuits 72-1 to 72-4 are provided in 2 k-1 pieces, where k is the constraint length of the convolutional code, and FIG. 7 shows the case where the constraint length is 3. become.

Further, each of the ACS circuits 72-1 to 72-4 has an adder (
A), a comparator (C), and a selector (S), the branch metric value and the previous path metric value are added by the adder (A), and compared by the comparator (C), and the bus metric value is The smaller value is selected by the selector (S) as the path metric value of the surviving bus, and the bus selection signal at that time is added to the bus memory 73. It has a bus memory cell, is stored as a surviving bus, and the output of the final stage is added to the bus selector 75, and a decoded output is obtained by majority vote processing or the like. In addition, when the path metric value is converted to a number of digits that cause an overflow, the normalization circuit 74 normalizes the path metric value.

When such a Viterbi decoder is used to decode a signal subjected to waveform interference, the ACS circuit calculates and compares the sum of the square of the error between the assumed sample value and the actual sample value and the previous path metric value. Then, the smaller one of the new path metric values of the addition output is selected as the next path metric value, and the selection information is added to the bus memory 73.

FIG. 8 shows a trellis diagram with a constraint length of 3, where solid arrows indicate transitions when input data is "0", dotted arrows indicate transitions when input data is "1'', and circles indicate internal states. For example, , the hypothetical sample values at buses PO and PL are shown in (a) of Fig. 9.
, [Yes]) can be set as y2° + ypl.

This value is obtained by waveform interference of the 3-bit hypothetical bus (a-+, ao, al) shown as the current value in (a) of FIG. Let g be the sample value according to the bit period, and let the constraint length be m−(
k-1)/2. Therefore, if '/ po + V pl is the constraint length = 3, then
Since m=1, the value is obtained from equation (1) for the range from i-1 to i=+1.

If interference from past data is also considered, it can be determined by using the path memory values (bz, tz, . . . ) as follows.

FIG. 10 is a block diagram of the main part of a conventional example in which interference from past data is taken into consideration based on the above-mentioned equation (2).
It is equipped with an S circuit 81, a path memory 82, a bus selector 83, and a hypothetical bus memory 84.
It is added to the S circuit 81. The path memory 82 and the hypothetical bus memory 84 have a shift register configuration capable of storing "1", "0", and "l I 11", and the ACS circuit 8
1 calculates and compares the squared output of the difference between the assumed sample value and the actual sample value and the previously calculated path metric value, and selects the smaller one. The value is input to the path memory 82.

Therefore, although the value in the path memory 82 is not the most probable decoded value, it is the most probable value at that point in time as being connected to the hypothetical bus. Also, the bus selector 83 is
The minimum value of the path metric value at that point in time is detected, the path that leads to that state is selected, and the last data is used as the decoded output. Further, the arrow connecting the path memory 82 and the hypothetical bus memory 84 indicates that multiplication and addition are performed, as shown in equation (2).

[Problem to be solved by the invention]

As mentioned above, by also considering interference from past data, accurate hypothetical sample values can be estimated. However, when considering the path one bit ahead, for example, assuming that the buses following bus PO in the trellis diagram of FIG. 8 are POO and PIO, the assumed sample value is (b) in FIG. , y shown in (e). . +)'p+. Therefore, if the amount of interference is not taken into account when the future data is "1", the error of the assumed sample value will be large. increase,
It is necessary to accurately estimate the amount of interference. However, since the circuit scale of the decoder is proportional to 2k, increasing the constraint length k requires an enormous circuit scale and is difficult to implement.

Furthermore, in a decoding method that takes into account interference caused by past data, such as the conventional example shown in FIG. It is necessary to perform special equalization to This special equalization is a major obstacle in practical application of magnetic disk drives and the like in which the amount of interference differs for each magnetic recording track.

The present invention aims to improve the decoding error rate by considering waveform interference due to past data as well as waveform interference due to future data.

[Means to solve all problems]

The maximum likelihood decoding control method of the present invention uses the output of the preceding Viterbi decoder to estimate and decode the amount of interference in the front of the hypothetical bus in the subsequent Viterbi decoder. Refer to and explain.

A first Viterbi decoder l that temporarily performs maximum likelihood decoding using a sample value obtained by an AD converter (A/D) 3 of a signal subjected to waveform interference, and an output of this first Viterbi decoder 1 and the sample value. The second Viterbi decoder 2 inputs and performs maximum likelihood decoding, and the second Viterbi decoder 2 uses the output of the first Viterbi decoder 1 to calculate future data for the current data. Estimate the amount of interference caused by the data, and estimate the amount of interference caused by past data with respect to the current data based on the contents of the path memory to obtain a hypothetical sample value, and perform decoding processing using this hypothetical sample value and the sample value. It is something.

In addition, the metric value from the ACS circuit of the first Viterbi decoder 1 is input to the ACS circuit of the second Viterbi decoder 2, and the output of the final stage of the path memory of the first Viterbi decoder 1 is input to the ACS circuit of the second Viterbi decoder 1. This is input to the calculation section for hypothetical sample values to be added to the ACS circuit of the Viterbi decoder 2.

[Operation] According to claim 1, maximum likelihood decoding is performed by the second Viterbi decoder 2 using the provisional decoded value subjected to error correction decoding by the first Viterbi decoder 1, and the decoding is performed in two stages. Since error correction decoding is performed, the error rate can be improved. The second Viterbi decoder 2 uses the temporary decoded value from the first Viterbi decoder 1 to estimate the amount of interference caused by future data and calculates a hypothetical sample value. Accurate hypothetical sample values can be obtained without increasing the length. Therefore, the error rate can be improved.

In claim 2, the output of the final stage of the bus memory of the first Viterbi decoder 1 is not selected and used as the decoded output, but the output of the final stage is inputted to the second Viterbi decoder 2, This is used to estimate the amount of interference caused by future data. In addition, the metric value from the ACS circuit of the first Viterbi decoder 1 is input to the ACS circuit of the second Viterbi decoder 2, and is added in the metric calculation to facilitate comparison of the metric values. .

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a magnetic head, 12 is an amplifier, 13.16 is an equalizer, 1
4 is a pulse circuit, 15 is a phase locked loop (PLL), 1
7 is an AD converter (A/D), 18.19 is the first . The second Viterbi decoder, 20, is an error correction decoder.

The signal reproduced by the magnetic head 11 from a recording medium such as a magnetic disk is subjected to waveform interference, and this reproduced signal is amplified by the amplifier 12 and equalized and amplified by the equalizer 13, which includes a filter and the like. At the same time, noise removal, etc. are performed, and the pulse is generated by peak detection in the pulse generator 14 and applied to the phase synchronization circuit 15. From the phase synchronization circuit 15, a clock signal synchronized with the reproduced signal phase is sent to the AD converter 17. Added. AD converter 1
7 samples the reproduced signal from the equalizer 16 according to the timing of this clock signal, and the sample value is 1. It is added to a second Viterbi decoder 18,19.

The first Viterbi decoder 18 includes an ACS circuit, a bus memory, a bus selector, and a hypothetical bus memory, performs decoding processing in the same manner as in the conventional example, and uses the decoded output as a temporary decoded value. The second Viterbi decoder 19 uses this provisional decoded value to estimate the amount of interference from the front of the hypothetical path and performs decoding processing. In this case, the temporary decrypted value and
It is necessary to match the phase with the sample value input to the second Viterbi decoder 19, but due to the length of the assumed path (constraint length) in the first Viterbi decoder 18 and the length of the bus memory. Since it is possible to determine the amount of delay by which a temporary decoded value is obtained, a phase matching configuration can be easily realized using a delay circuit such as a shift register.

The error correction decoder 20 is provided when the input signal is error correction coded, and performs error correction decoding on the decoded output of the first Viterbi decoder 18, and uses it as a temporary decoded value. , will be input to the second Viterbi decoder 19.

As described above, the first Viterbi decoder 18 performs error correction decoding, and the second Viterbi decoder 19 further performs error correction decoding, so that the error rate is improved.

As mentioned above, when considering interference by future data, the bit period sample (I!g r and the present 3 past and future bus values a
r, b1. The hypothetical sample value y is calculated using the following equation.

y=”i21g-4a, +,'z,,g-i
b, +, =〒g-,c.

...(3) FIG. 3 shows the main parts of the second Viterbi decoder 19 that performs the process of the above-mentioned formula (3), and 21 is a decoding section having the same configuration as the first Viterbi decoder 18; 22 is a shift register for shifting a temporary decoded value, 23 is a hypothetical bus memory, 24 is an ACS circuit, 25 is a bus memory, and 26 is a bus selector. Assuming shift register 22, bus memory 23 and bus memory 2
5 has a configuration capable of storing '1 "ZIIQ" Zll ll+, respectively. Further, the tentative decoded values from the first Viterbi decoder 18 are sequentially shifted to the shift register 22, and the sample values are input to the ACS circuit 24.

Assuming that the constraint length k (length of the assumed path) is 3, the 3 bits a-1, a O+ a l of the assumed path memory 23,
3 bits b2 of path memory 25. b3. b, and the 3 bits C-z, C-3, C-4 of the shift register 22 (
Using the time position of each bit (see Figure 9 (a)) and the sample value g of the isolated waveform (see Figure 9 (C) for the time position of the sample value), the assumed sample value y is (3)
It is obtained according to the formula, and the arrows indicate multiplication and addition.

FIG. 4 is a block diagram of the main part of the hypothetical sample calculation unit that calculates the hypothetical sample value y according to equation (3), in which 22 is a shift register, 23 is a hypothetical path memory, 25 is a path memory, and 31 to 39 are multipliers. , 40 is an adder. 3 bits C-a of the shift register 22 to which the temporary decoded value from the first Viterbi decoder 18 is added to the sample values g-a to g4 of the isolated waveform (see (C) in FIG. 9); C-3I
C-2 and hypothetical bus memory 2303 bits a-1+
aO+ a I and 3 bits b2 of the path memory 25. b, , b, are added to multipliers 31 to 39 and multiplied, and the output of each multiplier 31 to 39 is added to an adder 40, and the output of the adder 40 is applied to the ACS circuit 24 as a hypothetical sample value y. This is what is entered in the . And A
In the CS circuit 24, the difference from the sample value is determined.

That is, a hypothetical sample value y is obtained that takes into account interference due to past data and interference due to future data.

FIG. 5 is a block diagram of main parts of another embodiment of the present invention,
41.42 is a shift register, 43 is a hypothetical path memory,
44 is an ACS circuit, 45 is a path memory, 51 is a first Viterbi decoder, 52 is a second Viterbi decoder, 53 is a hypothetical path memory, 54 is an ACS circuit, 55 is a path memory, 56
is a bus selector, and 57 is a shift register.

The sample value is input to the ACS circuit 44 of the first Viterbi decoder 51, and based on the contents of the hypothetical path memory 43, (1
), or the contents of the path memory 45 are also used to obtain the assumed sample value according to equation (2), and the squared output of the difference between the sample value and the assumed sample value is calculated from the previous metric value. The sum is determined and compared,
The smaller one is selected as the next metric value, the metric value is input to the ACS circuit 54 of the second Viterbi decoder 52 via the shift register 42, and the selection information is added to the path memory 45. The output of the final stage is input to the shift register 57 of the second Viterbi decoder 52. The sample value is also input to the ACS circuit 54 of the second Viterbi decoder 52 via the shift register 41.

The shift registers 41 and 42 are connected to the first Viterbi decoder 51.
The second Viterbi decoder 52 acts as a delay circuit for phase matching between
It is selected according to the length of the

In the second Viterbi decoder 52, the shift register 5
Based on the contents of 7, the contents of the assumed path memory 53, and the contents of the path memory 55, an assumed sample value is calculated by multiplication and addition according to equation (3), as shown by the arrow, and the ACS The circuit 54 outputs the square of the difference between this hypothetical sample value and the sample value input via the shift register 41, and the sum of the previous metric value and the metric value input via the shift register 42. are determined and compared, and the smaller value is selected as the next metric value. Therefore, the values of the path memory 45 that are possible decoded values of the first Viterbi decoder 51 and the metric value indicating the probability thereof are transferred to the second Viterbi decoder 52, and the sample values are transferred to the second Viterbi decoder 52. Since maximum likelihood decoding is performed, the error rate is improved.

The present invention is not limited to the above-mentioned embodiments, but can also be applied to decoding signals subjected to waveform interference other than reproduction signals of magnetic recording devices.

[Effects of the Invention] As explained above, the present invention provides the first Viterbi decoder 1
Maximum likelihood decoding is performed using a two-stage configuration of a second Viterbi decoder 2 and a second Viterbi decoder 2, and waveform interference from data corresponding to the future from the assumed path is predicted without increasing the constraint length.
Because it is possible to obtain more accurate hypothetical sample values,
There is an advantage that the decoding error rate can be improved without increasing the circuit scale.

In addition, in the conventional example in which only waveform interference from past data is considered, special equalization is required to remove waveform interference from data corresponding to the future, making it difficult to realize a practical configuration. However, according to the present invention, there is no need for such special equalization, which has the advantage of facilitating practical implementation.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Part 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of main parts of an embodiment of the invention, and Fig. 4 is a diagram of the assumed sample value calculation section. Main part block diagram, Fig. 5 is a main part block diagram of another embodiment of the present invention, Fig. 6 is a main part block diagram.
The figure shows a conventional example. 7 is a block diagram of the Viterbi decoder, FIG. 8 is a trellis diagram with a constraint length of 3, FIGS. 9(a) to (e) are explanatory diagrams of signal waveforms, and FIG. FIG. 1 is the first Viterbi decoder, 2 is the second Viterbi decoder, 3
is an AD converter (A/D).

Claims (2)

[Claims] (1) In a maximum likelihood decoding control method in which a signal subjected to waveform interference is decoded by a maximum likelihood decoding method, a first Viterbi decoder (1) temporarily performs maximum likelihood decoding using sample values of the signal; , a second Viterbi decoder (2) that inputs the output of the first Viterbi decoder (1) and the sample value and performs maximum likelihood decoding, the second Viterbi decoder (2) The output of the first Viterbi decoder (1) is used to estimate the amount of interference due to future data to the current data, and the amount of interference due to past data to the current data is estimated based on the contents of the path memory. A maximum likelihood decoding control method, characterized in that a hypothetical sample value is obtained by using the hypothetical sample value, and a decoding process is performed using the hypothetical sample value and the sample value. (2) The metric value from the ACS circuit of the first Viterbi decoder (1) is converted into the A of the second Viterbi decoder (2).
input to the CS circuit, and the first Viterbi decoder (1)
2. The maximum likelihood decoding control system according to claim 1, wherein the output of the final stage of the path memory is inputted to a calculation section for hypothetical sample values to be added to the ACS circuit of the second Viterbi decoder (2).