JP2953859B2 - Delay flip-flop circuit with reset - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay flip-flop with reset, and more particularly to an ECL (Emitter).
The present invention relates to a reset-equipped delay flip-flop constituted by a Coupled Circuit.

[0002]

2. Description of the Related Art The conventional delay flip-flop with reset shown in FIG. 4 resets by taking a logical sum of a clock and a reset. 4, a power supply terminal V _CC , a data input terminal Data, a data inversion input terminal is an inversion Data, a clock input terminal CLK, a clock inversion input terminal is an inversion CLK, and a reset signal input terminal R.
eset, forward output Q, and inverted output are inverted Q, and Q1 to Q
22 is an NPN transistor, R1 to R4 are resistors, I1 to I
Reference numeral 9 denotes a constant current source.

A reset circuit for performing a logical sum of Reset (reset) and CLK (clock) between NPN transistors Q21 and Q22 and a constant current source I9, NPN transistors Q1 to Q9, resistors R1 and R2, and constant current sources I2 to I4. Thus, a latch circuit with reset (hereinafter, referred to as a master side) that latches input Data (data), NPN transistors Q12 to Q19 that output Data output from the master side at a high level of CLK, a resistor, A latch circuit (hereinafter, referred to as a slave side) composed of R3, R4 and constant current sources I6 to I8, and an NPN transistor Q11 and a constant current source I5 to shift the level of the inverted clock input to both the master side and the slave side. Clock inverting input circuit.

In order to reset the delay flip-flop circuit with reset, in the circuit shown in FIG. 4, the voltage at the node _VA is made higher than the voltage at _VH , and the NPN transistors Q3, Q6, Q9 on the master side are further turned on. The output of the master is reset by turning on the Q9 of the three differential transistors, and the NPN transistors Q12 and Q1 of the slave are received in response to the reset output of the master.
The reset is performed by turning on the NPN transistor Q19 of the nine differential transistors.

[0005]

Next, problems in the conventional configuration will be described with reference to the circuit diagram of FIG. 4 and the timing charts of FIGS. Data, CLK, inverted CLK, R
Eset, _{VA to VH} , Q, and inverted Q are represented by symbols in the circuit diagram shown in FIG. First, the manner of resetting when CLK = high level will be described with reference to FIGS. Initial state: Data = low level, CLK = low level, inverted C
LK = high level, Reset = low level, Q = low level, and inverted Q = high level. When CLK = high level, Data is read and Q = high level (FIG. 5 (Q)). When CLK = high level and Reset = high level, V _A > V _H , and the reset voltage on the master side only needs to be a voltage (V _D +0.1 V or more) at which the transistor Q9 conducts.
Since the current flows to the side, V _C = low level, V _B = high level, and V _D = low level and V _E = high level are reset. V _D = low level for the slave side which is conductive Q18 is, Q by being a V _E = high
Since 19 is conductive a current flows to the side of R4, V _F = high level, V _G = low level, Q = low level, the inverted Q =
It goes to the high level and enters the reset state. That is, when the CLK = high level state, the reset time (t _reset ) is the time t _Q9 during which the base voltage of Q ₉ becomes V _D +0.1 V and becomes conductive, and the time t _Q19 and Q 16 at which the slave switches Q 12 and Q 19 differentially. It is represented by a delay time t _Q16 . t _reset = t _Q9 + t _Q19 + t _Q16 (1) Next, the way of resetting when CLK = low level is V _A <V _H because the inverted CLK = high level in the circuit shown in FIG. When Reset = high level in this state, V _A > V _{H first} , and Q
9 conducts, causing a current to flow to the R2 side, and V _B = high level,
When V _C = low level, V _D = low level, V _E = high level, the master side is reset, and upon receiving the master side output, the slave side Q19 conducts and a current flows through the R4 side, and V _F = high level , V _G = low level, Q = low level, Q = high level, and reset is applied.
During this reset time, Reset rises from a low level to a high level, and the emitter voltages of the differential transistors Q21 and Q22 rise from _VA < _VH to _VA > _VH + 0.
The delay time (t _A ) until it becomes 1 V, and V _A > V _H +
It is represented by a delay time (t _Q2 ) from the time when the voltage becomes 0.1 V until Q2 becomes conductive and t _Q9 , a time when the differential transistors of Q12 and Q19 on the slave side are switched, and a delay time of Q16. _{reset = t a + t Q2 +} t Q9 + t Q19 + t Q16 ...... it is (2).

When Δt _reset is obtained by subtracting (1) from (2), Δt _reset = t _A + t _Q2 ... (3), and a time difference appears when CLK = high level or low level during the reset time. There was a problem.

[0007]

A feature of the present invention is a flip-flop circuit in which latch circuits are successively connected in two stages, wherein the latch circuit has a first NPN transistor for inputting data to a base. A third NPN transistor having an emitter commonly connected to an emitter of a second NPN transistor for inputting inverted data to a base, a collector of the first NPN transistor connected to a base, and a collector connected to a power supply terminal; A fourth NPN transistor connecting the collector of the second NPN transistor to the base and connecting the collector to a power supply terminal, and a fifth NPN transistor connecting the emitter of the third NPN transistor to the base.
NPN transistor, a sixth NPN transistor connecting an emitter of the fourth NPN transistor to a base, a fifth NPN transistor and a sixth NPN transistor.
A seventh connecting the collector to the common emitter of the transistor and inputting the clock (or inverted clock) to the base
An NPN transistor, an eighth NPN transistor having a collector connected to a common emitter of the first NPN transistor and the second NPN transistor, and inputting a clock (or inverted clock) to a base;
Connected between the ground terminal and the node between the emitter of the NPN transistor and the base of the fifth NPN transistor.
A second constant current source connected between a node between the emitter of the fourth NPN transistor and the base of the sixth NPN transistor and a ground terminal, and the seventh NP
A third constant current source connected to a common emitter of the N transistor and the eighth NPN transistor;
A first resistor commonly connected to the collectors of the PN transistor and the sixth NPN transistor and the base of the third NPN transistor, the other end of which is connected to a power supply terminal, and one end connected to the second NPN transistor; A second terminal commonly connected to the collector of the fifth NPN transistor and the base of the fourth NPN transistor and the other end connected to the power supply terminal;
, The emitter of the third NPN transistor is a non-inverting output, the emitter of the fourth NPN transistor is an inverting output, and the non-inverting output of the preceding latch circuit is the data input terminal of the subsequent latch circuit. In a delay flip-flop circuit in which an inverted output is connected to an inverted data input terminal and a clock or inverted clock input terminal of a preceding latch circuit and a subsequent latch circuit are commonly connected, a base is reset (or inverted clock). ), The ninth NPN transistor having the emitter connected to the fourth constant current source, the collector connected to the power supply terminal, and the base connected to the emitter of the ninth NPN transistor and the fourth constant current source. Commonly connected, and collectors of the second NPN transistor and the fifth NPN transistor Are commonly connected, the emitter the seventh
And a tenth NPN transistor connected to a common emitter of the eighth NPN transistor and the eighth NPN transistor, respectively, in the preceding latch circuit and the subsequent latch circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a delay flip-flop circuit with reset according to an embodiment of the present invention. The master side has a data input terminal Data, and the data inverting input terminal has an inverted Data,
A clock input terminal CLK, a clock inversion input terminal is an inverted CLK, a reset signal input terminal Reset, a normal output Q, an inverted output is an inverted Q, and NPN transistors Q1 to Q2.
1, resistors R1 to R4 and constant current sources I1 to I9,
Input data is latched by N transistors Q1 to Q9, resistors R1 and R2, and constant current sources I1 to I3. NPN transistors Q12 to Q20 for outputting data output from the master side at the high level of clock CLK, resistor R3,
The level of the non-inverted input of the clock CLK is shifted by the NPN transistor Q21 and the constant current source I9, and the inverted input of the clock CLK is shifted by the NPN transistor Q10 and the constant current source I4. A clock input circuit for level-shifting, and a reset signal Reset by an NPN transistor Q10 and a constant current source I4.
and a reset signal input circuit for level-shifting t.

First, how resetting is performed when CLK = high level will be described. FIG. 2 shows a timing chart at that time. CLK = high level and Data =
The high level is read and Q = high level. When Reset = high level in this state, the master side sets R
The voltage obtained by level-shifting the esest signal by Q10 is V _I
Then, V _I > V _A , the NPN transistor Q9 conducts, and a current flows to the resistor R2 side, and V _B = high level, V _C = low level, V _D = low level, V _E = high level, and the master becomes Reset on the side. Since V _I > V _A on the slave side, the NPN transistor Q2
0 conducts, V _F = high current flows on the side of the resistor R4, V _G = low level, Q = low level, the reset and become slave inverted Q = high level such. Since the master and the slave are reset at the same time, the time required for the reset to be reset is V _I > V _{A as shown} by the equation (4), and the NPN transistor Q18
To switch to NPN transistor Q20 from time t
_{Q18 →} and _Q20, the delay time of the NPN Torajisuta Q ₁₆ t _Q16
And the sum of t _reset = t _{Q18 → Q20} + t _Q16 (4) Next, how to perform reset when CLK = low level will be described. FIG. 3 shows a time chart at that time. The high level of Data is read when CLK = high level, and Q = high level is held even when CLK = low level. When Reset = high level in this state, V _I > V _H on the master side, the NPN transistor Q9 conducts, and current flows to the resistor R2 side, and V _B =
High level, V _C = low level, V _D = low level, V
_E = high level, resetting the master side.
Since the slave side is V _I> V _H electric current on the side of the resistor R4 by NPN transistor Q20 conducts, V _F = high level, V _G low, Q = low level, the slave becomes inverted Q = high Is reset. Since the reset is applied simultaneously on the master side and the slave side, the time required until the reset is applied is V _I > V _H and the NPN transistor Q
It is represented by a time t _{Q14 → Q20 from} the time of switching from 14 to the NPN transistor Q20, and a delay time of the NPN transistor Q16. t _reset = t _{Q14 → Q20} + t _Q16 …… (5) If Δt _reset is calculated by −, then Δt _reset = t _{Q14 → Q20} −t _{Q18 → Q20} …… (6), but t _{Q14 → Q20} and t _{Q18 → Since Q20} is the switching time of two of the three differential transistors of the NPN transistors Q14, Q18 and Q20, _{tQ14 → Q20} = _{tQ18 → Q20} (7) Therefore, Δt _reset = 0 ... (8), and the reset time is constant regardless of CLK = high level and low level.

[0010]

As described above, the delay flip-flop circuit with reset of the present invention has an N-N between the collectors of the transistors Q6 and Q8 of the master side latch circuit and the constant current source I2.
PN transistor Q9 is connected to power supply terminal VCC and constant current source I
An NPN transistor Q10 is connected between the four, a reset signal is input to the base, and the emitter is connected to the bases of the NPN transistors Q9 and Q20. An NPN transistor Q20 is connected between the transistors Q1 and Q19 of the slave side latch circuit and the constant current source I7, and an NPN transistor Q1 is connected between the power supply terminal VCC and the constant current source I5.
1 and an inverted clock signal is input to the base and the emitters are connected to the bases of the NPN transistors Q7 and Q14, respectively. Further, the NPN transistor Q1
A reset signal is input to the base of the power supply 0, the collector is connected to the power supply terminal VCC, and the emitter is connected to the constant current source I4 and the bases of the NPN transistors Q9 and Q20.

The NPN transistors Q9, Q10, Q
When the clock signal is at a high level, the time required for resetting is the time t _{Q18 → Q20 for} switching from the NPN transistor Q18 to Q20.
The sum of the delay time t _Q16 of the NPN transistor Q16 t
_reset = _{tQ18 → Q20} + _tQ16, and when the clock signal is low level, the NPN transistors Q14 to Q2
T _{Q14 → Q20} switching to 0 and NPN transistor Q
Sum of 16 delay times t _reset = t _{Q14 → Q20} + t _Q16
Therefore, the difference is Δt _reset = t _{Q14 → Q20} -t
_{Q18 → Q20} .

However, the NPN transistors Q14, Q1
8, Q20 is a three differential transistor circuit, so t
_The switching time between _{Q14 → Q20} and _{tQ18 → Q20} is equal,
Therefore, Δt _reset becomes 0, which has an effect that the resetting time is constant regardless of whether the clock signal is at a high level or a low level.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a flip-flop circuit with reset of the present invention.

FIG. 2 is a timing chart when a reset is applied when CLK is at a high level in the circuit shown in FIG. 1;

FIG. 3 is a timing chart when a reset is applied when CLK is at a low level in the circuit shown in FIG. 1;

FIG. 4 is a circuit diagram showing an example of a conventional flip-flop circuit with reset.

5 is a timing chart when a reset is applied when CLK is at a high level in the circuit shown in FIG. 4;

FIG. 6 is a timing chart when a reset is applied when CLK = low level in the circuit shown in FIG. 4;

[Explanation of symbols]

Q1～Q22 NPN transistor I1~I9 constant current source Reset reset signal R ₁ to R ₄ the resistance CLK clock signal Q output VCC supply terminal

Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 3/289

Claims (1)

(57) [Claims] 1. A flip-flop circuit comprising two latch circuits connected in cascade, said latch circuit including an emitter of a first NPN transistor for inputting data to a base and a flip-flop circuit for inputting inverted data to a base. A third NPN transistor having a common connection with the emitters of the second NPN transistor, a collector of the first NPN transistor connected to a base, and a collector connected to a power supply terminal; and a collector of the second NPN transistor. A fourth NPN transistor connected to the base and a collector connected to the power supply terminal, a fifth NPN transistor connected to the base of the emitter of the third NPN transistor, and a base connected to the emitter of the fourth NPN transistor; Connecting a sixth NPN transistor, the fifth NPN transistor and a sixth NP A seventh NPN transistor having a collector connected to a common emitter of the N transistors and a clock (or inverted clock) input to a base, and a collector connected to a common emitter of the first and second NPN transistors; An eighth NPN transistor for inputting a clock (or an inverted clock) to the base, a first NPN transistor connected between a node between the emitter of the third NPN transistor and the base of the fifth NPN transistor, and a ground terminal. A constant current source, a second constant current source connected between a node between the emitter of the fourth NPN transistor and the base of the sixth NPN transistor and a ground terminal, the seventh NPN transistor and an eighth A third constant current source connected to the common emitter of the NPN transistor;
One end is connected to the first NPN transistor and the sixth NP
A first resistor commonly connected to the collector of the N transistor and the base of the third NPN transistor, and the other end connected to the power supply terminal; and one end connected to the collectors of the second and fifth NPN transistors. And the fourth
A second resistor connected in common with the base of the NPN transistor of the third type and the other end connected to the power supply terminal.
The emitter of the PN transistor is set to the non-inverting output, and the fourth
The inverting output of the NPN transistor is connected to the data input terminal of the preceding latch circuit, the inverted output of the NPN transistor is connected to the data input terminal of the following latch circuit, and the inverted output of the preceding latch circuit is connected to the inverted data input terminal. In a delay flip-flop circuit in which input terminals of a circuit clock or an inverted clock are commonly connected, a base is used as a reset (or inverted clock) input terminal,
A ninth NPN transistor having an emitter connected to the fourth constant current source, a collector connected to the power supply terminal, and a base connected to the ninth NPN transistor.
, And the collector is commonly connected to the collectors of the second and fifth NPN transistors, and the emitter is connected to the seventh NPN transistor. And a tenth NPN transistor connected to a common emitter of an eighth NPN transistor in the preceding-stage latch circuit and the subsequent-stage latch circuit, respectively.