JPH05275982A - Delay flip flop circuit with reset - Google Patents

Abstract

PURPOSE:To fix the time required for reset in the master part and the slave part of a delay flip flop with reset in the case of the high level as well as the low level of a clock signal. CONSTITUTION:A transistor TR Q10 is connected between collectors of TRs Q6 and Q8 on the master side and a constant connected source 12, and a TR Q20 is connected between collectors of TRs Q17 and Q19 on the slave side and a constant current source 17, and a reset signal is inputted to bases of these TRs Q10 and Q20, and TRs Q10 and Q20 have collectors connected to a power terminal VCC and have emitters connected to a constant current source 14 and have bases connected in common, thereby constituting a ternary logic circuit by the reset signal, a clock signal, and an inverted clock signal. Thus, the reset time is fixed whether the clock signal is in the high level or the low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay flip-flop with reset, and more particularly to an ECL (Emitter).
The present invention relates to a delay flip-flop with reset composed of a Coupled Circuit.

[0002]

2. Description of the Related Art A conventional delay flip-flop with reset shown in FIG. 4 is reset by taking a logical sum of a clock and a reset. 4, a power supply terminal V _CC , a data input terminal Data, a data inversion input terminal is an inversion Data, a clock input terminal CLK, a clock inversion input terminal is an inversion CLK, and a reset signal input terminal R.
reset, normal output Q, inverted output is inverted Q, Q1 to Q
22 is an NPN transistor, R1 to R4 are resistors, and I1 to I
Reference numeral 9 indicates a constant current source.

A reset circuit that takes a logical sum of Reset (reset) and CLK (clock) by NPN transistors Q21 and Q22 and constant current source I9, NPN transistors Q1 to Q9, resistors R1 and R2, and constant current sources I2 to I4. The latch circuit with reset (hereinafter referred to as the master side) that latches the input Data (data), the NPN transistors Q12 to Q19 that outputs the data output from the master side at the high level of CLK, and the resistor The latch circuit (hereinafter referred to as the slave side) composed of R3 and R4 and the constant current sources I6 to I8, and the NPN transistor Q11 and the constant current source I5 shift the level of the inverted clock input to both the master side and the slave side. And a clock inverting input circuit that operates.

In order to apply a reset in this delay flip-flop circuit with reset, the voltage at the node V _A is made higher than the voltage at V _{H in} the circuit shown in FIG. 4, and the NPN transistors Q3, Q6, Q9 on the master side are further provided. The output of the master side is reset by turning on Q9 of the three differential transistors, and the NPN transistors Q12 and Q1 of the slave side are received by receiving the reset output of the master side.
The NPN transistor Q19, which is a differential transistor of No. 9, is turned on to reset.

[0005]

Next, the problems in the conventional configuration will be described with reference to the circuit diagram of FIG. 4 and the timing charts of FIGS. Data, CLK, inverted CLK, R
eset, _{VA to VH} , Q, and inversion Q are based on the symbols in the circuit diagram shown in FIG. First, how to reset when CLK = high level in FIGS. 4 and 5 will be described. Initial state is Data = low level, CLK = low level, inverted C
LK = high level, Reset = low level, Q = low level, inversion Q = high level. When CLK = high level, Data is read and Q = high level (FIG. 5 (Q)). When CLK = high level and Reset = high level, V _A > V _H is originally satisfied, and the reset voltage on the master side has only to be a voltage (V _D +0.1 V or more) at which the transistor Q9 conducts, and at that time, the resistance R2.
Since a current flows to the side, V _C = low level, V _B = high level, V _D = low level, V _E = high level reset state. On the slave side, since Q18 is conducting, V _D = low level and V _E = high level
Since 19 is conductive, a current flows to the side of R4, V _F = high level, V _G = low level, Q = low level, inversion Q =
It becomes high level and is in the reset state. That is, when CLK = high level, the reset time (t _reset ) is the time t Q9 when the base voltage of Q9 becomes V _D +0.1 V and the time t _Q9 is conductive and the switching time t _Q19 and Q16 of the slave side Q12 and Q19 differential. It is represented by the delay time t _Q16 . t _reset = t _Q9 + t _Q19 + t _Q16 (1) Next, when CLK = low level, in the circuit shown in FIG. 6, since the inverted CLK = high level, _VA <V _H , When Reset = high level in the state, first V _A > V _H , and on the master side, Q
9 conducts, current flows to the R2 side, V _B = high level,
When V _C = low level, V _D = low level, V _E = high level, the master side is reset, Q19 on the slave side receives the output from the master side, the current flows to R4 side, and V _F = high level , V _G = low level, Q = low level, inversion Q = high level, and reset is applied.
At the reset time at this time, Reset rises from the low level to the high level, and the emitter voltages of the differential transistors of Q21 and Q22 are V _A <V _H to V _A > V _H +0.
Delay time (t _A ) until reaching 1 V and V _A > V _H +
It is represented by the delay time (t _Q2 ) from when the voltage becomes 0.1 V to the conduction of _Q2 , t _Q9 , the time when the differential transistors of Q12 and Q19 on the slave side are switched, and the delay time of Q16. _reset = t _A + t _Q2 + t _Q9 + t _Q19 + t _Q16 (2).

[0006] (2) is from (1) by subtracting the seek Delta] t _reset when _{Δt reset = t A + t Q2} ...... (3), CLK = high level reset time, or low in that the time difference is out There was a problem.

[0007]

A feature of the present invention is a flip-flop circuit in which two stages of latch circuits are connected in cascade, wherein the latch circuit is a first NPN transistor for inputting data to a base. A third NPN transistor having the emitter and the emitter of a second NPN transistor for inputting inverted data input to the base connected in common, the collector of the first NPN transistor connected to the base, and the collector connected to a power supply terminal; A fourth NPN transistor connecting the collector of the second NPN transistor to the base and connecting the collector to the power supply terminal, and a fifth NPN transistor connecting the emitter of the third NPN transistor to the base.
NPN transistor, a sixth NPN transistor that connects the emitter of the fourth NPN transistor to the base, the fifth NPN transistor, and the sixth NPN transistor.
Seventh, connecting the collector to the common emitter of the transistor and inputting the clock (or inverted clock) to the base
NPN transistor, an eighth NPN transistor having a collector connected to the common emitter of the first NPN transistor and the second NPN transistor, and inputting a clock (or an inverted clock) to the base, and the third NPN transistor,
Connecting the node between the emitter of the NPN transistor and the base of the fifth NPN transistor and the ground terminal
Constant current source, a second constant current source connected between a node between the emitter of the fourth NPN transistor and the base of the sixth NPN transistor and the ground terminal, and the seventh NP
A third constant current source connected to a common emitter of the N transistor and the eighth NPN transistor, and one end of which is connected to the first N
A first resistor commonly connected to a PN transistor, a collector of the sixth NPN transistor, and a base of the third NPN transistor, and having the other end connected to a power supply terminal; one end connected to the second NPN transistor; A second common connection to the collector of the fifth NPN transistor and the base of the fourth NPN transistor, and the other end connected to the power supply terminal.
And the emitter of the third NPN transistor is a non-inversion output, the memitter of the fourth NPN transistor is an inversion output, and the non-inversion output of the latch circuit in the preceding stage is a data input terminal of the latch circuit in the subsequent stage. In addition, in the delay flip-flop circuit in which the inverted output is connected to the inverted data input terminal, and the clock or the inverted clock input terminal of the latch circuit in the preceding stage and the latch circuit in the subsequent stage are commonly connected, the base is reset (or the inverted clock). ), An emitter is connected to a fourth constant current source, a collector is connected to a power supply terminal, and a base is connected to the emitter of the ninth NPN transistor and the fourth constant current source. Commonly connected collectors of the second NPN transistor and the fifth NPN transistor Are commonly connected, the emitter the seventh
The NPN transistor and the tenth NPN transistor connected to the common emitter of the eighth NPN transistor are provided in the latch circuit in the front stage and the latch circuit in the rear stage, respectively.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of a delay flip-flop circuit with reset according to the present invention. The master side has a data input terminal Data and the data inversion input terminal has an inversion Data.
Clock input terminal CLK, inverted clock input terminal is inverted CLK, reset signal input terminal Reset, forward output Q, inverted output is inverted Q, NPN transistors Q1 to Q2
1, resistors R1 to R4, constant current sources I1 to I9, and NP
Input data is latched by N transistors Q1 to Q9, resistors R1 and R2, and constant current sources I1 to I3. NPN transistors Q12 to Q20 that output data output from the master side at a high level of the clock CLK, resistors R3,
The normal side input of the clock CLK is level-shifted by the slave side composed of R4 and the constant current sources I6 to I8, the NPN transistor Q21 and the constant current source I9, and the inverted input of the clock CLK is input by the NPN transistor Q10 and the constant current source I4. Of the reset signal Reset by the clock input circuit for level shifting the NPN transistor Q10 and the constant current source I4.
and a reset signal input circuit for level shifting t.

First, how to reset when CLK = high level will be described. The timing chart at that time is shown in FIG. CLK = High level and Data =
The high level is read and Q = high level. If Reset = high level in this state, R
The voltage obtained by level-shifting the estest signal by Q10 is V _I.
Then, V _I > V _A , the NPN transistor Q9 becomes conductive, and a current flows to the side of the resistor R2, V _B = high level, V _C = low level, V _D = low level, V _E = high level, and master. Reset takes place on the side. Since V _I > V _A on the slave side, NPN transistor Q2
0 becomes conductive, a current flows through the resistor R4, V _F = high level, V _G = low level, Q = low level, inversion Q = high level, and the slave side is reset. Since the master side and the slave side are reset at the same time, the time until the reset is seen from the slave side as shown in equation (4), V _I > V _A , and NPN transistor Q18
Time t from switching to NPN transistor Q20
_{Q18 →} and _Q20, the delay time of the NPN Torajisuta Q ₁₆ t _Q16
It is represented by the sum of and. t _reset = t _{Q18 → Q20} + t _Q16 (4) Next, how reset is applied when CLK = low level will be described. FIG. 3 shows a time chart at that time. The high level of Data is read when CLK = high level, and Q = high level is held even when CLK = low level. When Reset = high level in this state, V _I > V _H on the master side, the NPN transistor Q9 becomes conductive, and a current flows to the side of the resistor R2 V _B =
High level, V _C = low level, V _D = low level, V
_E = High level and reset on the master side.
Since V _I > V _H on the slave side, the NPN transistor Q20 conducts to cause a current to flow through the resistor R4 side, and V _F = high level, V _G low level, Q = low level, inversion Q = high level, and the slave side Resets. Since the master side and the slave side are reset at the same time, the time until the reset is seen from the slave side is V _I > V _H and the NPN transistor Q
It is represented by the time t _{Q14 → Q20} until switching from 14 to the NPN transistor Q20 and the delay time of the NPN transistor Q16. t _reset = t _{Q14 → Q20} + t _Q16 (5) _-When Δt _reset is calculated, Δt _reset = t _{Q14 → Q20} −t _{Q18 → Q20} … (6), but t _{Q14 → Q20} and t _{Q18 → Since Q20} is the switching time of two of the three differential transistors of NPN transistors Q14, Q18 and Q20, t _{Q14 → Q20} = t _{Q18 → Q20} (7) Therefore, Δt _reset = 0 ... (8) and the reset time becomes constant regardless of CLK = high level or low level.

[0010]

As described above, in the delay flip circuit with reset of the present invention, there is N between the collectors of the transistors Q6 and Q8 of the master side latch circuit and the constant current source I2.
The PN transistor Q9 is connected to the power supply terminal VCC and the constant current source I
An NPN transistor Q10 is connected between the four, a reset signal is input to the base, and the emitters are connected to the bases of the NPN transistors Q9 and Q20. An NPN transistor Q20 is provided between the transistor Q1 of the slave side latch circuit and the collector of Q19 and the constant current source I7, and an NPN transistor Q1 is provided between the power supply terminal VCC and the constant current source I5.
1 and the inverted clock signal is input to the base, and the emitters are connected to the bases of the NPN transistors Q7 and Q14, respectively. Furthermore, NPN transistor Q1
A reset signal is input to the base of 0, the collector is commonly connected to the power supply terminal VCC, and the emitter is commonly connected to the constant current source I4 and the bases of the NPN transistors Q9 and Q20.

The NPN transistors Q9, Q10, Q
By connecting 20, when the clock signal is at a high level, the reset time is the time t _{Q18 → Q20 at} which the NPN transistor Q18 switches to Q20.
The sum of the delay time t _Q16 of the NPN transistor Q16 t
_{When reset} = t _{Q18 → Q20} + t _Q16, and the clock signal is low level, NPN transistors Q14 to Q2
T _{Q14 → Q20} to switch to 0 and NPN transistor Q
Sum of 16 delay times t _reset = t _{Q14 → Q20} + t _Q16
Therefore, the difference is Δt _reset = t _{Q14 → Q20} −t
_{Q18 → Q20} .

However, NPN transistors Q14 and Q1
Since 8 and Q20 are three differential transistor circuits, t
_The switching times of _{Q14 → Q20} and t _{Q18 → Q20} are the same,
Therefore, Δt _reset becomes 0, which has the effect that the reset time is constant regardless of whether the clock signal is at the high level or the low level.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a flip-flop circuit with reset according to the present invention.

FIG. 2 is a timing chart when the circuit shown in FIG. 1 is reset when CLK is at a high level.

FIG. 3 is a timing chart when reset is applied when CLK is at a low level in the circuit shown in FIG.

FIG. 4 is a circuit diagram showing an example of a conventional flip-flop circuit with reset.

5 is a timing chart when reset is applied when CLK is at a high level in the circuit shown in FIG.

FIG. 6 is a timing chart when reset is applied when CLK = low level in the circuit shown in FIG.

[Explanation of symbols]

Q1～Q22 NPN transistor I1~I9 constant current source Reset reset signal R ₁ to R ₄ the resistance CLK clock signal Q output VCC supply terminal

Claims (1)

[Claims] 1. A flip-flop circuit formed by serially connecting two stages of latch circuits, wherein the latch circuit comprises a first NPN transistor for inputting data to a base and a first NPN transistor for inputting inverted data to a base. A second NPN transistor and a collector of the second NPN transistor are connected in common, the collector of the first NPN transistor is connected to the base, and the collector is connected to a power supply terminal. A fourth NPN transistor connected to the base and having a collector connected to the power supply terminal, a fifth NPN transistor connected to the base of the emitter of the third NPN transistor, and a base of the emitter of the fourth NPN transistor. A sixth NPN transistor connected to the fifth NPN transistor and a sixth NP A collector is connected to a common emitter of the N-transistor and a common emitter of the first NPN transistor and the second NPN transistor, and a seventh NPN transistor which inputs a clock (or an inverted clock) to a base. And an eighth NPN transistor for inputting a clock (or an inverted clock) to the base, and a first node connected between the node between the emitter of the third NPN transistor and the base of the fifth NPN transistor and the ground terminal. A constant current source, a second constant current source connected between the node of the emitter of the fourth NPN transistor and the base of the sixth NPN transistor and the ground terminal, the seventh NPN transistor and the eighth NPN transistor. A third constant current source connected to the common emitter of the NPN transistor,
One end is provided with the first NPN transistor and the sixth NP
A first resistor commonly connected to the collector of the N-transistor and the base of the third NPN transistor and having the other end connected to a power supply terminal, and one end of the second NPN transistor and the fifth NPN transistor collector And the fourth
A second resistor that is commonly connected to the base of the NPN transistor and has the other end connected to a power supply terminal.
The emitter of the PN transistor is a normal output, and the fourth
The NPN transistor emitter is used as an inverting output, the forward output of the latch circuit of the previous stage is connected to the data input terminal of the latch circuit of the subsequent stage, and the inverted output is connected to the inverted data input terminal of the latter stage, and the latch circuit of the previous stage and the latch of the latter stage In the delay flip-flop circuit in which the input terminals of the circuit clock or the inverted clock are commonly connected, the base is the input terminal of the reset (or the inverted clock),
A ninth NPN transistor having an emitter connected to a fourth constant current source and a collector connected to a power supply terminal, and a base connected to the ninth constant current source.
Of the NPN transistor are commonly connected to the fourth constant current source, the collector is commonly connected to the collectors of the second NPN transistor and the fifth NPN transistor, and the emitter is the seventh NPN transistor. A delay flip-flop circuit with reset, comprising: a latch circuit at the front stage and a latch circuit at the rear stage, and a tenth NPN transistor connected to a common emitter of an eighth NPN transistor.