JP2944573B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a trimming circuit, and more particularly to a trimming circuit capable of confirming an operation state after trimming before trimming.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram of a trimming circuit using a MOSFET described in Japanese Patent Application Laid-Open No. 4-243158. In FIG. 2, reference numeral 1 denotes a trimming circuit,
2 is a constant voltage circuit, 3 is a trimming data input circuit, 4
Indicates a decoder circuit. The wirings D, E, F of the trimming circuit 1 and the wirings of the same sign of the decoder circuit 4 are connected. FIG. 5 is a flowchart showing a procedure for performing preliminary confirmation of trimming adopted according to various trimming circuit methods and executing the trimming.

In the circuit shown in FIG. 2, first, in the preliminary confirmation stage, each of the wirings D, E, and F from the trimming circuit unit 1 is controlled according to the number of pulses input from the CLK terminal of the trimming data input circuit 3. When the control signal is supplied to the decoder circuit 4
ON, OF of 8 MOSFETs M27-34 through
F. As a result, the output voltage VR of the constant voltage circuit 2 is determined.

If the output voltage VR is within the target voltage range, the pad for resistance fusing in the trimming circuit 1 is fixed to fix the ON / OFF state of the control signal on the wirings D, E and F at that time. A large current is applied to a selected one of F1, F2, and F3, and MOSFETs M22, M2
4. A driving resistor R2 connected to the gate of M26.
1, trimming is performed by electrically fusing selected one of R22 and R23.

For example, if the output voltage VR enters the target voltage range when only the potential of the wiring D is at the Hi level and the others are at the Lo level in the prior confirmation stage, a large current flows through the pads F2 and F3 and R22 and R23 Fusing. That is, since the trimming can be executed after determining the optimum combination of the trimmings in advance, the actual trimming can be performed only once. That is, it follows the trimming procedure of FIG.

In this type of conventional trimming circuit, trimming is performed by selectively destroying a Zener diode or a polysilicon fuse resistor connected in parallel with the resistor, in addition to the one shown in FIG. There is something. 3 shows an example using a Zener diode, and FIG. 4 shows an example using a polysilicon fuse resistor.

When trimming is performed by the circuit of FIG.
Which of the Zener diodes D1 to D3 should be selected and destroyed depends on the trimming pads IN11 and IN12.
, IN12, IN13, etc., can be determined by short-circuiting in calculation. That is, the trimming can be performed after the optimum combination of the trimmings is determined by calculation in advance. Therefore, the actual trimming can be completed only once. That is, the trimming procedure shown in FIG. However, during the circuit operation, between IN11 and IN12,
The actual short circuit between IN12 and IN13 is
Although possible in principle, it is not practical because the circuit becomes complicated and leads to an increase in cost.

In the circuit of FIG. 4, prior confirmation in calculation is possible as in the circuit of FIG. However, since the trimming is performed by fusing the polysilicon fuse resistor, the state cannot be tested in advance.

As described above, in the trimming circuits shown in FIGS. 3 and 4, it is practically or in principle impossible to confirm the trimmed state in advance while the circuit is operating. There is. The circuit shown in FIG. 2 has significance as one solution to such a problem of the related art.

[0010]

However, in the circuit shown in FIG. 2, once the resistor has been blown, it cannot be returned to the original state. There is a problem that a circuit dedicated to the preliminary confirmation such as the data input circuit 3 is required, and an extra pad such as the data input pad CLK is required for such a circuit for the preliminary confirmation.

An object of the present invention is to provide a semiconductor integrated circuit having a trimming circuit without a dedicated circuit for prior confirmation of the trimming and an extra data input pad for the trimming without trimming. The later operation state can be confirmed.

[0012]

The object of the present invention is to provide a semiconductor integrated circuit comprising a constant voltage circuit and a trimming circuit for trimming the constant voltage circuit. Are arranged in correspondence with a plurality of serially connected control target elements to be trimmed and each of the control target elements, and have a first and a source and a drain connected to both ends of each control target element. Wherein the trimming circuit includes a set of a bipolar transistor and a second MOS transistor corresponding to each of the first MOS transistors, and an emitter of the bipolar transistor is grounded; A collector is connected to the gate of the first MOS transistor, and a base is connected to a constant current source and a control signal input pad. This is achieved by connecting the source of the second MOS transistor to the power supply potential, connecting the gate to the gate control potential, and connecting the drain to the gate of the first MOS transistor and the collector of the bipolar transistor. Is done.

In a trimming circuit according to a preferred embodiment of the present invention (hereinafter referred to as "the present circuit"), the constant voltage circuit includes a first MO in each of the serially controlled devices forming the output voltage dividing circuit.
S transistors are connected in parallel.
The output voltage VR of the constant voltage circuit is determined according to ON / OFF of the MOS transistor. In this case, the control target element to which the first MOS transistor maintained in the ON state is connected in parallel is trimmed, and the control target element in the OFF state is not trimmed.

In order to confirm which element to be controlled should be trimmed so that the output voltage VR of the constant voltage circuit falls within the target voltage range before actually performing the trimming, 0 V may be applied to the control signal input pad. . By doing so, 0
The bipolar transistor whose pad to which V is applied is connected to the base is turned off, the collector voltage of the bipolar transistor becomes Hi level, and the first MOS transistor whose collector is connected to the gate is turned on.
Therefore, the control target element to which the first MOS transistor is connected in parallel is in a trimmed state. When it is confirmed in advance which element should be trimmed in this way, next, trimming is executed to fix the trimming state.

When the trimming is performed, a voltage higher than the breakdown voltage is applied between the emitter and the base of the bipolar transistor corresponding to the first MOS transistor to be maintained in the ON state, and the bipolar transistor is destroyed to reduce hfe. By doing so, even if the pad connected to the base of the bipolar transistor is opened, the collector voltage becomes H
Fixed to i level. Therefore, the first MOS transistor whose collector is connected to the gate is fixed to the ON state, and the trimming is completed.

As described above, this circuit includes only circuits and pads that are indispensable for actually trimming the element to be controlled, and sharing these circuits and pads makes it difficult to check in advance. Can be done without.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention include the following (a) to (e). (A) The current driving capability of the constant current source and the gate control potential are set so that the current driving capability of the second MOS transistor is smaller than the current driving capability of the bipolar transistor when the control signal input pad is opened. .

(B) By opening the control signal input pad, the current of the constant current source is applied to the base of the bipolar transistor to turn on the bipolar transistor.
Then, a current corresponding to the current driving capability of the second MOS transistor, which is smaller than the current driving capability of the bipolar transistor, is caused to flow from the drain of the second MOS transistor to ground via the bipolar transistor, thereby forming the first MOS transistor. Turning off the transistor, thereby connecting the control target element to another control target element before and after without short-circuiting the control target element.

(C) applying a first potential to the control signal input pad to turn off the bipolar transistor;
By turning on the gate of the first MOS transistor,
Short-circuit both ends of the controlled element. In addition, the first potential is 0V.

(D) The second potential is applied to the control signal input pad to destroy the bipolar transistor, and the current driving capability of the bipolar transistor becomes relatively smaller than the current driving capability of the second MOS transistor. After that, the control signal input pad is released, and the power supply potential is
The first MOS transistor is turned on by inputting to the gate of the first MOS transistor via the second MOS transistor, thereby short-circuiting both ends of the control target element. Further, the second potential is a potential equal to or higher than the withstand voltage between the emitter and the base of the bipolar transistor.

(E) The element to be controlled is a resistor, and
The resistance element to be controlled is a trimming resistor.

The embodiment (a) relates to the setting of the current driving capability of the second MOS transistor and the bipolar transistor in the driving circuit of the first MOS transistor. The current driving capability of the second MOS transistor is determined by the gate control potential, and the current driving capability of the bipolar transistor when the control signal input pad is opened is determined by the current driving capability of the constant current source. In the present embodiment, the gate drive potential and the current drive capability of the constant current source are adjusted so that the current drive capability of the second MOS transistor becomes smaller than the current drive capability of the bipolar transistor when the control signal input pad is opened. Set.

With this arrangement, when the control signal input pad is opened, the collector current of the bipolar transistor becomes smaller than that of the second MOS transistor having a smaller current driving capability.
The drain current value of the transistor is limited to a value less than the drain current value. Therefore, the collector voltage of the bipolar transistor becomes Lo level, which is applied to the gate of the first MOS transistor, so that the first MOS transistor is turned off.

In contrast to the above, 0 is input to the control signal input pad.
When V is applied, the bipolar transistor
F state, the collector voltage becomes Hi level,
The first MOS transistor is turned on. Since this state corresponds to a state in which the control target element to which the first MOS transistor is connected in parallel is trimmed, the trimming state can be restored so as to be restored by the above operation.

The embodiment (b) relates to opening the control signal input pad in the state where the embodiment (a) is carried out. The operation of the present embodiment is as described above.

The embodiment (c) relates to applying 0 V to the control signal input pad in the state where the embodiment (a) is implemented. This embodiment describes a method of confirming the trimming in advance, and the operation is as described above.

The embodiment (d) relates to applying a potential equal to or higher than the emitter-base breakdown voltage of the bipolar transistor to the control signal input pad. As a result, the bipolar transistor is destroyed, and hfe decreases. This is an operation corresponding to execution of trimming.

The embodiment (e) describes that the element to be controlled is a resistance element, and in particular, the resistance element is an object to be trimmed.

[0029]

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing internal connections of a semiconductor integrated circuit (hereinafter, referred to as an “exemplary circuit”) as the present embodiment. The example circuit includes a trimming circuit 1 and a constant voltage circuit 2.

The trimming circuit 1 is a P-channel MOS transistor M referred to above as a second MOS transistor.
4, M5, M6, NPN transistors Q1, Q2, Q3 referred to as bipolar transistors above, constant current sources CI1, CI2, CI3, and a control signal input pad IN
1, IN2, IN3, and wirings D, E, and F, and the source of the P-channel MOS transistor has a power supply potential VDD.
, The gate is at the control potential VG, the drain is the wiring D, E,
F is connected to the collector of the NPN transistor, and the base of the NPN transistor is commonly connected to the constant current source and the control signal input pad, and the emitter is grounded.

The constant voltage circuit 2 includes an amplifier AMP1, resistors R1 to R5 constituting an output voltage dividing circuit, and N-channel MOS transistors M1, M2 and M3 whose sources and drains are connected in parallel to R1 to R3, respectively. And the gates of the N-channel MOS transistors M1, M2, M3 are connected to wirings D, E, F, respectively, and the amplifier AMP1
Is supplied with Vref as a (+) input, and a voltage obtained by dividing the output voltage VR by a predetermined division ratio as a (−) input. VR = Vref × (R1 + R2 + R3 + R
4 + R5) / (R1 + R2 + R3 + R4). The resistors R1 to R3 are targets of trimming, and the trimming can adjust VR to a desired value.

In the trimming circuit 1, the constant current sources CI1,
The current driving capabilities of CI2 and CI3 are I1 and NPN, respectively.
Control signal input pads IN1 and IN, where the collector current driving capability of transistors Q1, Q2 and Q3 is I2 (= hfe × I1), and the source / drain current driving capability of P-channel MOS transistors M4, M5 and M6 is I3.
2, the current driving capabilities I1 and P2 of the constant current sources CI1, CI2, and CI3 such that I3 <I2 when IN3 is open.
The gate control potential VG of the channel MOS transistors M4, M5, M6 is set.

By so doing, when the control signal input pad is opened, the collector current I2 of the NPN transistors Q1, Q2, Q3 is forced to have the same value as I3, so that the collector voltage becomes Lo level, and the gate is The N-channel MOS transistors M1, M2, M3 in the connected constant voltage circuit 2 are turned off. In this state, the resistors R1 to R3 are connected to other control target elements before and after without being short-circuited. That is, no trimming is performed in this state.

When the trimming is checked in advance, 0V is applied to the selected control signal input pad, and the base voltage of the corresponding one of the NPN transistors Q1, Q2, Q3 is set to 0V. Since the selected NPN transistor is turned off, the collector voltage of the selected NPN transistor becomes Hi level, and the corresponding one of the N-channel MOS transistors in the constant voltage circuit 2 is turned on. In this state, the corresponding one of the resistors R1 to R3 is short-circuited. That is, in this state, a temporary trimming state appears. As a result, it is possible to know beforehand the execution of the trimming whether the combination of the control signal input pads to which 0V is applied and the output voltage VR of the constant voltage circuit 2 becomes a desired value.

Next, when the trimming is executed, the base and NPN transistor of the NPN transistor are supplied from the corresponding control signal input pad by the combination confirmed in advance as described above.
By applying a voltage higher than the breakdown voltage between the emitters, the selected NPN transistor is destroyed and its hfe is reduced as shown in FIG. As a result, even if the control signal input pad is released, the collector voltage of the destroyed NPN transistor is maintained at the Hi level, so that the corresponding N-channel MOS transistor in the constant voltage circuit 2 is always turned on.
The state becomes N, and the trimming state is fixed.

In the above description, an NPN transistor has been described as a bipolar transistor.
Transistors can be used as well. In this embodiment, the case where the output voltage VR of the constant voltage circuit 2 is adjusted has been described. However, the same effect can be obtained even when the output voltage VR is used for zero adjustment of the input offset voltage of the OP amplifier.

[0037]

According to the present invention, the operation state after trimming can be confirmed before trimming without providing a circuit dedicated to the preliminary confirmation of the trimming or an extra data input pad therefor.

Further, the semiconductor integrated circuit according to the present invention includes an N-channel MOS transistor, an NPN transistor, a P-channel MOS transistor, a constant current source, and a trimming pad corresponding to the number of trimming target elements.
This can be realized with a smaller number of elements than in the conventional example. In particular, compared to a Zener diode or a method of trimming a polysilicon fuse resistor, one pad can be reduced in addition to the above advantages not possessed by these.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a conventional technique of trimming.

FIG. 3 is a circuit diagram showing a conventional technique for trimming a Zener diode.

FIG. 4 is a circuit diagram showing a conventional technique for trimming a polysilicon fuse resistor.

FIG. 5 is a process flow chart showing a trimming procedure.

FIG. 6 is an explanatory diagram of characteristics before and after trimming of the NPN transistor in the example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 trimming circuit 2 constant voltage circuit 3 trimming data input circuit 4 decoder circuit M1 to M3 N channel MOS transistor M4 to M6 P channel MOS transistor Q1 to Q3 NPN transistor CI1 to CI3 constant current source IN1 ~ IN3 ... Control signal input pad R1 ~ R5 ... Resistance AMP1 ... Amplifier

Claims (9)

(57) [Claims] 1. A semiconductor integrated circuit comprising: a constant voltage circuit; and a trimming circuit for trimming the constant voltage circuit, wherein the constant voltage circuit includes a plurality of control targets connected in series to be trimmed. And a first MOS transistor disposed corresponding to each of the control target elements and having a source and a drain connected to both ends of each control target element, wherein the trimming circuit includes the first MOS transistor. MO of 1
A set of a bipolar transistor and a second MOS transistor corresponding to each of the S transistors, wherein an emitter of the bipolar transistor is grounded;
A collector is connected to a gate of the first MOS transistor, a base is connected to a constant current source and a control signal input pad, a source of the second MOS transistor is connected to a power supply potential, and a gate is connected to a gate control potential. And a drain connected in common to a gate of the first MOS transistor and a collector of the bipolar transistor. 2. The current driving capability of the constant current source and the current driving capability of the bipolar transistor when the current driving capability of the second MOS transistor is smaller than the current driving capability of the bipolar transistor when the control signal input pad is opened. 2. The semiconductor integrated circuit according to claim 1, wherein a gate control potential is set. 3. The control signal input pad is opened to apply the current of the constant current source to the base of the bipolar transistor, thereby turning on the bipolar transistor.
N, causing a current according to the current driving capability of the second MOS transistor, which is smaller than the current driving capability of the bipolar transistor, to flow from the drain of the second MOS transistor to the ground via the bipolar transistor. Turns off the first MOS transistor
3. The semiconductor integrated circuit according to claim 2, wherein the control target element is connected to another element before and after without being short-circuited. 4. A bipolar transistor is cut off by applying a first potential to the control signal input pad, and the gate of the first MOS transistor is turned on to short-circuit both ends of the control target element. The semiconductor integrated circuit according to claim 1, wherein 5. The semiconductor integrated circuit according to claim 4, wherein said first potential is 0V. 6. A bipolar transistor is destroyed by applying a second potential to said control signal input pad, and the current driving capability of said bipolar transistor is made relatively higher than the current driving capability of said second MOS transistor. Then, the control signal input pad is opened, and the power supply potential is input to the gate of the first MOS transistor via the second MOS transistor, whereby the first MOS transistor is opened. 6. The semiconductor integrated circuit according to claim 1, wherein a transistor is turned on, thereby short-circuiting both ends of the control target element. 7. The device according to claim 1, wherein the second potential is a potential equal to or higher than an emitter-base breakdown voltage of the bipolar transistor.
A semiconductor integrated circuit according to claim 6. 8. The device according to claim 1, wherein said controlled element is a resistor.
8. The semiconductor integrated circuit according to any one of claims 7 to 7. 9. The semiconductor integrated circuit according to claim 1, wherein the resistance element to be controlled is a trimming resistor.