JP2937655B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for logic.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional logic semiconductor integrated circuit, and FIG.
Shown in Input terminals I000 to I003 are connected to inputs 1 to 4 of a 4-bit flip-flop B4.
CLK is an input clock, which is connected to the clock input 5 of the counter B3, flip-flops B4 and B13.
RST is an input reset, the input 1 of the inverter B2,
It is connected to the reset inputs 6 of the flip-flops B4 and B13. LOAD is a frame reset input and is connected to the load input 7 of the counter B3. CTL0-C
TL3 is drop input data, EXCLUSIVE
It is connected to input 2 of NOR (EX-NOR) gates B9 to B12. B1 is a clamp element whose output 001
Are connected to inputs 8, 9 of the counter B3. Also,
The output 002 is connected to the inputs 1 to 4 of the counter B3 and the inputs 4 of the multiplexers B5 to B8. Inverter B
2 is connected to input 6 of counter B3. Outputs 001 to 004 of the 4-bit flip-flop B4 are connected to inputs 2 of the multiplexers B5 to B8. Outputs 001 to 004 of the counter B3 are EX-NOR gates B9 to
It is connected to input 1 of B12. The output 001 of the EX-NOR gates B9 to B12 is 1 to 1 of the AND gate B14.
4 is connected. Output 001 of AND gate B14
Are connected to inputs 3 of multiplexers B5 to B8. The outputs 001 of the multiplexers B5 to B8 are connected to the inputs 1 to 4 of the flip-flop B13, respectively.
Outputs 001-00 of 4-bit flip-flop B13
4 is connected to output external terminals O000 to O003.
Outputs 005 to 008 are output from inverters B15 to B18.
Connected to input 1 of The output 001 of the inverters B15 to B18 is connected to the input 1 of the multiplexers B5 to B8.

[0003] Therefore, as shown in FIG.
003 from the output 00 of the counter B3.
When the values of 1 to 004 match the values of CTL0 to CTL3,
The data is transferred to the inputs 1 to 4 of the flip-flop B13, and the data of the output external terminals O000 to O003 is kept until the next match.

[0004]

In such a conventional semiconductor integrated circuit, since the counter B3 is a 4-bit counter, the value of the counter B3 coincides with the value of CTL0 to CTL3 when CLK is 2 ⁴ = Once every 16 clock cycles,
In order to confirm the data capture operation by changing the values of CTL0 to CTL from 0 to 15, 16 × 16 = 256 clocks are required, and the larger the number of bits is, the larger the test pattern becomes. Will be needed.

An object of the present invention is to provide a semiconductor integrated circuit capable of washing functions with a smaller number of patterns in an operation test of the semiconductor integrated circuit.

[0006]

A semiconductor integrated circuit according to the present invention has a first latch circuit for inputting a plurality of bits, a counter circuit that counts up periodically, an output of the counter circuit and a plurality of control inputs. A data input match detection circuit that detects and outputs when the two match, a gate circuit that passes the output of the data input match detection circuit only when a predetermined test value is input, A selector circuit that receives the outputs of the latch circuit and the gate circuit and holds the input data when the output of the gate circuit is "0" and outputs the input data when the output is "1"; and a plurality of bits input from the selector circuit. And a second latch circuit for outputting the same.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing waveforms of respective parts thereof. I
Input external terminals 000 to I003 are connected to data inputs 1 to 4 of a 4-bit flip-flop A4. CLK is a clock input and is connected to the clock A5 of the counter A3, flip-flops A4 and A13. RST is a reset input, and flip-flop A
4 and the reset input 6 of A13 and the input 1 of the inverter A2. Output 1 of inverter A2 is connected to input 6 of counter A3. LOAD is a frame reset input and is connected to the load input 7 of the counter A3. CTL0 to CTL3 are drop input data, and are connected to inputs 2 of EXCLUSIVE NOR (EX-NOR) gates A9 to A12. TEST is a test mode switching input, which is input 2 of OR gate A19.
Connected to A1 is a clamp element whose output 00
1 is connected to inputs 8, 9 of the counter A3. Also,
Output 002 is connected to inputs 1 to 4 of counter A3 and inputs 4 of multiplexers A5 to A8. Counter A3
Output 001-004 are EX-NOR gates A9-A1
2 is connected to input 1. EX-NOR gate A9 ~
Output 001 of A12 is connected to inputs 1 to 4 of AND gate A14, respectively. Output 0 of AND gate A14
01 is connected to the input 1 of the OR gate A19. OR
The output 001 of the gate A19 is connected to the multiplexers A5 to A8.
Is connected to input 3 of Outputs 001 to 004 of the 4-bit flip-flop A4 are supplied to multiplexers A5 to A8.
Connected to input 2 of The outputs 001 of the multiplexers A5 to A8 are respectively the input 1 of the flip-flop A13.
~ 4. Output 0 of flip-flop A13
01 to 004 are connected to output external terminals O000 to O003. The outputs 005 to 008 are output from the inverter A1.
5 to A18. Inverter A15
To the output 001 of the multiplexers A5 to A18, respectively.
Connected to input 1 of A8. Therefore, as shown in FIG. 2, when the TEST terminal is “0”, I000 to I003
Is input only when the outputs 001 to 004 of the counter A3 match the drop input data of the CTLs 0 to 3.
Data input 1-4 of 4-bit flip-flop A13
, And the data of the output external terminals O000 to O003 is retained until the next match. On the other hand, when the TEST terminal changes from “0” to “1”, the counter output and CTL
Even if the data of 0 to CTL3 do not match, since "1" is constantly input to the input 3 of the multiplexers A5 to A8, even if the data of CTL0 to CTL3 does not change, I
Drop the data of 000 to I003, and
003.

[0009]

As described above, according to the present invention, in an operation test of a semiconductor integrated circuit, when a large number of patterns are required, the function can be washed with a smaller number of patterns when a large number of patterns are required. Yes, the test pattern can be reduced, and the number of gates and external terminals of the test pattern circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a time chart showing waveforms at various parts in FIG.

FIG. 3 is a circuit diagram of a conventional semiconductor integrated circuit.

FIG. 4 is a time chart showing waveforms at various parts in FIG. 3;

[Description of Signs] A1 Clamp element A2, A15 to A18 Inverter A3 Counter A4, A13 Flip-flop A5 to A8 Multiplexer A9 to A12 EXCLUSIVE-NOR gate A14 AND gate A19 OR gate CTL0 to CTL3 Drop input data CLK Clock input I000 to I003 Input external terminal LOAD Frame reset input RST Reset input TEST Test mode switching input O000 to O003 Output external terminal

Claims (1)

(57) [Claims] 1. A first latch circuit for inputting a plurality of bits, a counter circuit that counts up periodically, and an output of the counter circuit and a plurality of control inputs are compared. A data input coincidence detection circuit, a gate circuit that allows the output of the data input coincidence detection circuit to pass only when a predetermined test value is input, and an output of the first latch circuit and the gate circuit. A selector circuit that holds input data when the output of the gate circuit is "0" and outputs input data when the output is "1"; and a second latch circuit that outputs a plurality of bits input from the selector circuit. A semiconductor integrated circuit characterized by the above-mentioned.