JP2936900B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2936900B2 JP2936900B2 JP4191254A JP19125492A JP2936900B2 JP 2936900 B2 JP2936900 B2 JP 2936900B2 JP 4191254 A JP4191254 A JP 4191254A JP 19125492 A JP19125492 A JP 19125492A JP 2936900 B2 JP2936900 B2 JP 2936900B2
- Authority
- JP
- Japan
- Prior art keywords
- lead pattern
- lead
- pattern
- semiconductor chip
- return current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体チップとリードフ
レームとを電気的に接続した際の寄生インダクタンスに
よる電気的ノイズの少ない半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having little electrical noise due to parasitic inductance when a semiconductor chip and a lead frame are electrically connected.
【０００２】[0002]
【従来の技術】半導体装置は大規模集積化に伴ない半導
体チップ面積が増加している。更に端子数増大や端子位
置の自由度を増したいとの要求から半導体チップとリー
ドフレームを接続する構造が最近変更されつつある。こ
の要求を満たす構造としてリードを半導体チップの上に
まで延長した構造（Ｌｅａｄ ｏｎ Ｃｈｉｐ構造、以
下ＬＯＣ構造と記す）がある。このＬＯＣ構造の一例は
特開平３−２２７５４１号公報に示されている。2. Description of the Related Art The area of semiconductor chips in semiconductor devices has increased with the integration of large-scale devices. Furthermore, the structure for connecting a semiconductor chip and a lead frame has recently been changed due to a demand for an increase in the number of terminals and a degree of freedom in terminal positions. As a structure that satisfies this requirement, there is a structure in which leads are extended above a semiconductor chip (Lead on Chip structure, hereinafter referred to as LOC structure). One example of this LOC structure is disclosed in Japanese Patent Application Laid-Open No. 3-227541.
【０００３】図５は、このような従来のＬＯＣ構造の半
導体装置のパッケージの長手方向に垂直な断面を示した
部分断面図である。半導体チップ１０はリードフレーム
のアイランド１１に載置・固定されている。リードには
半導体チップ上まで延びて半導体チップ表面に形成され
た絶縁層１５に接しているリードパターン１６を有し、
リードパターン１６と半導体チップ上のボンディングパ
ッド１４との間は、ボンディングワイヤ１３により電気
的に接続され、リードパターン１６，半導体チップ，ア
イランドが封止材にて封止されている。FIG. 5 is a partial cross-sectional view showing a cross section perpendicular to the longitudinal direction of a package of such a conventional semiconductor device having a LOC structure. The semiconductor chip 10 is mounted and fixed on the island 11 of the lead frame. The lead has a lead pattern 16 extending to above the semiconductor chip and in contact with an insulating layer 15 formed on the surface of the semiconductor chip,
The lead pattern 16 and the bonding pad 14 on the semiconductor chip are electrically connected by a bonding wire 13, and the lead pattern 16, the semiconductor chip, and the island are sealed with a sealing material.
【０００４】[0004]
【発明が解決しようとする課題】上記ＬＯＣ構造によれ
ば、半導体チップがリードフレームを含むパッケージに
入りきらないという問題は解決されるが、半導体チップ
上に長いリードパターンが存在することになる。最近の
半導体装置は、高集積化に伴ない半導体チップ内配線長
が長く寄生インダクタンスが大きくなっている。そして
高速駆動が要求されるため、リードを含めた寄生インダ
クタンスの増加は、見逃すことができなくなっている。
すなわち、リードを含めたある配線で駆動電流が流れる
と寄生インダクタンスの影響で不要な起電力が生じ、過
大な電流オーバーシュートや近傍の配線での入力信号レ
ベルのしきい値変動等の電気的ノイズが発生する。According to the above-mentioned LOC structure, the problem that the semiconductor chip cannot fit in the package including the lead frame is solved, but a long lead pattern exists on the semiconductor chip. Recent semiconductor devices have a long wiring length in a semiconductor chip and a large parasitic inductance as the degree of integration increases. Since high-speed driving is required, an increase in parasitic inductance including the lead cannot be overlooked.
That is, if a drive current flows through a certain wiring including a lead, an unnecessary electromotive force is generated due to the influence of parasitic inductance, and an electric noise such as an excessive current overshoot or a threshold fluctuation of an input signal level in a nearby wiring is generated. Occurs.
【０００５】本発明の目的は、上記の従来困難であった
半導体チップ上の長いリードパターンの寄生インダクタ
ンスによる電気的ノイズの発生を低減し、高速駆動でき
る半導体装置を提供することである。An object of the present invention is to provide a semiconductor device which can reduce the occurrence of electrical noise due to the parasitic inductance of a long lead pattern on a semiconductor chip and which can be driven at high speed, which has been difficult in the prior art.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体装置は、
リードフレームのリードが、絶縁層を介して半導体チッ
プ上に延在したリードパターンを有し、前記リードパタ
ーンと半導体チップ上のボンディングパッドとが電気的
に接続されたリードオンチップ構造の半導体装置におい
て、前記リードパターンに隣接して平行に戻り電流リー
ドパターンを備え、前記戻り電流リードパターンは、前
記リードパターンを取り囲むように前記リードパターン
の先端で折り返され、前記戻り電流リードパターンの先
端は前記リードパターンを挟んで前記戻り電流リードパ
ターンの根本とボンディングされていることを特徴とす
る。According to the present invention, there is provided a semiconductor device comprising :
The lead of the lead frame is connected to the semiconductor chip via the insulating layer.
A lead pattern extending over the lead pattern;
And the bonding pads on the semiconductor chip are electrically connected.
Semiconductor device with lead-on-chip structure connected to
And return current parallel to and adjacent to the lead pattern.
And the return current lead pattern is
The lead pattern so as to surround the lead pattern.
At the end of the return current lead pattern.
The end is the return current lead
It is characterized by being bonded to the root of the turn .
【０００７】[0007]
【実施例】以下、本発明について図面を参照して説明す
る。図１は本発明の参考例の半導体装置の部分断面図、
図２は封止材で封止する以前の部分平面図である。図１
の半導体装置は、図５の従来の半導体装置と同じく、半
導体チップ１０はアイランド１１の上に載置・固定さ
れ、リード１２に接続したリードパターン１６は半導体
チップ表面に設けた絶縁層１５上に延在し、このリード
パターン１６と半導体チップ上のボンディングパッド１
４とがボンディングワイヤ１３で電気的に接続され、こ
れらリードパターン１６、半導体チップ１０、アイラン
ド１１が封止材１７で埋め込まれている。本参考例は、
従来例とは違い、リードパターン１６の上に絶縁層２５
を介して新たに戻り電流リードパターン２６を備えてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a partial sectional view of a semiconductor device according to a reference example of the present invention,
FIG. 2 is a partial plan view before sealing with a sealing material. FIG.
5, a semiconductor chip 10 is mounted and fixed on an island 11, and a lead pattern 16 connected to a lead 12 is formed on an insulating layer 15 provided on the surface of the semiconductor chip. Extending the lead pattern 16 and the bonding pad 1 on the semiconductor chip.
The lead pattern 16, the semiconductor chip 10, and the island 11 are embedded with a sealing material 17. This reference example
Unlike the conventional example, the insulating layer 25 is formed on the lead pattern 16.
, A return current lead pattern 26 is newly provided.
【０００８】本参考例では一例として幅５００μｍ，厚
さ５０μｍ，長さ２ｍｍのＣｕ合金からなるリードパタ
ーン１６をリード１２に接続し、半導体チップ１０上に
設け、リードパターン１６上に厚さ３０μｍのポリイミ
ドからなる絶縁層２５を設け、この絶縁層２５上に幅３
００μｍ，厚さ５０μｍ，長さ２ｍｍの戻り電流リード
パターン２６をリード１２に接続して設けた。このとき
リードパターンの寄生インダクタンス値は、数値計算に
よる図４曲線４１の予測値と一致する実測値（長さＬ＝
２ｍｍにおいて約０．３ｎＨ）が得られた。この値は、
図４曲線４０で示す従来例での値に比べ約０．１倍に低
減されている。これは、戻り電流リードパターンをリー
ドパターン近傍に備えることにより、各リードパターン
の自己インダクタンスが相互インダクタンスで部分的に
相殺され、全体の寄生インダクタンスが減少するためで
ある。In this embodiment , as an example, a lead pattern 16 made of a Cu alloy having a width of 500 μm, a thickness of 50 μm and a length of 2 mm is connected to the lead 12, provided on the semiconductor chip 10, and has a thickness of 30 μm on the lead pattern 16. An insulating layer 25 made of polyimide is provided.
A return current lead pattern 26 having a size of 00 μm, a thickness of 50 μm, and a length of 2 mm was connected to the lead 12. At this time, the parasitic inductance value of the lead pattern is an actually measured value (length L =
About 0.3 nH at 2 mm) was obtained. This value is
The value is reduced to about 0.1 times the value in the conventional example shown by the curve 40 in FIG. This is because by providing the return current lead pattern near the lead pattern, the self-inductance of each lead pattern is partially offset by the mutual inductance, and the overall parasitic inductance is reduced.
【０００９】図３は本発明の実施例の部分平面図に電流
が戻るよう２本の戻り電流パターン２６を設けた。戻り
電流リードパターン２６の先端と根本（リード１２の近
傍）はボンディングワイヤ３３で結んだ。ここでリード
パターンは幅３００μｍ厚さ５０μｍ長さ２ｍｍであ
り、その左右両側に２００μｍの間隔をあけて幅３００
μｍの戻り電流パターン２６を同一平面上に備えた。ま
た、リードパターン及び戻り電流リードパターンはリー
ドと一体に形成した。このときのインダクタンスは、図
４の曲線４２に示すように、従来の場合より十分低い値
にできることが確認された。[0009] Figure 3 is provided with two return current pattern 26 so that the current returns to the partial plan view of the solid施例of the present invention. The tip of the return current lead pattern 26 and the root (near the lead 12) were connected by a bonding wire 33. Here, the lead pattern has a width of 300 μm, a thickness of 50 μm, and a length of 2 mm.
A μm return current pattern 26 was provided on the same plane. The lead pattern and the return current lead pattern were formed integrally with the lead. Inductance at this time is as shown in curve 42 of FIG. 4, it was confirmed that the sufficiently lower than the case of the traditional.
【００１０】本実施例ではリードパターン１６及び戻り
電流パターン２６とボンディングパッド１４との電気的
接続はボンディングワイヤ１３で行なったが、ボンディ
ングパッド１４の上にパターン１６，２６を伸ばし、ボ
ンディングパッド上で穴を空けはんだにより電気的接続
を行う場合も本発明は同様に有効である。In the present embodiment, the electrical connection between the lead pattern 16 and the return current pattern 26 and the bonding pad 14 is made by the bonding wire 13, but the patterns 16 and 26 are extended on the bonding pad 14 and The present invention is similarly effective when making holes and making electrical connection by soldering.
【００１１】[0011]
【発明の効果】図４に示した効果はリードパターン１６
と戻り電流リードパターン２６の距離をより近付けるこ
とにより大きくなる。また実施例においてリードパター
ン１６の左右両側の戻り電流リードパターン２６は左右
のうちいずれか片側でも構わないが両側に備えたものが
より効果がある。なお、参考例と実施例とを組み合わせ
て戻り電流リードパターンをリードパターンの左右上下
のいずれか複数位置に備える場合については、容易に類
推されるようにより優れた効果が得られる。以上、説明
したように本発明は半導体装置内のリードパターンに対
し戻り電流リードパターンを近接して備えることにより
寄生インダクタンスを減少し、半導体装置の高速駆動時
に発生する電気的誘導ノイズを低減するという効果を有
する。The effect shown in FIG.
When the distance between the return current lead pattern 26 and the return current lead pattern 26 is reduced, the distance increases. The left and right sides of the return current lead pattern 26 of Oite lead pattern 16 in Example is more effective ones but may be either of the left and right side with each side. In a case where the return current lead pattern is provided at a plurality of positions on the left, right, upper and lower sides of the lead pattern by combining the reference example and the embodiment , more excellent effects can be obtained as easily analogized. As described above, the present invention reduces the parasitic inductance by providing the return current lead pattern close to the lead pattern in the semiconductor device, and reduces the electric induction noise generated when the semiconductor device is driven at high speed. Has an effect.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の参考例の部分断面図。FIG. 1 is a partial cross-sectional view of a reference example of the present invention.
【図２】図１の半導体装置の部分平面図。FIG. 2 is a partial plan view of the semiconductor device of FIG. 1;
【図３】本発明の実施例の部分平面図。FIG. 3 is a partial plan view of the embodiment of the present invention.
【図４】本発明の実施例と従来例の寄生インダクタンス
の比較図。FIG. 4 shows a parasitic inductance according to an embodiment of the present invention and a conventional example.
Comparison diagram of.
【図５】従来例の部分断面図。FIG. 5 is a partial sectional view of a conventional example.
１０ 半導体チップ １１ アイランド １２ リード １３ ボンディングワイヤ １４ ボンディングパッド １５ 絶縁層 １６ リードパターン １７ 封止材 ２５ 絶縁層 ２６ 戻り電流リードパターン ３３ ボンディングワイヤ DESCRIPTION OF SYMBOLS 10 Semiconductor chip 11 Island 12 Lead 13 Bonding wire 14 Bonding pad 15 Insulating layer 16 Lead pattern 17 Sealing material 25 Insulating layer 26 Return current lead pattern 33 Bonding wire
Claims (1)
して半導体チップ上に延在したリードパターンを有し、
前記リードパターンと半導体チップ上のボンディングパ
ッドとが電気的に接続されたリードオンチップ構造の半
導体装置において、前記リードパターンに隣接して平行
に戻り電流リードパターンを備え、前記戻り電流リード
パターンは、前記リードパターンを取り囲むように前記
リードパターンの先端で折り返され、前記戻り電流リー
ドパターンの先端は前記リードパターンを挟んで前記戻
り電流リードパターンの根本とボンディングされている
ことを特徴とする半導体装置。1. A rie de frame leads, via an insulating layer
Having a lead pattern extending on the semiconductor chip,
In semi <br/> conductor arrangement of the lead-on-chip structure and the bonding pads on the lead pattern and the semiconductor chip are electrically connected, a current lead pattern back into parallel and adjacent to the front Symbol lead pattern, the Return current lead
The pattern is formed so as to surround the lead pattern.
Folded at the end of the lead pattern,
The leading end of the lead pattern is
A semiconductor device that is bonded to the root of a current lead pattern .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4191254A JP2936900B2 (en) | 1992-07-20 | 1992-07-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4191254A JP2936900B2 (en) | 1992-07-20 | 1992-07-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0637236A JPH0637236A (en) | 1994-02-10 |
| JP2936900B2 true JP2936900B2 (en) | 1999-08-23 |
Family
ID=16271481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4191254A Expired - Fee Related JP2936900B2 (en) | 1992-07-20 | 1992-07-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2936900B2 (en) |
-
1992
- 1992-07-20 JP JP4191254A patent/JP2936900B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0637236A (en) | 1994-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9905497B2 (en) | Resin sealing type semiconductor device and method of manufacturing the same, and lead frame | |
| JP2518569B2 (en) | Semiconductor device | |
| US5798571A (en) | Inductance reduced wire-bonding type semiconductor device | |
| US7511361B2 (en) | DFN semiconductor package having reduced electrical resistance | |
| JPH0815193B2 (en) | Semiconductor device and lead frame used for the same | |
| JP3286765B2 (en) | Semiconductor device | |
| JP2936900B2 (en) | Semiconductor device | |
| KR100390466B1 (en) | multi chip module semiconductor package | |
| JPH061801B2 (en) | Lead frame | |
| JP2601228B2 (en) | Method for manufacturing resin-sealed circuit device | |
| JP2969301B2 (en) | Semiconductor device | |
| JPH0529528A (en) | Semiconductor integrated circuit device and lead frame used for same | |
| KR100635386B1 (en) | Semiconductor chip package with high speed signal processing | |
| JP3702152B2 (en) | Semiconductor device | |
| JP2869596B2 (en) | Resin-sealed semiconductor device | |
| JPH05114685A (en) | Semiconductor device | |
| US7951651B2 (en) | Dual flat non-leaded semiconductor package | |
| WO2024034359A1 (en) | Semiconductor device | |
| JP2756436B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2629461B2 (en) | Resin-sealed semiconductor device | |
| KR0135672B1 (en) | Lead frame for semiconductor package | |
| KR0142756B1 (en) | Loc package | |
| JPS62169461A (en) | Semiconductor device | |
| JP2577880B2 (en) | Semiconductor device | |
| JPH0357259A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |