JP2936799B2 - Resin-sealed multi-chip package - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed multi-chip package in which a plurality of semiconductor chips such as MIS type integrated circuits or bipolar type integrated circuits are incorporated, and more particularly to a wiring board on which these semiconductor chips are mounted. The present invention relates to a resin-encapsulated multi-chip package having a substrate mounting portion in which a substrate is provided at the center.

[0002]

2. Description of the Related Art Conventionally, the above-mentioned resin-encapsulated multi-chip package (hereinafter simply referred to as a multi-chip package) is provided at a central portion by being supported by a suspension lead 3 as shown in FIG. A wiring board 5 on which a plurality of semiconductor chips 6a and 6b are mounted is mounted on the island 2, and the inner end faces in the horizontal and vertical directions around the island in substantially the same plane as the island 2, and the outer end faces. Are a plurality of inner leads 4 connected to external terminals (not shown).
Is provided. In this type of multi-chip package, the shape of the wiring board 5 is limited because the shape of the package must be reduced to a certain size or less due to mounting requirements, but the shape of the wiring board 5 is limited. When connecting to the inner leads located below the wiring board 5, a complicated lead wiring must be formed on the wiring board 5. In such a case, as shown in FIG. 7, a two-layer laminated substrate is employed to suppress an increase in the area of the wiring substrate 5. That is,
Relay electrode pads A to G and electrode pads a to g are provided on both upper and lower ends of a substrate 5a made of a green sheet of alumina or the like.
Are provided on the substrate 5b also made of a green sheet, and wirings I to VII for connecting the electrode pads A and a,..., G and g are provided. The electrode pads A to G and a to g are connected through through holes and fired to form the laminated wiring board 5. Then, as shown in FIG. 6, the electrode pads P to V of the semiconductor chip 6a and the relay electrode pads A to G of the substrate 5a are connected by wire bonding.
To g and the inner ends p to v of the inner leads 4 are connected by wire bonding, so that predetermined electrode pads of the semiconductor chip 6a at positions separated from each other and predetermined inner leads 4 are connected. (See, for example, JP-A-61-110460).

[0003]

However, in the above-mentioned multi-chip package, a laminated substrate must be used as a wiring substrate, so that the thickness of the wiring substrate is increased. As a result, there is a mounting problem that the thickness of the entire multi-chip package increases and the mounting volume increases, and if the thickness of the entire multi-chip package is reduced by reducing the thickness of the resin mold, the reliability of the semiconductor chip is reduced. It will spoil the nature. Further, by using an expensive laminated substrate, the cost of the wiring substrate is increased and the cost of the final integrated circuit component is increased. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide an inexpensive multi-chip package having a small overall thickness while maintaining the reliability of a resin-sealed semiconductor chip.

[0004]

SUMMARY OF THE INVENTION A feature of the present invention is to provide a substrate disposing portion for disposing a wiring substrate on which a plurality of semiconductor chips are mounted, and to surround the substrate disposing portion. In a resin-sealed multi-chip package including a lead frame having a plurality of inner leads each having an inner end facing each other and an outer end connected to an external terminal in substantially the same plane, at least a part of the inner leads Are extended to the substrate disposing portion, and the wiring substrate is placed and fixed on the upper surface thereof, and each extended inner end of the inner lead is placed on the electrode pattern on the wiring substrate or the wiring substrate. The present invention is characterized in that one of the predetermined electrode pads of the placed semiconductor chip is directly connected by wire bonding.

[0005]

In the resin-sealed multi-chip package of the present invention configured as described above, a part of the plurality of inner leads is extended to the portion where the substrate is provided, and the wiring substrate is mounted on the upper surface thereof. Because each inner end of the inner lead extended while being mounted and fixed was directly connected by wire bonding to either the electrode pattern on the wiring board or the electrode pad of the semiconductor chip mounted on the wiring board,
There is no need to form complicated wiring on the wiring substrate, and a single-layer substrate may be used as the wiring substrate, and it is no longer necessary to use a laminated substrate. As a result, the thickness of the wiring board can be reduced, and the thickness of the entire package can be reduced. As a result, the thickness of the integrated circuit component, which is a requirement from the mounting surface, has been reduced while maintaining the reliability of the semiconductor chip. can do. Furthermore, since an expensive laminated substrate is no longer required, the cost of the wiring substrate can be reduced, and the cost of the final integrated circuit component can be reduced.

In addition, since the wiring board is supported by the extended inner leads, an island for holding the wiring board and a suspension lead for supporting the island, which have been conventionally required, become unnecessary. A cutting die is not required, and the cut and vent process time can be shortened by eliminating the hanging lead cutting process. Further, since there is no need to provide relay electrode pads on the wiring substrate, the substrate area can be reduced, and the overall shape of the multi-chip package can be reduced, thereby reducing the mounting area of the final integrated circuit component. be able to. Also, since the relay electrode pad is no longer required, the distance between each inner end of the inner lead and the electrode pad of the semiconductor chip is reduced, and the bonding wire length can be reduced to an appropriate length. The reliability of wire bonding can be improved. Further, since wire bonding between the relay electrode pad of the wiring board and the semiconductor chip is not required, the number of wire bonding is reduced, and the number of wire bonding steps can be reduced.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an assembled state of a multi-chip package according to a first embodiment before resin sealing. In this multi-chip package, a lead frame 10 and a semiconductor integrated circuit chip (hereinafter, referred to as a semiconductor chip) are mounted. And a wiring board 20 for it. The lead frame 10
As shown in detail in FIG. 2, a plurality of inner leads 11 whose inner ends face each other in a horizontal direction and a vertical direction are provided in substantially the same plane around a substrate arrangement site K indicated by a virtual line, In addition, a tie bar 12 for integrally fixing each inner lead 11 and an external terminal 13 connected to an outer end of the inner lead 11 are provided. Then, inner lead 1
1 of inner leads 11A-
11F is extended upward and the inner lead 11G located at the lower right end is bent at a right angle and extended upward, and passes through the substrate mounting portion K, and each inner end is an upper inner lead 11W-1.
It is formed so as to be parallel to the inner end of 1Z in the same plane.

As shown in FIG. 1, the wiring board 20 includes semiconductor chip mounting pads 21 and 22 formed on a one-layer insulating substrate made of alumina or the like by a metallizing technique, and electrode pads of both semiconductor chip chips 31 and 32. There are twelve intermediate electrode pads 23 for connecting between them. The wiring board 20 is mounted on the board placement site K indicated by a virtual line of the lead frame 10 in FIG. As shown in FIG. 3, the mounting method of the wiring substrate 20 is as follows. (See (a), (b)). Wiring board 2 by dicing blade
0 is cut to a part of the sheet portion 41b (see FIG. 3 (b)), and the divided wiring substrate 20 is bonded to a predetermined substrate mounting portion K of the lead frame 10 by die bonding at the adhesive portion 41a (see FIG. 3B). (See FIG. 3 (c)). Note that a double-sided tape 41 may be attached to the substrate mounting portion K of the lead frame 10 and the wiring substrate 20 may be bonded thereto by die bonding. Alternatively, a highly viscous insulating paste may be applied on the lead frame 10. It may be applied, and the wiring substrate 20 is bonded by die bonding.

Next, an assembling process up to the formation of a package of the lead frame 10 on which the wiring board 20 is mounted will be described. As shown in FIG.
A conductive resin paste or the like is applied to the semiconductor chip mounting pads 21 and 22 and predetermined semiconductor chips 31 and 32 are bonded by die bonding. Next, the semiconductor chip 3
The electrode pads 1 and 32 and the inner leads 11 are connected by wire bonding. Furthermore, a resin-sealed integrated circuit as a final product is obtained through a resin molding step (not shown), cutting of tie bars and the like, and a bending step of external terminals. In the above assembling step, the outer electrode pads 31A to 31A of the semiconductor chip 31 mounted on the wiring board 20 are formed.
Since the G and the inner ends of the inner leads 11A to 11G are arranged close to each other, the electrode pads 31A to 31G and the inner ends of the inner leads 11A to 11G can be directly connected by wire bonding. For this reason, there is no need to form complicated wiring on the wiring substrate 20, and the wiring substrate 2
As 0, a one-layer substrate may be used, and it is not necessary to use a laminated substrate. As a result, the thickness of the wiring board 20 can be reduced, and the thickness of the entire package can be reduced. Therefore, while maintaining the reliability of the semiconductor integrated circuit, the thinning of the integrated circuit component, which is a demand from the mounting surface, is required. Can be achieved. Furthermore, since an expensive laminated board is no longer required, the cost of the wiring board 20 can be reduced, and the cost of the final integrated circuit component can be reduced.

In addition, since the wiring board 20 is supported by the extended inner leads, the conventionally required island for holding the wiring board and the suspension lead for supporting the island are not required. A cutting die is not required, and the cut and vent process time can be shortened by eliminating the hanging lead cutting process. Further, since it is not necessary to provide a relay electrode pad (see FIG. 6) between the semiconductor chip and the inner lead, which has been conventionally required, on the wiring substrate 20, the substrate area is reduced by about 25% as compared with the conventional example shown in FIG. Since the size can be greatly reduced and the overall shape of the multichip package can be reduced, the mounting area of the final integrated circuit component can be reduced, and the cost of the wiring board 20 can be reduced. Further, since the relay pad is not required, the distance between the inner end of the inner lead 11 and the electrode pad of the semiconductor chip 31 is reduced,
The bonding wire length, which was about 2.5 mm in the past, is 1.
Since the length can be reduced to an ideal length of about 5 mm, the reliability of wire bonding can be improved. Further, since wire bonding between the relay electrode pad of the wiring board 20 and the semiconductor chip, which is required in the related art, becomes unnecessary, the number of wire bondings can be reduced, and the number of wire bonding steps can be reduced.

Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, parts 11P to 11R of the inner lead 11 located at the upper part of the drawing are extended downward, and are formed in parallel on the same plane at the inner end of the inner lead 11 at the lower part of the drawing. did. By configuring the second embodiment in this manner, the wiring board 20 can be supported by the inner leads 11P to 11R in the same manner as in the first embodiment, and the outer electrode pads 32P to the lower semiconductor chip 32 can be supported. 32R and inner lead 11P ~
11R wire bonding can be performed directly.

Next, a third embodiment of the present invention will be described with reference to FIG. In the third embodiment, portions 11S to 11U of the upper and lower inner leads 11 in the drawing extend to a substantially intermediate position of the wiring board 20, and further, the wiring board around the inner end of the extended inner lead 11 Opening 2 at 20
0a was formed. By configuring the third embodiment as described above, the wiring board 20 can be supported by the inner leads 11S to 11U as in the first embodiment, and the electrode pads 31T, inside the semiconductor chips 31, 32 can be supported. Wire bonding with the inner leads 11S to 11U at positions distant from 31U and 32S can be performed directly.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing an assembled state of a lead frame and a wiring board of a multi-chip package according to one embodiment of the present invention.

FIG. 2 is an overall plan view of the lead frame.

FIG. 3 is a view showing a method of assembling a wiring board on a lead frame.

FIG. 4 is a schematic plan view of a lead frame according to a second embodiment.

FIG. 5 is a schematic plan view of a lead frame according to a third embodiment.

FIG. 6 is a schematic plan view showing an assembled state of a lead frame and a wiring board of a multi-chip package according to a conventional example.

FIG. 7 is an exploded plan view of a laminated wiring board according to a conventional example.

[Explanation of symbols]

10: Lead frame, 11: Inner lead, 11A
11G, 11P to 11R, 11S to 11U: inner lead extension portion, 12: tie bar, 13: external terminal, 2
0: wiring board, 31, 32: semiconductor chip.

Claims (1)

(57) [Claims] A substrate mounting portion for mounting a wiring substrate on which a plurality of semiconductor chips are mounted; and an inner end portion surrounding the substrate mounting portion and substantially in the same plane as the substrate mounting portion. In a resin-sealed multi-chip package including a lead frame having a plurality of inner leads whose opposed outer ends are connected to external terminals, at least a part of the inner leads is extended to the substrate mounting portion. The wiring board is mounted and fixed on the upper surface thereof, and each inner end of the inner lead extended and an electrode pattern on the wiring board or a predetermined electrode pad of the semiconductor chip mounted on the wiring board A resin-sealed multi-chip package characterized by being directly connected to any one of the above by wire bonding.