JP2936265B2 - Thin film etching method - Google Patents
Thin film etching methodInfo
- Publication number
- JP2936265B2 JP2936265B2 JP63138734A JP13873488A JP2936265B2 JP 2936265 B2 JP2936265 B2 JP 2936265B2 JP 63138734 A JP63138734 A JP 63138734A JP 13873488 A JP13873488 A JP 13873488A JP 2936265 B2 JP2936265 B2 JP 2936265B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- etching
- resist
- etching method
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 43
- 238000005530 etching Methods 0.000 title claims description 25
- 238000000034 method Methods 0.000 title description 12
- 239000000758 substrate Substances 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 description 7
- 239000010410 layer Substances 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- VLTRZXGMWDSKGL-UHFFFAOYSA-N perchloric acid Chemical compound OCl(=O)(=O)=O VLTRZXGMWDSKGL-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 2
- XMPZTFVPEKAKFH-UHFFFAOYSA-P ceric ammonium nitrate Chemical compound [NH4+].[NH4+].[Ce+4].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O XMPZTFVPEKAKFH-UHFFFAOYSA-P 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- OKJMLYFJRFYBPS-UHFFFAOYSA-J tetraazanium;cerium(4+);tetrasulfate Chemical compound [NH4+].[NH4+].[NH4+].[NH4+].[Ce+4].[O-]S([O-])(=O)=O.[O-]S([O-])(=O)=O.[O-]S([O-])(=O)=O.[O-]S([O-])(=O)=O OKJMLYFJRFYBPS-UHFFFAOYSA-J 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- ing And Chemical Polishing (AREA)
- Drying Of Semiconductors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、金属薄膜等のテーパーエッチング方法に関
し、特に薄膜トランジスタ（TFT）、液晶表示装置等の
配線形成時のエッチング法に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a taper etching method for a metal thin film or the like, and more particularly to an etching method for forming a wiring of a thin film transistor (TFT), a liquid crystal display device, or the like.
本発明は、金属膜等の薄膜をレジストをマスクにして
エッチングした後、酸素プラズマによってレジストの端
部を除去し、再度薄膜をエッチングすることによって、
薄膜パターンの端部をなだらかにして、層間絶縁耐圧が
高く、断線しにくい薄膜トランジスタや液晶表示装置等
を提供するものである。The present invention, by etching a thin film such as a metal film using a resist as a mask, removing the end of the resist by oxygen plasma, and etching the thin film again,
An object of the present invention is to provide a thin film transistor, a liquid crystal display device, and the like in which an end portion of a thin film pattern is made gentle, an interlayer dielectric strength is high, and disconnection is difficult.
Cr薄膜は、融点、硬度、遮光性等が高いため、TFTや
液晶表示装置等の配線や電極の一部に使われている。そ
の際用いられるCrの選択エッチは従来、第２硫酸（硝
酸）セリウムアンモンと過塩素酸の水溶液等によるウェ
ットエッチが主に用いられてきた。しかし、この方法で
は、Cr端面の形状を制御することが困難で、基板表面に
対しほぼ垂直に近い形となる。このCr薄膜上に層間絶縁
膜をCVD等で堆積すると、端面でのステップカバー性が
良くなく、上層の配線と短絡もしくは耐圧不良を発生し
てしまう。さらに、Cr配線上を横切る配線が切れやすい
問題もある。この問題を防ぐには、Cr薄膜の端面をなだ
らかにすることであるが、上記のウェットエッチでは一
般に困難で、ドライエッチが用いられる。Cr側面をなだ
らかにするテーパエッチは、特にエッチングの異方性が
制御できるイオンエッチ（ミリング）が有利である。第
２図にはイオンエッチを用いたCr薄膜の選択エッチ例を
示した。第２図（ａ）は、基板１上にCr薄膜２を全面堆
積の後、フォトレジスト３を通常のマスク工程によって
選択的に残した断面である。しかる後、Ar+等のイオン
を基板表面に対し斜めに照射しつつ基板１を回転させる
ことによってCr薄膜２を選択エッチする（第２図
（ｂ））。その後、レジスト３を除去して選択エッチさ
れたCr薄膜２を残す（第２図（ｃ））。この例の様にイ
オンエッチを用いれば、テーパーエッチは可能ではある
が、装置が高価、エッチの終点検出が困難、基板にイオ
ン照射損傷が発生する等の問題があった。The Cr thin film has a high melting point, hardness, light-shielding property and the like, and is therefore used for a part of wirings and electrodes of TFTs and liquid crystal display devices. Conventionally, as a selective etching of Cr used at that time, a wet etching using an aqueous solution of cerium ammonium sulfate and perchloric acid has been mainly used. However, in this method, it is difficult to control the shape of the Cr end face, and the shape becomes almost perpendicular to the substrate surface. If an interlayer insulating film is deposited on this Cr thin film by CVD or the like, the step coverage on the end face is not good, and short-circuiting with the wiring in the upper layer or poor withstand voltage occurs. Further, there is another problem that the wiring crossing over the Cr wiring is easily cut. In order to prevent this problem, the end face of the Cr thin film is made smooth. However, it is generally difficult to perform the above wet etching, and a dry etch is used. As the taper etch for making the Cr side surface gentle, an ion etch (milling) in which the anisotropy of etching can be controlled is particularly advantageous. FIG. 2 shows an example of selective etching of a Cr thin film using ion etching. FIG. 2 (a) is a cross section in which a photoresist 3 is selectively left by a normal masking process after a Cr thin film 2 is entirely deposited on a substrate 1. FIG. Thereafter, the Cr thin film 2 is selectively etched by rotating the substrate 1 while irradiating the substrate surface obliquely with ions such as Ar + (FIG. 2 (b)). Then, the resist 3 is removed to leave the selectively etched Cr thin film 2 (FIG. 2 (c)). If an ion etch is used as in this example, a taper etch is possible, but there are problems such as an expensive apparatus, difficulty in detecting the end point of the etch, and ion irradiation damage to the substrate.
以上述べた様に、ウェットエッチでは、エッチングさ
れたCr薄膜の端部が、基板表面に対し垂直に形成される
為、前記Cr薄膜上に層間絶縁層及び導電層を堆積する
と、導電層の断線、前記Cr薄膜と導電層との短絡及び耐
圧不良が発生する課題があった。又、ドライエッチで
は、テーパーエッチが可能であり、前述の課題を防止す
ることが出来る反面、基板のイオン照射損傷、高コスト
等の課題があった。As described above, in the wet etching, the edge of the etched Cr thin film is formed perpendicular to the substrate surface. Therefore, when an interlayer insulating layer and a conductive layer are deposited on the Cr thin film, the conductive layer is disconnected. In addition, there is a problem that a short circuit between the Cr thin film and the conductive layer and a breakdown voltage failure occur. Further, in the dry etching, a taper etching is possible, and the above-mentioned problems can be prevented. However, there are problems such as ion irradiation damage to the substrate and high cost.
上記課題を解決するために本発明は、薄膜をレジスト
をマスクにしてエッチング後、レジスト端部が薄膜端部
の内側にくるよう酸素プラズマ等によってレジストの端
部を除去後、薄膜を再度エッチングするものである。In order to solve the above problems, the present invention provides a method for etching a thin film using a resist as a mask, removing the end of the resist by oxygen plasma or the like so that the resist end comes inside the thin film end, and etching the thin film again. Things.
上記のように、本発明の薄膜のエッチング方法によれ
ば、薄膜をレジストをマスクにしてエッチング後、レジ
ストを例えば平行平板型陽極結合プラズマエッチ装置に
よる酸素プラズマでレジストの端部を除去し、再度薄膜
をエッチングすることによって、イオン照射損傷が少な
く、しかも低コストで、薄膜のパターン端部がなだらか
に形成できるものである。As described above, according to the thin film etching method of the present invention, after etching the thin film using the resist as a mask, the resist is removed with oxygen plasma using, for example, a parallel plate type anodic bonding plasma etch apparatus, and the resist is removed again. By etching the thin film, the pattern edge of the thin film can be formed smoothly with less ion irradiation damage and at low cost.
従って、本発明の薄膜のエッチング方法によって、TF
T等の多層構造の素子形成に於いて、薄膜パターン端部
の形状がなだらかである為、端部でのステップカバー性
が向上され、上・下層の配線の短絡もしくは耐圧不良の
発生を防止し、かつ上層の配線の断線の発生を防止する
ことができ、TFTや半導体製造等の信頼性の向上及び製
造歩留りの向上が達成されるものである。Therefore, according to the thin film etching method of the present invention, TF
In the formation of devices with a multilayer structure such as T, the shape of the edge of the thin film pattern is gentle, so step coverage at the edge is improved, and short-circuiting of upper and lower wiring or breakdown voltage failure is prevented. In addition, it is possible to prevent disconnection of the wiring in the upper layer, and to achieve an improvement in reliability of TFT and semiconductor manufacturing and an improvement in manufacturing yield.
以下に図面を用いて本発明を詳述する。 Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図には本発明によるCr薄膜のエッチング工程説明
図を示す。第１図（ａ）は、基板１上にCr薄膜２をスパ
ッタ等によって積層し、レジスト３を選択的に残した状
態を示す。基板１は、ガラス、石英、Si等でデバイス等
製造工程途中まで進んでいるものも使われる。Cr薄膜２
は、スパッターによって例えば2000オングストローム堆
積され、レジスト３は、例えばポジ型で1.3μｍの厚み
に形成される。第１図（ｂ）は、従来のエッチング方法
であるウェットエッチングでCr薄膜２を選択エッチした
状態を示す。硝酸第２セリウムアンモンと過塩素酸水溶
液との混合液を用いると約４分でエッチできる。第１図
（ｃ）は、酸素プラズマ処理にて、レジスト３が、Cr薄
膜２の端部の内側までくるようにした状態を示す。酸素
プラズマ処理は、例えば酸素圧力0.3Torr、電力0.4W/cm
2で２分間行なったものである。第１図（ｄ）は、ウェ
ットエッチングにて、１回目のエッチングの約５分の１
の時間エッチヤントに浸漬して再度Crエッチした状態を
示す。第１図（ｅ）は、レジストを除去した状態を示
す。図のようにCr薄膜２は、従来に比べてなだらかな断
面形状が得られる。FIG. 1 is a view for explaining the etching process of a Cr thin film according to the present invention. FIG. 1A shows a state where a Cr thin film 2 is laminated on a substrate 1 by sputtering or the like, and a resist 3 is selectively left. As the substrate 1, a device such as glass, quartz, Si, etc., which has progressed partway through the manufacturing process, such as a device, is used. Cr thin film 2
Is deposited, for example, by 2000 angstroms by sputtering, and the resist 3 is formed, for example, in a positive type with a thickness of 1.3 μm. FIG. 1B shows a state where the Cr thin film 2 is selectively etched by wet etching which is a conventional etching method. If a mixed solution of ceric ammonium nitrate and an aqueous solution of perchloric acid is used, it can be etched in about 4 minutes. FIG. 1 (c) shows a state in which the resist 3 reaches the inside of the end of the Cr thin film 2 by the oxygen plasma treatment. The oxygen plasma treatment is performed, for example, at an oxygen pressure of 0.3 Torr and a power of 0.4 W / cm.
2 for 2 minutes. FIG. 1 (d) shows about one fifth of the first etching by wet etching.
A state of immersion in the etchant for a period of time and Cr etching again is shown. FIG. 1 (e) shows a state in which the resist has been removed. As shown in the figure, the Cr thin film 2 has a gentler cross-sectional shape than the conventional one.
以上、Cr薄膜の実施例を述べてきたが、例えばAl、絶
縁膜等の薄膜にも本発明は有効である。Although the embodiment of the Cr thin film has been described above, the present invention is also effective for a thin film such as an Al or insulating film.
上述の説明から明らかなように、従来の薄膜のテーパ
ーエッチングとちがって、基板にイオン照射損傷を与え
ることなく薄膜の端部をなだらかに形成でき、低コスト
化につながる。また、薄膜の端部がなだらかな形状にな
るため、多層配線の層間絶縁耐圧、上層配線の断線等の
改善された信頼性の高いTFT装置、半導体装置、液晶表
示装置等が低コストで提供できる。As is apparent from the above description, unlike the conventional taper etching of a thin film, the edge of the thin film can be formed smoothly without causing ion irradiation damage to the substrate, which leads to cost reduction. In addition, since the end portion of the thin film has a gentle shape, it is possible to provide a TFT device, a semiconductor device, a liquid crystal display device, and the like with high reliability with improved interlayer dielectric breakdown voltage of multilayer wiring, disconnection of upper wiring, and the like. .
第１図は、本発明による薄膜のエッチング工程説明図、
第２図は、従来の方法による薄膜のエッチング工程説明
図である。 １……基板 ２……Cr薄膜 ３……レジストFIG. 1 is an explanatory diagram of a thin film etching process according to the present invention,
FIG. 2 is an explanatory view of a thin film etching process by a conventional method. 1 ... substrate 2 ... Cr thin film 3 ... resist
Claims (1)
クとしてエッチングする工程と、酸素プラズマによって
前記レジストのパターン端部を除去する工程と、その
後、前記薄膜のパターン端部をなだらかに形成するため
に前記薄膜を再度エッチングする工程と、を備えること
を特徴とする薄膜のエッチング方法。A step of etching the thin film coated on the substrate using the resist as a mask, a step of removing a pattern end of the resist by oxygen plasma, and thereafter, forming a pattern end of the thin film gently. And etching the thin film again for the purpose of etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138734A JP2936265B2 (en) | 1988-06-06 | 1988-06-06 | Thin film etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138734A JP2936265B2 (en) | 1988-06-06 | 1988-06-06 | Thin film etching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01306581A JPH01306581A (en) | 1989-12-11 |
| JP2936265B2 true JP2936265B2 (en) | 1999-08-23 |
Family
ID=15228922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63138734A Expired - Lifetime JP2936265B2 (en) | 1988-06-06 | 1988-06-06 | Thin film etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2936265B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5132745A (en) * | 1990-10-05 | 1992-07-21 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| CN107086274A (en) * | 2017-05-15 | 2017-08-22 | 京东方科技集团股份有限公司 | Organic light emitting diode and preparation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0626204B2 (en) * | 1985-01-22 | 1994-04-06 | セイコー電子工業株式会社 | Chromium thin film selective etching method |
-
1988
- 1988-06-06 JP JP63138734A patent/JP2936265B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01306581A (en) | 1989-12-11 |
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