JPH01306581A - Method for etching thin film - Google Patents

Method for etching thin film

Info

Publication number
JPH01306581A
JPH01306581A JP13873488A JP13873488A JPH01306581A JP H01306581 A JPH01306581 A JP H01306581A JP 13873488 A JP13873488 A JP 13873488A JP 13873488 A JP13873488 A JP 13873488A JP H01306581 A JPH01306581 A JP H01306581A
Authority
JP
Japan
Prior art keywords
thin film
etching
resist
film
pattern edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13873488A
Other languages
Japanese (ja)
Other versions
JP2936265B2 (en
Inventor
Shunichi Motte
物袋 俊一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP63138734A priority Critical patent/JP2936265B2/en
Publication of JPH01306581A publication Critical patent/JPH01306581A/en
Application granted granted Critical
Publication of JP2936265B2 publication Critical patent/JP2936265B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Abstract

PURPOSE:To suppress damage due to irradiation with ions and to gently slope the pattern edge of a thin film by etching the thin film through a resist as a mask, removing the pattern edge of the resist with oxygen plasma and etching the thin film again. CONSTITUTION:A thin Cr film 2 is laminated on a substrate 1 and a resist 3 is selectively left on the film 2. This film 2 is selectively etched and the pattern edge of the resist 3 is removed with oxygen plasma so that the resist 3 is made to stand back from the pattern edge of the film 2. The film 2 is then etched again to gently slope the pattern edge of the film 2. By this method, the reliability of a TFT device, a semiconductor device, etc., can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野1 本発明は、金属薄膜等のテーパーエツチング方法に関し
、特に薄膜トランジスタ(TPT)、液晶表示装置等の
配線形成時のエツチング法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a taper etching method for metal thin films, etc., and particularly to an etching method for forming wiring for thin film transistors (TPT), liquid crystal display devices, etc.

【発明の概要] 本発明は、金属膜等の薄膜をレジストをマスクにしてエ
ツチングした後、酸素プラズマによってレジストの端部
を除去し、再度薄膜をエツチングすることによって、薄
膜パターンの端部をなだらかにして、層間絶縁耐圧が高
く、断線しにくい薄膜トランジスタや液晶表示装置等を
提供するものである。
[Summary of the Invention] The present invention involves etching a thin film such as a metal film using a resist as a mask, removing the edges of the resist using oxygen plasma, and etching the thin film again to gently smooth the edges of the thin film pattern. Accordingly, the present invention provides thin film transistors, liquid crystal display devices, etc., which have a high interlayer dielectric strength voltage and are resistant to disconnection.

【従来の技術] Cr薄膜は、融点、硬度、遮光性等が高いため、TPT
や液晶表示装置等の配線や電極の一部に使われている。
[Prior art] Cr thin film has high melting point, hardness, light shielding properties, etc.
It is used as part of the wiring and electrodes of LCDs and liquid crystal display devices.

その際用いられるCrの選択エッチは従来、第2硫酸(
硝酸)セリウムアンモンと過塩素酸の水溶液等によるウ
ェットエッチが主に用いられてきた。しかし、この方法
では、Cr端面の形状を制御することが困難で、基板表
面に対しほぼ垂直に近い形となる。このCr薄膜上に層
間絶縁膜をCVD等で堆積すると、端面でのステップカ
バー性が良くな(、上層の配線と短絡もしくは耐圧不良
を発生してしまう、さらに、Cr配線上を横切る配線が
切れやすい問題もある。この問題を防ぐには、Cr薄膜
の端面をなだらかにすることであるが、上記のウェット
エッチでは一般に困難で、ドライエッチが用いられる。
The selective etching of Cr used in this process has conventionally been performed using dibasic sulfuric acid (
Wet etching using an aqueous solution of cerium ammonium (nitric acid) and perchloric acid has been mainly used. However, with this method, it is difficult to control the shape of the Cr end face, which is almost perpendicular to the substrate surface. If an interlayer insulating film is deposited on this Cr thin film by CVD or the like, the step coverage at the end face will be poor (this may cause a short circuit with the upper layer wiring or a breakdown voltage failure), and the wiring that crosses the Cr wiring will break. To prevent this problem, it is necessary to smooth the end face of the Cr thin film, but this is generally difficult with the above wet etching, so dry etching is used.

Cr側面をなだらかにするテーバエッチは、特にエツチ
ングの異方性が制御できるイオンエッチ(ミリング)が
有利である。第2図にはイオンエッチを用いたCr薄膜
の選択エッチ例を示した。
Ion etching (milling) is particularly advantageous in that it allows the anisotropy of etching to be controlled. FIG. 2 shows an example of selective etching of a Cr thin film using ion etching.

第2図(a)は、基板l上にCr薄膜2を全面堆積の後
、フォトレジスト3を通常のマスク工程によって選択的
に残した断面である。しかる後、Ar”等のイオンを基
板表面に対し斜めに照射しつつ基板lを回転させること
によってCr薄膜2を選択エッチする(第2図(b))
、その後、レジスト3を除去して選択エッチされたCr
薄膜2を残す(第2図(C))。この例の様にイオンエ
ッチを用いれば、テーパーエッチは可能ではあるが、装
置が高価、エッチの終点検出が困難、基板にイオン照射
損傷が発生する等の問題があった。
FIG. 2(a) is a cross-sectional view in which a Cr thin film 2 is deposited on the entire surface of the substrate 1, and then a photoresist 3 is selectively left by a normal mask process. Thereafter, the Cr thin film 2 is selectively etched by rotating the substrate 1 while obliquely irradiating the substrate surface with ions such as Ar'' (FIG. 2(b)).
, then the resist 3 was removed and selectively etched Cr
A thin film 2 is left (FIG. 2(C)). If ion etching is used as in this example, taper etching is possible, but there are problems such as expensive equipment, difficulty in detecting the end point of etching, and ion irradiation damage to the substrate.

[発明が解決しようとする課題) 以上述べた様に、ウェットエッチでは、エツチングされ
たCr薄膜の端部が、基板表面に対し垂直に形成される
為、前記Cr薄謹上に層間絶縁層及び導電層を堆積する
と、導電層の断線、前記Cr薄膜と導電層との短絡及び
耐圧不良が発生する課題があった。又、ドライエッチで
は、テーパーエッチが可能であり、前述の課題を防止す
ることが出来る反面、基板のイオン照射損傷、高コスト
等の課題があった。
[Problems to be Solved by the Invention] As described above, in wet etching, the edge of the etched Cr thin film is formed perpendicular to the substrate surface, so an interlayer insulating layer and a conductive layer are formed on the Cr thin film. When the layers are deposited, there are problems such as disconnection of the conductive layer, short circuit between the Cr thin film and the conductive layer, and breakdown voltage failure. Further, although dry etching allows taper etching and can prevent the above-mentioned problems, it also has problems such as ion irradiation damage to the substrate and high cost.

[課題を解決するための手段] 上記課題を解決するために本発明は、薄膜をレジストを
マスクにしてエツチング後、レジスト端部が薄膜端部の
内側にくるよう酸素プラズマ等によってレジストの端部
な除去後、薄膜を再度エツチングするものである。
[Means for Solving the Problems] In order to solve the above problems, the present invention etches a thin film using a resist as a mask, and then etches the ends of the resist using oxygen plasma or the like so that the ends of the resist are inside the ends of the thin film. After the removal, the thin film is etched again.

[作用] 上記のように、本発明の薄膜のエツチング方法によれば
、薄膜をレジストをマスクにしてエツチング後、レジス
トを例えば平行平板型陽極結合プラズマエッチ装置によ
る酸素プラズマでレジストの端部を除去し、再度薄膜を
エツチングすることによって、イオン照射損傷が少なく
、しかも低コストで、薄膜のパターン端部がなだらかに
形成できるものである。
[Operation] As described above, according to the thin film etching method of the present invention, after etching the thin film using a resist as a mask, the edges of the resist are removed using oxygen plasma using, for example, a parallel plate type anodic coupled plasma etching apparatus. However, by etching the thin film again, it is possible to form gentle pattern edges of the thin film with little ion irradiation damage and at low cost.

従って1本発明の薄膜のエツチング方法によって、TP
T等の多層構造の素子形成に於いて、薄膜パターン端部
の形状がなだらかである為、端部でのステップカバー性
が向上され、上・下層の配線の短絡もしくは耐圧不良の
発生を防止し、かつ上層の配線の断線の発生を防止する
ことができ、TPTや半導体製造等の信頼性の向上及び
製造歩留りの向上が達成されるものである。
Therefore, by the thin film etching method of the present invention, TP
When forming elements with a multilayer structure such as T, the shape of the edge of the thin film pattern is gentle, so step coverage at the edge is improved, preventing short circuits or breakdown voltage failures in upper and lower layer wiring. Moreover, it is possible to prevent the occurrence of disconnection of the upper layer wiring, thereby achieving improvement in reliability of TPT and semiconductor manufacturing, and improvement in manufacturing yield.

(実施例1 以下に図面を用いて本発明を詳述する。(Example 1 The present invention will be explained in detail below using the drawings.

第1図には本発明によるCr薄膜のエツチング工程説明
図を示す。第1図(a)は、基板l上にCr薄膜2をス
パッタ等によって積層し、レジスト3を選択的に残した
状態を示す、基板1は、ガラス、石英、Si等でデバイ
ス等製造工程途中まで進んでいるものも使われる。Cr
薄膜2は、スパッターによって例えば2000オングス
トローム堆積され、レジスト3は、例えばポジ型で1゜
3μmの厚みに形成される。第1図(b)は、従来のエ
ツチング方法であるウェットエツチングでCr薄膜2を
選択エッチした状態を示す、硝酸第2セリウムアンモン
と過塩素酸水溶液との混合液を用いると約45+でエッ
チできる。第1図(C)は、酸素プラズマ処理にて、レ
ジスト3が、Cr薄膜2の端部の内側までくるようにし
た状態を示す、酸素プラズマ処理は、例えば酸素圧力0
.3Torr、電力0 、4 W/cm”で2分間行な
ったものである。第1図(d)は、ウェットエツチング
にて、1回目のエツチングの約5分のlの時間エッチャ
ントに浸漬して再度Crエッチした状態を示す。第1図
(e)は、レジストを除去した状態を示す。図のように
Cr薄膜2は、従来に比べてなだらかな断面形状が得ら
れる。
FIG. 1 shows an explanatory diagram of the etching process of a Cr thin film according to the present invention. FIG. 1(a) shows a state in which a Cr thin film 2 is laminated by sputtering or the like on a substrate 1, with a resist 3 selectively left behind. Those that have advanced up to that point are also used. Cr
The thin film 2 is deposited to a thickness of, for example, 2000 angstroms by sputtering, and the resist 3 is formed, for example, of a positive type to a thickness of 1.3 μm. FIG. 1(b) shows the Cr thin film 2 selectively etched by wet etching, which is a conventional etching method. Etching can be performed at approximately 45+ using a mixed solution of ceric ammonium nitrate and perchloric acid aqueous solution. . FIG. 1(C) shows a state in which the resist 3 is brought to the inside of the edge of the Cr thin film 2 by oxygen plasma treatment.
.. It was etched for 2 minutes at 3 Torr, power 0, and 4 W/cm''. Figure 1(d) shows wet etching, which was immersed in the etchant for about 5 minutes of the first etching time and then etched again. The state after Cr etching is shown. FIG. 1(e) shows the state after the resist has been removed. As shown in the figure, the Cr thin film 2 has a gentler cross-sectional shape than the conventional one.

以上、Cr薄膜の実施例を述べてきたが、例えばA1.
絶縁膜等の薄膜にも本発明は有効である。
Examples of Cr thin films have been described above, but for example, A1.
The present invention is also effective for thin films such as insulating films.

[発明の効果] 上述の説明から明らかなように、従来の薄膜のテーパー
エツチングとちがって、基板にイオン照射損傷を与える
ことなく薄膜の端部をなだらかに形成でき、低コスト化
につながる。また、薄膜の端部がなだらかな形状になる
ため、多層配線の層間絶縁耐圧、上層配線の断線等の改
善された信頼性の高いTPT装置、半導体装置、液晶表
示装置等が低コストで提供できる。
[Effects of the Invention] As is clear from the above description, unlike conventional taper etching of thin films, the edges of the thin film can be formed smoothly without damaging the substrate by ion irradiation, leading to cost reduction. In addition, since the edges of the thin film have a gentle shape, it is possible to provide highly reliable TPT devices, semiconductor devices, liquid crystal display devices, etc. with improved interlayer dielectric breakdown voltage of multilayer wiring and disconnection of upper layer wiring at low cost. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明による薄膜のエツチング工程説明図、
第2図は、従来の方法による薄膜のエツチング工程説明
図である。 1・・・基板 2・・・Cr薄膜 3・・・レジスト 以上 出願人 セイコー電子工業株式会社 代理人 弁理士  林   敬 之 助第1図
FIG. 1 is an explanatory diagram of the thin film etching process according to the present invention;
FIG. 2 is an explanatory diagram of a thin film etching process according to a conventional method. 1...Substrate 2...Cr thin film 3...Resist and above Applicant Seiko Electronics Industries Co., Ltd. Agent Patent attorney Keisuke Hayashi Figure 1

Claims (1)

【特許請求の範囲】[Claims] 基板上に被覆された薄膜をレジストをマスクとしてエッ
チングした後、酸素プラズマによって前記レジストのパ
ターン端部を除去し、前記薄膜を再度エッチングし、形
成される前記薄膜のパターンの端部をなだらかにするこ
とを特徴とする薄膜のエッチング方法。
After etching the thin film coated on the substrate using the resist as a mask, the edges of the resist pattern are removed by oxygen plasma, the thin film is etched again, and the edges of the formed thin film pattern are smoothed. A thin film etching method characterized by:
JP63138734A 1988-06-06 1988-06-06 Thin film etching method Expired - Lifetime JP2936265B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63138734A JP2936265B2 (en) 1988-06-06 1988-06-06 Thin film etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63138734A JP2936265B2 (en) 1988-06-06 1988-06-06 Thin film etching method

Publications (2)

Publication Number Publication Date
JPH01306581A true JPH01306581A (en) 1989-12-11
JP2936265B2 JP2936265B2 (en) 1999-08-23

Family

ID=15228922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63138734A Expired - Lifetime JP2936265B2 (en) 1988-06-06 1988-06-06 Thin film etching method

Country Status (1)

Country Link
JP (1) JP2936265B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992006504A1 (en) * 1990-10-05 1992-04-16 General Electric Company Thin film transistor having an improved gate structure and gate coverage by the gate dielectric
WO2018210040A1 (en) * 2017-05-15 2018-11-22 京东方科技集团股份有限公司 Organic light emitting diode and preparation method therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61168924A (en) * 1985-01-22 1986-07-30 Seiko Instr & Electronics Ltd Selective etching method of thin chromium film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61168924A (en) * 1985-01-22 1986-07-30 Seiko Instr & Electronics Ltd Selective etching method of thin chromium film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992006504A1 (en) * 1990-10-05 1992-04-16 General Electric Company Thin film transistor having an improved gate structure and gate coverage by the gate dielectric
WO2018210040A1 (en) * 2017-05-15 2018-11-22 京东方科技集团股份有限公司 Organic light emitting diode and preparation method therefor
US11171301B2 (en) 2017-05-15 2021-11-09 Boe Technology Group Co., Ltd. Organic light emitting diode and method for fabricating the same

Also Published As

Publication number Publication date
JP2936265B2 (en) 1999-08-23

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