JP2933822B2 - Elevator control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elevator controller using a computer, and more particularly to an elevator controller using a single-chip microcomputer.

[0002]

2. Description of the Related Art For example, as a device for digitally controlling a system to be controlled, such as an elevator, using a microcomputer, there is the following conventional technology. The first prior art is mainly used when the system to be controlled is large-scale or when particularly high-speed processing is required. For example, the "Hitachi 32-bit microprocessor H32 / 10"
0] As disclosed in page 8 of the user's manual, FIG. 1.5, a multi-chip microcomputer (indicated as a main processor in the figure) is mainly used as a microcomputer capable of executing control processing at high speed. External operating system, external read-only memory for storing application programs (main memory in the figure), and other interface chips via the main processor's wide bus. The configuration is as follows.

In the case of this type of system, since the clock that defines the operation speed of the microcomputer has reached several tens of MHz, the system must be constructed in such a manner that the processing speed is increased by relying on the high-speed operation capability of the microcomputer itself. Used as a control device having a high-speed processing capability.

The second prior art is mainly used when the system is small-scale or when it is desired to minimize the cost increase. For example, the "Hitachi single chip microcomputer H8 / 350" As shown in FIG. 1.1 on page 5 of the user's manual, a central processing unit (shown as CPU in the figure), a read-only memory (shown as mask ROM in the figure), and A single-chip microcomputer in which a readable / writable memory (in the figure, referred to as a RAM) is formed on the same IC chip at any time is used. Note that an IC is an integrated circuit.

In such a system, the programs used for the operation are all burned into a mask ROM in the microcomputer, and a simple and inexpensive control device consisting of only a single-chip microcomputer is generally constructed.

A third prior art is disclosed in Japanese Unexamined Patent Publication No.
Japanese Patent Application Laid-Open No. 47147/1993 discloses three types of operation modes: a mode in which processing is performed by an internal memory; a mode in which processing is performed by an external memory; and a mode in which processing is performed by both memories. It proposes a technology to flexibly respond to software changes and reduce costs.

[0007]

In the first prior art,
As described above, since the program necessary for the operation is stored in the external read-only memory due to the configuration of the control device, this memory is expensive and can perform high-speed reading corresponding to the processing capability of the microcomputer. Otherwise, the capability of the control device will not be fully exhibited. That is, when a memory having a low read speed is used, the microcomputer waits for a time until predetermined data comes out of the memory, and thus the processing speed is equivalently reduced.

Therefore, in a system using a multi-chip microcomputer, a cost problem that an expensive high-speed operation type IC is required for a memory and an interface, and a reduction in noise resistance due to handling of high-speed signals. For this reason, there is a problem that this method cannot be applied to a field where cost competition is severe, such as an elevator, or an application where the installation environment is severe.

On the other hand, in the second prior art, as described above, a program is generally burned into a mask ROM in a microcomputer, and an external memory other than the microcomputer is not provided. It is. For this reason, for example, when trying to apply this second conventional technology to elevator control, etc., in the elevator, the specifications such as the rated traveling speed, the rated loading load, the number of floors stopped, etc. are diverse. Since the number of combinations of these specifications is enormous, a mask ROM is required for each combination.
It is necessary to prepare various types of dedicated single-chip microcomputers.

[0010] However, a large cost typified by a mask charge of a mask ROM in a processing procedure is expected to be dedicated to a single-chip microcomputer, but demand corresponding to the cost cannot generally be expected. For applications such as elevators, the second prior art is not an ideal system configuration.

In the case of this type of microcomputer, the clock that defines the operating speed of the microcomputer is about 10 MHz, which is considerably slower than that of a multichip microcomputer, and it is impossible to expect high-speed processing. Therefore, there is also a problem that the applicable range is limited.

Further, in the third prior art, operation switching in three modes, ie, a built-in memory, an external memory, and a combination of the two, is disclosed. There is no mention of the task level of a program to be stored in the memory, and the specific configuration for application to a single-chip microcomputer is not always clear.

An object of the present invention is to solve the above-mentioned problems of the prior art and to apply the method to an application field of a small quantity and a wide variety of products to control an elevator using a microcomputer capable of realizing a high-speed processing and an inexpensive system configuration. It is to provide a device.

[0014]

The object of the present invention is to provide a single-chip microcomputer in which a central processing unit and a memory are built on the same IC chip, and a read-only memory connected to the microcomputer outside the chip. The central processing unit performs processing according to processing procedures separately stored in a memory in the same IC chip and an external memory,
This is achieved by controlling the elevator to be controlled.

[0015]

The central processing unit executes the processing in accordance with the processing procedure divided and stored in the memory built in the single-chip microcomputer and the external memory. It is possible to selectively use an internal memory having a high reading speed and an external memory having a not so high reading speed, so that the total processing time can be reduced with an inexpensive system configuration.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an elevator control apparatus according to the present invention will be described in detail with reference to the illustrated embodiments. FIG.
In one embodiment of the present invention, an AC power supplied from a three-phase AC power supply 1 serving as a drive power source for an elevator system is normally supplied to a rectifier (forward conversion unit) 2 composed of a diode bridge.
Is converted to DC power, the output of which is smoothed by a capacitor 3 and supplied to an inverter (inverting unit) 4. Then, the electric power converted into a three-phase AC power supply having a variable voltage and a variable frequency by the inverter 4 is supplied to the induction motor 6 via the current detector 5. At this time, the electric current is supplied to the induction motor 6 by the current detector 5. The flowing current is detected.

A sheave 7 is provided on the rotating shaft of the induction motor 6.
Is mounted, whereby the car 8 and the counterweight 9 travel up and down according to the rotation of the induction motor 6,
The service between the floors by the car 8 can be obtained. A pulse generator 10 is attached to the rotating shaft of the induction motor 6, whereby pulse signals of a number corresponding to the number of rotations of the induction motor 6 are taken out, and the position of the car 8 is controlled. ing.

Reference numeral 11 denotes an elevator control device, which is a single-chip microcomputer 12
And a read-only memory (ROM) 13. The read-only memory 13 is connected to the microcomputer 12 via a relatively narrow external bus 14 of about 8 bits or 16 bits, for example, to form an external read-only memory.

The elevator control device 11
Takes the current signal a detected by the current detector 5 and the pulse signal p detected by the pulse generator 10 and creates a control signal s for the inverter as a result of a predetermined arithmetic processing. By supplying the ON / OFF signal to the switch element, the inverter 4 is PWM-controlled, whereby the rotation control of the induction motor 3, that is, the traveling control of the car 8 can be obtained.

As will be described later, the read only memory 13 included in the elevator control device 11 is completely stored when the elevator system is started (for example, when power is turned on). Real-time processing for normal elevator control, since information transfer is performed only during startup processing before entering the operating state (a state in which the elevator can be serviced in response to a user call) Unlike the EPRO, the access time is considerably slower than the memory built in the microcomputer 12.
An M or an EEPROM is sufficient in time, and as a result, an inexpensive system can be constructed.

The read-only memory 13 stores, as a representative example, a table of specification data corresponding to the model and specifications of each elevator. That is, as shown in FIG. 2, for example, the rated speed of the elevator is at address 1, the load capacity of the elevator is at address 2, the number of floors at which the elevator is stopped at address 3, and the abnormality is at address 4. Various unique data that is different for each elevator to be delivered, such as speed data serving as a reference for checking the speed increase, and the presence or absence of a special specification for wheelchair calls at address n, is stored. In addition, programs that are strongly restricted by these specifications are also stored here.

Next, in the single-chip microcomputer 12, in addition to a central processing unit (CPU) 15 for executing a processing procedure necessary for operating the elevator, a clock generator 16 for defining the operation timing of the central processing unit 15 And a read-only memory 17 storing a program necessary for executing common processing irrespective of the model among processing procedures to be executed by the central processing unit 15, and particularly a program requiring high-speed processing. A read / write memory as a storage destination when reading and storing the specification data and the like stored in the external read-only memory 13 when the central processing unit 15 is started, etc.
(RAM) 18, an analog-to-digital converter 19 for converting an analog value such as a current value into a digital value, and counting the number of pulses of a pulse signal p output from the pulse generator 10 to determine the number of pulses required to generate a speed command. Calculate car position,
A counter 20 that counts pulse intervals and widths to calculate the rotation speed of the motor necessary for speed feedback control, and outputs a pulse width-modulated on / off signal to an inverter, and performs a count necessary for PWM control processing. In order to process high-precision wide data with a small number of accesses at high speed, for example,
The single-chip microcomputer 12 is connected by a wide internal bus 21 such as two bits.
Is configured.

Next, the processing procedure written in a read-only memory (hereinafter referred to as a first ROM) 17 in the single-chip microcomputer 12 and an external read-only memory (hereinafter referred to as a second ROM) 13 and a readable / writable memory (hereinafter referred to as RA) as needed.
The relationship between this and M will be specifically described with reference to FIGS. 3, 4, and 5. FIG.

First, when the operating power supply of the elevator controller 11 is turned on, the single-chip microcomputer 12 rises from a reset state, and when the power supply is established, a program counter is set to an address to be referred first, and the address is set on that address or at that address. The initialization program P10 stored at the indicated address starts operation.

The initial setting program P10 is
The elevator system operates only when the microcomputer is started, and the entire elevator system has not yet begun to operate. Therefore, high-speed operation is not required.
There is no problem if the data is stored in either the upper part or the second ROM 13.

As shown in FIG. 3, the initialization program P10 first initializes the hardware of the microcomputer itself in a process P101, for example, sets a zero value to the entire area of the built-in RAM 18 and turns on the power. RAM1 accompanying
8 to remove the uncertainty of the contents
The initial setting of the interface such as whether each pin of 0 is used as an input side or an output side is performed.

Next, in process P102, the specification data stored in the second ROM 13 and the application program strongly associated with the specification data are stored in the R.
A process for transferring to the AM 18 is performed. In this transfer processing, the central processing unit 15 may transfer data one by one, or the processing may be performed by DMA (direct memory access) transfer without the central processing unit 15 interposed. In any case, since the elevator system has not yet performed the processing such as the normal speed control at this time, there is no problem even if the transfer processing by the second ROM access takes some time.

When the transfer processing is completed, the main processing of the initialization program P10 is completed, and the processing P103
Then, the program counter returns to the interrupt waiting portion in the operation system not described here.

FIG. 4 shows spec data as an example of the result transferred to the RAM 18. In this case,
An example is shown in which a series of specification data starting from the address 1 of the externally attached second ROM 13 and the application program following it are transferred to the transfer destination RAM 18 starting from the address 1001H.

Normally, after the initial setting program P10 completes its operation and enters an interrupt waiting state, after this state, various real-time control application programs stored in the first ROM 17, for example, generation of an elevator speed command. A program, a car position detection program, a stop floor determination program, a speed control program, a PWM signal generation program for controlling a switch element in an inverter, an abnormal speed detection program, etc. are started at predetermined time intervals, that is, in response to a timer interrupt. It has become.

FIG. 5 shows a processing procedure of the abnormal speed detection program P20 as an example of these programs, and an effect caused by a difference in a memory accessed in the program will be described.

Now, for example, the abnormal speed detection program P20 is registered in a 10 millisecond task in an operation system program (not shown), and the abnormal speed detection program P20 is generated by a timer interrupt generated every 10 milliseconds. If it is started, first, a process P20
At 1, the counter 20 is referred to. Specifically, the actual traveling speed V of the elevator is calculated by counting the width of the pulse generated from the pulse generator 10.

Next, in process P202, the rated speed Vmax of this elevator is searched. The address accessed at this time is not address 1 of the second ROM 13, but RA address.
It is address 1001H of M18.

Further, in process P203, the actual traveling speed V
It is checked whether the speed is not an abnormal speed exceeding (rated speed Vmax + predetermined value ΔV). Again, the rated speed Vma
The access destination of x and the predetermined value ΔV is not the second ROM 13 but the RAM 18 in the single-chip microcomputer 12.
It is.

If the check result is YES, a warning is issued and an emergency stop process is performed in process P204.
At 205, the process returns to the interrupt wait destination. If NO, no processing is performed and the process returns to the interrupt wait destination.

Here, in the abnormal speed detection program P20, the data such as the rated speed Vmax and the check data ΔV must use a value corresponding to the specification of the elevator system depending on the type of the elevator.

Here, as described above, these values are set as fixed constants in the program, and data is prepared in the first ROM 17 in the microcomputer according to the model of each elevator (the first ROM 17 in the microcomputer). Using a mask ROM according to each elevator model) requires a dedicated single-chip microcomputer for each elevator model, and the cost (one type) required to create this mask pattern Hit, for example, about 50
Considering the cost of 10,000 yen, it is difficult to adopt such a method in terms of investment in small-lot, multi-product applications such as elevators.

In this embodiment, however, one kind of mask ROM is prepared as the first ROM 17 so that the constant accesses a fixed address, for example, the address 1001H or 1004H, while the constant 1 is used. Address or address 4 (external EPROM or EEPROM
The corresponding data for each model of the elevator is written in the second ROM 13 such as M, etc.).
A constant is transferred and established at addresses 1H and 1004H, and this address is accessed by the program P20. As a result, according to this embodiment, only one type of mask ROM is available regardless of the model. The cost burden associated with mask ROM creation can be greatly reduced.

Further, in this embodiment, the time required for referring to the memory is shortened, and as a result, an effect is obtained that the processing such as calculation can be indirectly executed at high speed. The points here are the access time of the memory storing the data to be accessed and the bus width of the data to be read.

In this embodiment, processes P202 and P203
Then, the specification data which can be changed according to the type of the elevator, such as the rated speed Vmax and the predetermined value ΔV, is stored in the second external ROM 13 and the internal RAM is read therefrom.
The data is transferred to the RAM 18 at a high frequency.

Here, E which is the external second ROM 13
PROMs and EEPROMs require an access time of about 200 to 300 nanoseconds unless a particularly high-speed and expensive device is used.
Has an access time of less than 50 nanoseconds,
Even if the central processing unit 15 performs a high-speed processing operation of, for example, a clock of about 20 MHz, the access time of the RAM 18 is short, so that the central processing unit does not have to wait by memory access (that is, a non-wait operation is possible). High-speed processing becomes possible.

Further, in the single-chip microcomputer, it is necessary to secure as many ports for the interface (number of external pins as possible), but on the other hand, it is necessary to reduce the total number of pins as much as possible due to the package size and cost. In many cases, the number of pins for the interface is not reduced, but the number of pins for the external bus is reduced. As a result, the bus width tends to be narrowed (reducing the number of bits).

Therefore, in order to access high-precision data (data having a large number of bits) from an external memory via an external bus, one data is transferred between the central processing unit in the microcomputer and the external memory. Must be divided and read in several times. As a result, a larger number of times of reading (time) is required than when reading the RAM inside the microcomputer at a time with a 32-bit bus width as in the above embodiment. .

Due to the difference between the access time and the bus width, it can be said that a processing speed difference of 5 to 10 times occurs between the case where the central processing unit directly accesses the external ROM and the case where the central processing unit accesses the internal RAM after data transfer. .

In the above embodiment, a very simple example was taken as a program to explain the difference between these operations. Therefore, as described above, the actual time difference required for processing is several microseconds compared to the prior art. Although there is only a slight difference, since a program for operating an actual system has an enormous number of memory accesses, a difference in processing speed of 5 to 10 times causes a large real time difference.

As a result, for example, assuming that the control target is the above-described inverter-controlled elevator, in the conventional method, the task level is a single-chip microcomputer dedicated to operating a PWM control program having a task level of several hundred microseconds, Can be achieved if it is not a multiple configuration with a multi-chip microcomputer that executes programs such as a car position detection program, a stop floor determination program, a speed command generation program, a speed control program, an abnormal speed detection program of several milliseconds to 40 milliseconds According to the embodiment of the present invention, the performance that was not provided can be achieved by one inexpensive single-chip microcomputer.

In the embodiment shown in FIG. 1, the external bus 14 and the internal bus 21 are shown to be directly connected to each other. However, an interface circuit for bus width conversion is actually required between them. is there. However, since it is not directly related to the operation of the embodiment, it is omitted.

Further, this embodiment exhibits an excellent effect also in terms of the reliability of the control device. That is, in this embodiment, the central processing unit 15 includes the first ROM 17 and the RAM
The processing is executed in real time by accessing the ROM 18 and the ROM 17 and the RAM 1.
8 is located very close to the same chip as the central processing unit 15, so that the second RO which is externally mounted on a printed board outside the chip and remote from the central processing unit 15
As compared with the case where M13 is accessed with high frequency and high speed and real-time processing is performed, higher noise immunity can be obtained. Therefore, power converters such as inverters and converters that may generate much noise can be obtained. Even if it is installed nearby and compactly integrated in the control panel of the elevator, there is no possibility of malfunction, and as a result, high reliability can be easily maintained.

Of course, also in this embodiment, at the time of startup, there is a mode in which the contents of the external second ROM 13 are transferred and accessed. In this case, while the system is being started, the inverter is still in operation. Power converters such as power converters and converters have not begun energizing. Therefore, at this time, since there is almost no noise itself and access to an EPROM or EEPROM with a slow access time, there is a large margin for waveform distortion and noise. It is said that there is no possibility that the reliability may be degraded due to noise at all, since the state is essentially not easily affected by the noise.

Further, as a result, in this embodiment, the external ROM 13 and the single-chip microcomputer 1
In addition, there is also an effect that there is little restriction on the arrangement of ICs on a printed board.

As described above, in the above-described embodiment, the ROM incorporated in the single-chip microcomputer stores the common part that is not linked to the type of the system to be controlled, and the external ROM has strong specifications data and specifications. Store the linked application program, transfer the information in the external ROM to the RAM built into the single-chip microcomputer, and then control all the application programs using the ROM and RAM in the microcomputer. Since the device is constructed, only one kind of built-in mask ROM in the microcomputer is needed, and there is an effect that cost reduction effect and realization of high-speed processing by internal memory access can be simultaneously obtained for a small number of kinds of applications.

Next, another embodiment of the present invention will be described. First, in the embodiment shown in FIG. 6, as shown in the figure, the only memory in the single-chip microcomputer 12 is a RAM (memory readable and writable at any time) 18,
And a second ROM (read-only memory) 13 connected outside the chip of the microcomputer to constitute an elevator control device 11. The ROM 13 includes a diode bridge 2
The processing procedure necessary for controlling the elevator system composed of from the pulse generator 10 to the pulse generator 10 is stored.

Next, a specific operation of the embodiment of FIG. 6 will be described. First, when power supply to the elevator control device 11 is turned on, the single-chip microcomputer 12 rises from a reset state, a program counter is set to an address to be referred to first when power is established, and an address indicated on the address or indicated by the address is set. The operation starts with the initialization program P10 (FIG. 3) stored in the.

The initial setting program P10 is stored in the external second ROM 13. First, in a process P101, initial setting of the hardware of the microcomputer itself, for example, the entire area of the built-in RAM 18 is executed. To set the initial value of the interface such as whether to remove the uncertainty of the contents of the RAM 18 when the power is turned on or to use each pin of the counter 20 as an input side or an output side. Do.

Next, in a process P102, a process of transferring an application program and the like including the specification data stored in the external second ROM 13 to the built-in RAM 18 is performed. The application programs include an elevator speed command generation program, a car position detection program, a stop floor determination program, a speed control program, a PWM signal generation program for controlling a switch element in an inverter, an abnormal speed detection program, and the like.

The transfer processing is performed by the central processing unit 1
5 may transfer data one by one, or the central processing unit 15 may perform DMA (direct memory access) transfer without intervention. By the end of the transfer processing, the main processing of the initialization program P10 ends, and the processing P
At 103, the program counter returns to the interrupt waiting portion in the operating system, not shown. Since this operating system is also included in a part of the transferred application program, the address at which the program waits for an interrupt is also stored in the RAM in the microcomputer.
18 is stored in a certain predetermined area.

Here, the area allocated as the RAM 18 in the microcomputer is generally about 10 kB. Therefore, in an application where the capacity of the system program does not exceed this, the externally attached second ROM 13
Is transferred to the RAM 18 in the microcomputer, all the application programs started by the subsequent timer interrupt can be operated at high speed inside the microcomputer.

Therefore, according to the embodiment of FIG. 6, not only the high-speed operation of the program but also the mask ROM in the microcomputer is not used, so there is no need to mask the program, and the external ROM 13 is replaced with an EPROM or the like. A program that includes different specification data for each model may be burned and used each time, and the effect of eliminating the cost of masking is obtained.

Next, still another embodiment of the present invention is shown in FIG. As shown in FIG. 7, the embodiment of FIG. 7 uses only the first ROM (read-only memory) 17 as the memory in the single-chip microcomputer 12, the single-chip microcomputer 12 having the ROM 17, and the chip of the microcomputer. Externally connected second ROM (read only memory) 13
The ROM 17 stores the elevator model among the processing procedures required for controlling the elevator system including the diode bridge 2 to the pulse generator 10. A program such as an operation system that does not change the contents, a PWM signal creation program for controlling the switch element in the inverter, a stop floor determination program, and the like are stored in the second ROM 13, and a speed control program that changes the contents depending on the model of the elevator. And a program such as an abnormal speed detection program.

As a specific operation of the embodiment of FIG. 7, when the power supply to the elevator control device 11 is turned on, the single-chip microcomputer 12 rises from a reset state and returns to the address to be referred first when the power supply is established. The program counter is set, and the initialization program stored on the address or at the address indicated by the address starts operation.

This initialization program is stored in the first ROM 17 built in the microcomputer or the second ROM 1
First, the initial setting of the hardware of the microcomputer itself, for example, the initial setting of the interface such as whether each pin of the counter 20 is used as the input side or the output side, is performed. The counter returns to an interrupt waiting portion in the operation system (not shown).

Since this operation system is included in a group of application programs whose contents do not change depending on the type of elevator, the address at which the program waits for an interrupt also exists in a certain area in the first ROM 17 built in the microcomputer. Will do.

Accordingly, of the application programs started by the subsequent timer interrupt, the PWM signal creation program for controlling the switch element of the inverter and the stop floor determination program stored in the first ROM 17 built in the microcomputer are the microcomputers. It can be operated at high speed only inside.

Since the programs such as the speed control program and the abnormal speed detection program, the contents of which must be changed depending on the type of elevator, are stored in the external second ROM 13, the processing speed of this program is Is a little slower, but in particular P requires high-speed processing every hundreds of microseconds.
As described above, since the WM signal creation program and the like can be operated within the microcomputer at high speed with no wait, with high accuracy and high efficiency with a wide bus width, there is no particular problem. In the example, the cost reduction effect by using only one type of mask ROM in the single-chip microcomputer is more remarkable.

In the above embodiment, the case where the present invention is applied to an elevator control device has been described. However, it goes without saying that the present invention can be carried out regardless of the control target. Another feature is that a program with a high task level (of high activation frequency) is stored in a mask ROM in a single-chip microcomputer, and a program with a low task level is stored in an external ROM.

In this way, a program which has a high start-up frequency and greatly affects the processing time of the entire system can access the built-in ROM at a high speed, uses a wide bus width, and can perform non-divided access. The same effects as those of the embodiment described with reference to FIGS. 1 to 7 can be obtained, for example, the time required for the processing is short.

Further, according to the embodiment of the present invention, not only the activation frequency but also a program which takes a long time as a result of the activation frequency and the length of the program is stored in the mask ROM in the single-chip microcomputer. Can also be.
In this case, the program stored in the mask ROM can be processed at a high speed, so that the total processing time of the entire system can be reduced. Here, the present invention
The following is a list of other embodiments.
You. In the invention of claim 1 or claim 2, the I
The memory in the C chip is larger than the external memory
It is characterized by comprising a memory with a short read time.
Microcomputer control device. In the invention of claim 2,
The transfer processing according to the above transfer processing procedure is the first
The central processing
The equipment will be lifted according to this transferred procedure.
Is configured to control in real time
Elevator control device. Claim 2 or Claim 3
In the invention, the data stored in the second read-only memory is
Data are the rated speed of the elevator, the rated load,
Includes elevator specification data such as the number of floors to stop
An elevator control device characterized in that: Claim
Item 5. The invention according to Item 5, wherein the real-time control is performed by an elevator
Speed control or pulse width modulation control of power converter
Characterized by including one of the controls.
Control device. Any one of claims 1 to 3
In the above procedure, the elevator driving power
The processing procedure relating to the pulse width modulation control of the converter is described in the above I.
An element stored in a memory in the C chip.
Beta control device. Any one of claims 1 to 3
In the invention, the central processing unit and the memo in the IC chip are used.
The width of the bus connecting the
Make sure that the width is wider than the bus connecting read-only memory.
Elevator equipment characterized.

[0068]

According to the present invention, the processing by the central processing unit is executed according to the processing procedure divided and stored in the memory built in the single-chip microcomputer and the external memory. Depending on the start frequency of the procedure and the required processing time, it is possible to selectively use the internal memory with a high read speed and the external memory with a low read speed, thus achieving low cost while having high speed processing and high reliability. In addition, it is possible to provide an elevator control device which can easily cope with various small-quantity application fields.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an elevator control device according to the present invention.

FIG. 2 is an explanatory diagram showing the contents of a second read-only memory in one embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation according to an initialization program in one embodiment of the present invention.

FIG. 4 is an explanatory diagram showing contents transferred to a read / write memory at any time in a microcomputer according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation according to an abnormal speed detection program in one embodiment of the present invention.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a block diagram showing still another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Three-phase AC power supply 2 Diode bridge 3 Smoothing capacitor 4 Inverter 5 Current detector 6 Induction motor 7 Sheave 8 Car 9 Balance weight 10 Pulse generator 11 Microcomputer controller 12 Single chip microcomputer 13 External attached Read-only memory (second ROM) 14 external bus 15 central processing unit (CPU) 16 clock generator 17 first read-only memory in microcomputer (first ROM) 18 read / write in microcomputer as needed memory
(RAM) 19 analog-digital converter 20 counter 21 internal bus

Continued on the front page (72) Inventor Yuto Suzuki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Masahiro Konya 1-6-6 Kanda Nishikicho, Chiyoda-ku, Tokyo, Ltd. JP-A-4-49181 (JP, A) JP-A-1-275388 (JP, A) JP-A-63-315476 (JP, A) JP-A-5-139645 ( JP, A) JP-A-4-47147 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) B66B 1/00-1/52 B66B 3/00

Claims (3)

(57) [Claims] 1. A single-chip microcomputer in which a central processing unit and a memory are formed on the same IC chip, and an external memory connected to a bus of the single-chip microcomputer and outside the chip. In the elevator control device used, at least an elevator driving power converter is included in the elevator control processing procedure used in the central processing unit .
The processing procedure with high activation frequency including the processing procedure related to the pulse width modulation control of the above is stored in a memory built on the IC chip, and the processing procedure with low activation frequency is stored in the external memory. Elevator control device. 2. A single-chip microcomputer having a central processing unit and a readable / writable memory formed on the same IC chip, and an external device connected to a bus of the single-chip microcomputer outside the chip.
A read-only memory , wherein at least the elevator is used as the read-only memory.
Processing procedure for pulse width modulation control of driving power converter
And a transfer processing procedure for transferring the control processing procedure of the elevator to the memory that can be read and written at any time built on the IC chip. An elevator control device, wherein the central processing unit is configured to control the elevator in accordance with an elevator control processing procedure transferred to the writable memory. 3. A single-chip microcomputer in which a central processing unit and a first read-only memory are formed on the same IC chip, and an external second bus connected to the bus of the single-chip microcomputer outside the chip. An elevator control device comprising a read-only memory of the type described above, wherein a control processing procedure applicable to a plurality of types of elevators is stored in the first read-only memory, and the second read-only memory stores the type of elevator in the second read-only memory. The central processing unit controls the elevator according to the control processing procedures stored in the first and second read-only memories. Elevator control device.