JPS643790B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed command for an elevator, and particularly to a speed command generation device suitable for use in a digital computer.

[Conventional technology]

Generally, in order to obtain good elevator characteristics, when accelerating an elevator, the acceleration is performed according to the deviation between the acceleration command signal, which increases over time, and the output signal of the speed generator connected to the elevator. During deceleration, a method is adopted in which deceleration control is performed in accordance with the deviation between the output signal of the speed generator and a deceleration command signal that decreases in response to the deceleration position of the elevator.

In this case, in order to obtain good deceleration characteristics, it is necessary to include a large number of position elements in the deceleration command, which requires a large number of expensive position detectors, which increases costs and reduces reliability. This will lead to

Therefore, as a means to eliminate this drawback, a signal proportional to the rotation speed of the elevator drive motor is detected, this signal is counted by a counter, the output of this counter is decoded by a decoder, and this output is stored by a latch. Therefore, a method has been developed in which the number of position detectors is reduced by integrating signals proportional to the rotation speed of the electric motor to detect the traveling position of the elevator.

In this case, when the counter is input with a signal proportional to the rotation speed of the electric motor, it is kept in a state where it can count this signal, and until the elevator reaches the deceleration starting point, the counter is kept in a state where it can count the signal proportional to the rotation speed of the electric motor. It is conceivable to detect the running position of the elevator by not inputting the signal, but by inputting it from the deceleration start point and counting the signal proportional to the rotational speed of the electric motor with a counter.

However, in such a method, the deceleration pattern is determined so that the acceleration/deceleration is approximately constant in consideration of ride comfort, so the relationship between the elevator stopping distance and the speed becomes a square root curve. Therefore, adjusting the counter and decoder that counts the number of pulses and converts them into a speed curve is a complicated task, and the cost is also very high.

In addition, during acceleration, a load compensation circuit was used to prevent sudden acceleration, or to prevent the elevator from moving once in the opposite direction to the starting direction and then proceeding to the destination direction. .

However, this load compensation circuit uses relay contacts to switch analog circuits that generate acceleration patterns depending on multiple types of loads.

As a result, the circuit becomes complicated, and compensation can only be made based on the greatest common denominator for the various buildings in which the elevator is installed, resulting in a reduction in service to elevator users.

Therefore, the problem was raised that elevator speed commands were generated by switching multiple circuits and making delicate adjustments to elements, and by using a digital computer and digital-to-analog converter,
A device that can generate speed commands for a plurality of types of elevators with a single circuit configuration has been desired and has been developed.

FIG. 1 is a block diagram of a conventional elevator speed control system using a digital computer. Elevator car 1, along with counterweight 2,
It is suspended from a sheave 4 via a rope 3 in a hanging shape. The sheave 4 is connected to an elevator driving three-phase induction motor 6 and an electromagnetic brake 7 via a speed reducer 5. 8 are connected.

R, T, S are three-phase AC power supplies, main contact circuit 17
Switching between raising, lowering, maintenance operation, normal operation, etc. is performed using a combination of switches, and the thyristor control device 1
6. Here, the thyristor control device 16 is composed of a thyristor or a combination of a thyristor and a switch, and is controlled by the phase shifter 15. The phase shifter 15 performs feedback control by inputting the signal from the speed generator 8 using a digital calculation, for example, a microcomputer 14 as shown in FIG. With this feedback control,
The elevator car 1 can be operated at a speed similar to the speed command 18 generated by the microcomputer 14.

The speed command 18 is generated by the microcomputer 14 which receives the position signal from the waveform shaping circuit 12, the speed signal from the speed generator 8 (waveform shaping circuit 13), the elevator control device 19, and the internal clock. Ru.

Here, the above-mentioned position signals include a signal when the position detectors 10 and 11 attached to the car 1 operate when they cross the shield plate 9 provided in the tower, and a signal from the elevator car 1. The signal from the position detector of the floor controller 40, which simulates the position of the elevator car, is obtained via the waveform shaping circuit 12.

The microcomputer 14 is indicated by the broken line in FIG.
MPU) 20, determines the operation timing of this MPU 20 and monitors the progress of a specific time interval.
a clock 21 for informing the microcomputer 14, and peripheral interfaces (PIA) 22, 2 for exchanging digital external signals with the microcomputer 14.
3, 24, 25, ROM (read only memory) 26 in which the operating procedure manual of the MPU 20 is written;
A RAM (random access memory) 27 used for temporary storage as a work area for the MPU 20, a data bus 28 for exchanging data between each element,
It consists of a control bus 29 that selects addresses and elements of memories, etc., and exchanges clocks, interrupt signals, etc. For the output signals of the speed generator 8 and the waveform shaping circuit 13, the register of the PIA 22 is set so as to recognize the rising or falling edge of the signal and set a flag. The position signal from the waveform shaping circuit 12 is set to receive a digital signal.
Input to PIA23. A speed command to the phase shifter 15 is output from the microcomputer 14 via a D/A converter 30 and a filter circuit 31 that convert the digital signal output from the PIA 24 into an analog signal. Inputs from the operation panel of the elevator maintenance personnel and the elevator control device 19 (FIG. 1) are input to the PIA 25 via the input/output device 32.

Microcomputer 14 with such a configuration
is operated by a program as shown in FIG. The main program 100 is initialized 10 after the elevator is powered on or restarted in the event of a failure.
1, processing 102 for when the elevator is stopped, processing 103 for starting elevator operation, processing 104 for generating an acceleration patter, and processing 10 for generating a steady running pattern.
5. Process 106 for generating a deceleration pattern, forming a closed loop that returns to the process during elevator stop when deceleration is completed.

As shown in FIG. 4, the initialization step 101 includes a step 110 in which the MPU 20 does not accept interrupts, a PIA 22, 23, 24,
Initial value setting step 111 that determines the input/output direction selection of step 25, how to set a flag when the rising (or falling) of the input is recognized, and the initial setting of a clock (hereinafter referred to as a timer) that notifies the passage of a certain period of time. Value setting step 112, step 113 where the variable COUNT for determining how far the acceleration has been made is set to zero, step 114 setting initial values for the internal registers of the MPU 20 such as the stack pointer and index register, and canceling the interrupt mask. Step 11:
5, and step 116 to return to the main program 100.

Step 102 while the elevator is stopped is the fourth step.
It consists of processing unrelated to step 113 in the figure and the speed command.

Step 103 for starting elevator operation is the fifth step.
As shown in the figure, step 301 detects the load state of the elevator from the PIA 25 and determines the load state, and when the load is light, step 30 sets the index register to the start address of pattern A.
2. Furthermore, after executing one of the steps 303 in which the index register is set to pattern B if the load is heavier than pattern A, and the start address of pattern Z (FIG. 10) is set to the index if the load is heavy, Step 304 outputs the data at the address indicated by the index to the D/A converter 30 via the PIA 24, and the contents of the index register and
The program consists of a step 305 in which the contents of the memory whose address is the value added to the value of OFS is assigned to the timer, a step 306 in which the contents of the index and counter are incremented by 1, and a step 307 to return to the main program.

The acceleration generation pattern 104 includes a step 400 in which the elevator is in a dynamic stop state (entering a closed loop from the outside and appearing as if it is in a stopped state) until the timer finishes counting, and a step 400 in which the count number is in a divided operation (the elevator is running on a short floor). When servicing the next time, the vehicle should be operated at an intermediate speed without accelerating to the maximum speed due to the relationship between acceleration and deceleration. Step 401 to decide whether to perform the divide operation, step 402 to set the index to the start address with the divide operation pattern (see Figure 10), and step 402 to set the index to the start address with the divide operation pattern (see Figure 10); if the divide operation is not to be performed, ignore step 402 and proceed to the next step. Steps 304 to 306 similar to those shown in FIG. The program consists of step 403 and step 404 for returning to the main program.

Processing 105 during steady running includes step 501 in which the output of the D/A converter is held, the start address of the deceleration pattern is entered in the index register, and the dynamic stop is held until the position signal 12 of the deceleration start point is input. Step 50
3. When a signal to start deceleration is received, the contents of the memory with the contents of the index as an address are output to the D/A converter 30, and the variable is used to count the number of pulses of the speed generator and generate the next speed command. COUNT
Step 50 of assigning the contents of the memory indicated by the address obtained by adding the contents of the index and OFS to
4. Step 505 returns to the main program 100.

Step 106 for generating a deceleration pattern includes:
It is determined whether the position detector is operating from the contents of PIA23, and if it is operating, step 602 is performed.
If it is not operating, proceed to step 601.Step 600; If the rising (or falling) of the pulse of the speed generator (PG) 8 is not detected, return to step 600Step 601: Check the pulse of the speed generator (PG) 8 If the content of COUNT is detected, the content of COUNT is decreased by 1 in step 603. If the content of COUNT does not become zero, the process returns to step 600, and the content of COUNT becomes zero and it is determined whether the time to change the speed command has come in step 604. step 605, incrementing the content of 1 by 1; step 602, which determines which position detector has operated if the position detector has operated; step 504, which is executed next;
Step 60: Determine whether the deceleration end position detection has been activated, and if the operation has not been completed, proceed to Step 600.
6. Step 607 of returning to the main program 100. Here, step 6 of determining the operating position
As shown in FIG. 9, step 02 is step 6 in which it is determined whether or not the position detector (abbreviated as positive) A has operated, and if it has operated, the process advances to step 613.
10. Step 6 to determine whether positive B has operated
11. Step 612 to determine whether the last positive has operated; step 613 to substitute the operating address of positive A to the index if positive A is operating; step 614 to substitute the operating address of positive B to the index; The program consists of step 615 in which a deceleration end flag is set and the index register is set to the final positive operation address, and step 616 in which the process returns to the main program.

FIG. 10 shows a memory map. Memorizes multiple patterns such as acceleration patterns and deceleration patterns,
Steps 302, 303, 402, 502, 61
The speed command pattern is changed every time 3,614 is executed.

With such a software configuration, when the elevator control device 19 notifies the microcomputer 14 of a departure signal, the microcomputer 14 executes step 103 in FIG. in this case,
Assuming that the load on the elevator is light and the operating speed is accelerated to the maximum speed, store the value of the first address ADRA of pattern A in the memory map shown in FIG. 10 in the index register,
Set the count value to zero. This step 103
Next, the data at the address indicated by the index, ie, the data at ADRA in the memory map of FIG. 10, is output to the PIA 24. Then the above
The output from the PIA 24 is converted into an analog signal by a D/A converter 30, passes through a filter 31, and is passed through a phase shifter 1.
Output to 5. The phase shifter 15 then controls the speed of the elevator car to match the input to the phase shifter. Next, the microcomputer 14 regards the contents of the index register plus the offset value (OFS) as an address, and
The ADRA+OFS data _T0 of the address map shown in FIG. 10, which is written in the ROM 26, is retrieved and stored in the software timer.
Store in TIMER.

The contents of the index register at this time,
Time 0 in FIG. 11a shows the relationship between the contents of COUNT and the output of the D/A converter. Also,
The waveform of the output of the D/A converter 30 in this case is
As shown in FIG. 2a, when the output passes through the filter circuit 31, the speed command 18 in FIG. 12b becomes the speed of the elevator car, and the relationship shown in FIG. 12c corresponds to zero time.

Next, assume that the COUNT value is i and the microcomputer 14 is executing step 400.

In this way, the case where i=1, that is, the case where step 103 is executed and step 104 is executed, can be considered in the same way, so here we will use a representative example.
Let the COUNT value be i.

TIMER already stores the value T _i-1 for counting time, so when that value becomes zero, the 11th
In Figure a, the microcomputer 14 executes the program so that the index value ADRA+i, the COUNT value i, and the output of D/A are set to D _i as indicated by the relationship of time _i 〓 ^R=0 _TR . In this case, D/A converter 3
The relationship between the output of 0, the speed command 18, and the speed of the car 1 is the value shown at time _t1 in FIG. In this way, when the COUNT value reaches e or the index value reaches ADRA+e, acceleration is terminated, the speed command is kept constant, and the vehicle enters a steady running state. When performing heavy load or short floor operation, set the index value to the address where the pattern is stored, for example short floor operation.
When set to ADRDV, different patterns can be generated using exactly the same procedure.

Next, the deceleration is executed at step 504 in FIG. 7 when the elevator position detector A operates. In this case, the index register is set at step 502 to the start address where the deceleration pattern is stored, that is,
Since it is set to ADPA, data D _pa of the index-qualified address is output to PIA24 which is output to the D/A converter, and D _paf is stored in COUNT.
Every time the output pulse of the AC speed generator 8 is input,
When the value of COUNT is subtracted and the value of COUNT becomes zero, the value stored in the index is increased by 1, ADPA+1 is added, and the data D _ap+1 stored at the address of ADPA+1 is stored in the PIA24.
The value obtained by adding the contents of the index register and OFS is the address, that is, the data of ADPA + 1 + OFS.
D _paf+1 is stored in COUNT, and a loop is entered in which the COUNT value is decreased each time a pulse from the AC speed generator 8 is input again.

In this way, as shown in Fig. 11b,
Pulse number 0, D _paf and index register,
The relationship between the outputs of the D/A converters is established.

Moreover, when the elevator position detectors 10 and 11 operate for the purpose of correcting the error of the AC speed generator,
For example, when the *th position detector operates, the speed command output is forced to match the position. That is, when the *th position detector is determined to be in operation in the operation position detector determination step 602, the contents of the index register are set to ADP* regardless of the value before the position detector was activated. When the position is corrected in this manner and the program returns to step 504 in FIG. 8, the MPU 20 outputs D _p* to the D/A converter and sets the COUNT value to P _{p *f} . This relationship is represented by b in FIG. 11.

When the final position detector operates, the elevator speed command is set to zero, the elevator is stopped, and the microcomputer 14 enters a standby state until it receives a restart signal from the control device 19.

Here, Figure 12a shows the relationship in Figure 11 with time and the number of pulses of the speed generator on the horizontal axis, and the output of the D/A converter on the vertical axis, and the output of this D/A converter. The speed command smoothed through the filter 31 is shown in Fig. 12b.
5 controls the speed of the elevator car 1 as shown in FIG. 12c to provide a comfortable ride for passengers.

Note that since the speed of the elevator car is determined by the speed command 18, the intermediate speed during short floor operation is determined by selecting the divide operation pattern, that is,
The value of the index register is set to ADRDV in Figure 10.
What can be achieved by doing so becomes obvious from the above explanation.

With this configuration, the values of the pattern table shown in Figure 10 can be sent to the D/A converter by using the same circuit for generating acceleration commands and deceleration commands, without switching them using relay contacts as in the conventional case. By sequentially outputting the signals, an elevator speed command can be generated.

Therefore, conventional analog circuits such as load compensation, acceleration command, short floor operation, and deceleration command, as well as relay circuits for switching these circuits, are no longer necessary, simplifying the device and improving reliability.

Also, by being able to prepare multiple speed commands,
The speed command curve can be easily changed depending on the passenger situation, greatly improving riding comfort.

Furthermore, adjustments based on the floor spacing of individual buildings where elevators are installed can be realized by changing the numerical values in the data table.

In addition, the elevator was previously adjusted by hardware based on the capacity of the elevator motor 6, the power supply frequency, the reduction ratio of the reduction gear 5, the diameter of the sheave 4, etc., but this can be realized by changing the data table.

As a result, it is possible to standardize elevator speed command devices.

[Problem to be solved by the invention]

However, in the above-mentioned conventional elevator speed control device using a digital computer, the timing for switching the pattern during acceleration is set at step 400, for example.
405, the processing time of the MPU 20 is devoted to this purpose. Furthermore, during deceleration, most of the processing is spent in steps 600, 601, 603, and 604, so the microcomputer does not have time to perform other tasks.

SUMMARY OF THE INVENTION An object of the present invention is to provide an elevator that can improve the operating efficiency of a digital computer and perform good elevator speed control.

[Means to solve the problem]

A feature of the present invention is that a digital computer for speed control stores a plurality of speed command values according to the load condition of the elevator, and a storage means for storing a count value corresponding to an interval at which the speed command values are read. , is installed separately from the microprocessor that counts pulses by inputting time pulses at fixed time intervals during acceleration and travel pulses at fixed distance travel during deceleration, and generates an interrupt signal when the pulses match the set count value. and the interrupt signal of the measuring means reads out the corresponding speed command value stored in the storage means to generate a speed command, and reads out the next count value stored in the storage means to the measuring means. It is equipped with a microprocessor for configuration.

〔Example〕

FIG. 13 shows a block diagram of a circuit according to an embodiment of the present invention. The pulse output of the AC speed generator 8, waveform shaper 13 is connected to an external clock terminal of a programmable counter-timer element, PTM 33 for short.

Here, the operation of this PTM 33 will be explained using the block diagram of FIG.

The PTM 33 is connected to the data bus 28 of the microcomputer 14, the control bus 29 including a clock and address bus, and the output of the AC speed generator 8 via the waveform shaping circuit 13.

MPU 20 can write data on the data bus to control register 50 and latch 52 via buffer 53. Further, the contents of the counter 51 and the contents of the flag register 61 are read into the MPU 20 via the buffer 53.

Although the PTM 33 can be used in various ways depending on the data written in the control register 50, the functions necessary for generating a speed command will be described here. First, as a first usage, the control register 50 is set to the control bus 29.
The operation starts when the reset signal of the control bus 29 is received, or when a specific bit of the control register becomes zero.
Add the internal clock signal of 1 to the signal line 62, connect the clock changeover switch 60 to the signal line 62 side,
Each time the falling edge of the internal clock is detected, the value in the counter 51 is decremented, and as soon as it reaches zero, an interrupt signal is output to the control bus 29, and a flag indicating that the count has ended is set in the flag register 61. Further, when the interrupt flag is set to the flag register 61, the contents of the latch 52 are stored in the counter 51,
Again, the contents of the counter are decremented internally by the clock.

Further, data can be written to the latch 52 at any time.

In this way, an instruction code that causes the PTM 33 to operate is stored in the control register 50, and the PTM 33 is used when accelerating the speed command.

In the second usage, the changeover switch 60 is changed over so that the counter 51 selects the external clock, and the other operations are the same as in the first usage, and a code is stored in the control register 50.

In this way, the PTM 33 can be used to measure the number of pulses of the AC speed generator 8 during deceleration.

The connection of the PTM 33 is as described above, and the other parts are the same as in FIG.

In such a circuit configuration, the microcomputer 14 generates a speed command according to a procedure manual (program) written in the ROM 26 and shown in FIG.

The main program 1000 includes an initialization step 1001 that determines constants necessary for the program after the microcomputer is powered on or reset (restarts the microcomputer), a step 1002 that controls the movement of the elevator while the elevator is stopped, Step 1003 for starting elevator operation, Step 1 during elevator acceleration
004, Step 100 during steady elevator operation
5. Step 1006 for elevator deceleration, and interrupt processing 1007 when an interrupt occurs. Unlike the previous embodiment, the procedure for generating a speed command uses interrupt processing except for step 1003.

First, the initialization step 1001 is the first step.
As shown in Fig. 6, steps 110 and 111 are the same steps as in the conventional method, and to simplify the explanation, the first method of using the PTM 33 will be described here.
PTM-A, PTM-B that performs the second usage 2
Used individually, and together they are called PTM33.

Therefore, in step 1102, the codes for the first and second usage methods are stored in the control registers of PTM-A and PTM-B, respectively, to the control registers that define the operation of this PTM, and the operating state of the elevator is set. Step 110
3, and steps 114, 115, and 116.

The elevator operation start step 1003 is the 17th step.
As shown in the figure, enable PTM-A and
The counter of PTM-A is microcomputer 1
The PTM is set to count down every time the internal clock of 4 is input, and when the counter reaches zero, it generates an interrupt signal, puts the contents of the latch in PTM-A into the counter, and starts counting down again. Initial value setting step 130
0. Steps 301, 302, 303 for switching patterns depending on the load condition of the elevator; Step 13 for outputting the contents of the memory whose address is the contents of the index register to the D/A converter 30.
01. Step 1302: Assign the data whose address is the contents of the index register plus OFS to assign the time when the next interrupt will occur to the latch of PTM-A. Step 1303 to increase and accelerate the status flag, return step 130
It consists of 4.

The interrupt determination step 1007 in FIG.
Steps 600 and 602 in the figure
Step 2001 to determine whether PTM-A has generated an interrupt, step 2002 to determine the operation of PTM-B, acceleration processing 2012 to be executed when PTM-A operates, and when PTM-B operates , step 2004, incrementing the contents of the index register by 1, step 2005, outputting the index-qualified memory data to the D/A converter, and assigning the index-qualified memory data with OFS to the latch of PTM-B; It is determined that the deceleration has ended, and if the deceleration is in progress, the process skips to step 2003 for returning from the interrupt, and if the deceleration has ended, the process skips to step 1002 (step 2006).

The acceleration processing step 2012 includes a step 2200 in which the content of the index register is incremented by 1 as shown in FIG.
Step 2 of assigning the contents of index-qualified memory with offset OFS to the latch of
201, Step 2203 for returning from interrupt
It is made up of

Further, the signal to start deceleration can be realized by receiving a signal from the position detector, that is, by changing step 613 as shown in FIG. 20, assuming that the position detector is set to positive A in FIG. Here, step 660 assigns the address of the reference table when positive A operates to the index register, counts down PTM-B using the external clock, that is, the output of the waveform shaping circuit 13 as the input of the counter,
When the contents of the counter reach zero, send an interrupt signal.
This step is to send the data to the MPU 20, input the data previously stored in the latch into the counter, and set it to count down again.

Furthermore, after the acceleration and deceleration of the elevator are completed, the operations of PTM-A and PTM-B are stopped.

With this configuration, step 4 in Figure 6
PTM-A processes steps 00, 405, and PTM-A processes steps 601, 603, and 604 in FIG.
B acts on your behalf.

Further, by making the operation position detection an interrupt process, step 600 can be omitted.

However, according to an embodiment of the present invention, PTM
If the internal clock added to step 33 is accurate, the software timer (steps 400, 405)
It is more accurate and can generate an interrupt at any time.

The same applies when decelerating.

From these facts, by generating the speed command 18 using the PTM 33, the time that the MPU spends for speed commands is reduced to several percent of that of conventional devices.
The MPU will be able to perform other tasks, for example the tasks of the elevator control unit 19.

〔Effect of the invention〕

According to the present invention, acceleration, deceleration, and load compensation can be realized by a microcomputer by changing a speed pattern reference table stored in a memory, so that acceleration pattern generation circuit, deceleration pattern generation circuit, load compensation circuit, It is not only possible to omit the switching circuit and the switching circuit, greatly reducing the number of parts and simplifying the circuit.
The operating efficiency of microcomputers can be greatly improved.

In addition, until now circuit constants and the like had to be changed depending on the model, making adjustments complicated, but since the circuits can be standardized, inventory management, production equipment, etc. can be easily managed.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram illustrating operation management of an elevator speed control device using a conventional digital computer;
Fig. 2 is a schematic diagram of a microcomputer for implementing the device shown in Fig. 1, Fig. 3 is an overall configuration diagram of a program for operating the microcomputer, and Fig. 4 is a diagram for setting initial values of the microcomputer. FIG. 5 is a flowchart for the start of elevator operation, FIG. 6 is a flowchart for generating an elevator acceleration pattern, FIG. 7 is a flowchart for generating a steady running pattern, and FIG. 8 is a flowchart for generating an elevator acceleration pattern. FIG. 9 is a flowchart for determining the operation of the position detector; FIG. 10 is a memory map of the reference table; FIG. 11 is an explanatory diagram showing the relationship between outputs and index registers; Fig. 12 is a schematic diagram of the output of the microcomputer and the speed of the elevator, Fig. 13 is a schematic diagram of the microcomputer for explaining an embodiment of the present invention, and Fig. 14 is a schematic diagram of the microcomputer output and elevator speed.
A block diagram of the PTM, FIG. 15 is an overall configuration diagram of a program according to an embodiment of the present invention, FIG. 16 is a flowchart for setting initial values of the microcomputer, and FIG. 17 is a flowchart for starting operation. Figure 18 is a flowchart for generating an interrupt determination and deceleration pattern, Figure 19 is a flowchart for generating an acceleration pattern, and Figure 2 is a flowchart for generating an acceleration pattern.
FIG. 0 is a flowchart when the deceleration start signal is received. DESCRIPTION OF SYMBOLS 1... Elevator car, 6... Elevator drive alternator, 8... Speed generator, 10, 11... Position detector, 12, 13... Waveform shaping circuit, 14... Microcomputer, 15... Phase shifter, 16... Thyristor control device, 18... Speed command, 19... Elevator control device, 20... Microprocessor, 21...
Clock (MPU), 22, 23, 24, 25... Peripheral input/output device (PIA), 26... Read only memory (ROM), 20... Random access memory (RAM), 28... Data bus, 29... Control bus, 30 ...D/A converter, 31...filter,
33...Programmable timer unit (PTM).

Claims (1)

[Scope of Claims] 1. In an elevator speed command generation device that uses a digital computer to generate an elevator speed command, the digital computer stores a plurality of speed command values according to the load state of the elevator, and A memory means for storing a count value corresponding to the interval at which the speed command value is read, and a time pulse for each fixed time during acceleration and a running pulse for each fixed distance traveled during deceleration are inputted and counted. A measuring means provided separately from the microprocessor generates an interrupt signal when it matches the count value, and the interrupt signal of the measuring means reads out the corresponding speed command value stored in the storage means and generates a speed command. and a microprocessor for reading out the next count value stored in the storage means and setting it in the measurement means.