JP2929242B2 - Processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing apparatus for processing an object under reduced pressure.

[0002]

2. Description of the Related Art In general, when performing system control, a priority is given between states of respective apparatuses, and when a state of one apparatus or a combination of states of a plurality of apparatuses is a predetermined condition,
It is necessary to interlock regardless of a control request for a certain device.

[0003] Such an interlock will be described with reference to FIG. 3 which schematically shows a part of an apparatus by taking a part of a processing step of a semiconductor wafer as an example. In the system of FIG. 3, the first transfer robot 2 placed outside the processing chamber 1
A, the unprocessed wafer is temporarily accommodated in the load lock chamber 3, then the pressure in the load lock chamber 3 is reduced to the same degree as that in the processing chamber 1, and then the wafer W is transferred to the load lock chamber 3 by the second transfer robot 2 B. From above to the turntable 1A in the processing chamber 1, and thereafter, for example, processing such as ion implantation is performed.

In such a system, for example, in order to open the gate G1 on the atmosphere side (the first transfer robot 2A side) of the load lock chamber 3, the gate on the processing chamber 1 side is closed and the inside of the load lock chamber 3 is closed. Is normal pressure. Therefore, even if a control command to open the gate G1 due to a malfunction of the main controller or the like is received and the above condition is not satisfied, an interlock is applied and the gate G1 is not opened. Need to be

Conventionally, a method of providing such an interlock function to a system is as follows: (1) A method of interlocking by detecting information of a constituent unit of each device by software in a system controller for giving a control request to each device; (2) A method of collecting information related to the interlock of each device constituent unit in one place, and applying an interlock by hardware based on the information, that is, an interlock logic circuit common to each device constituent unit; A method of independently providing an interlock logic circuit for each device configuration unit has been adopted. The device configuration unit is a portion corresponding to each function unit when each device is divided into function units.

[0006]

However, in the method using software as described in the above (1), the state of each section can be detected only discretely, for example, once per second, and an accurate interlock can be obtained. If the software is erroneously operated, all the interlocks are invalidated, and there is a possibility that the operator, the object to be processed and the apparatus itself may be damaged.

On the other hand, in the method of interlocking by hardware collectively as in the above (2), the state of each unit can be collectively and continuously viewed, so that an accurate interlock can be applied. It is excellent in that the safety of the device can be ensured because it is not affected by the malfunction of software. However, on the other hand, if the scale of the system is large and complicated, the logic of the interlock becomes large and complicated by that much, and a large number of steps are required for debugging the logic circuit. In addition, if there is an increase in the information on the interlock due to a change in the logic circuit of the interlock or the addition of a device configuration unit, an extremely troublesome operation of reassembling a large-scale hardware becomes necessary.

In the method of providing an interlock logic circuit independently for each device configuration unit as in the above (3), interlock across device configuration units cannot be performed. For example, in the example of the above-mentioned semiconductor wafer processing step,
The mechanism for opening and closing the gate G1 and the sensor for detecting the pressure in the load lock chamber 3 are configured as the same unit, that is, as a unit of the apparatus. Although an interlock can be applied to the "open" request, there is a problem that the interlock cannot be applied when the state of another device constituent unit, for example, the gate G2 is open. Further, when an operation different from the normal operation is performed, for example, at the time of starting the apparatus or at the time of maintenance, the interlock may hinder the work.

SUMMARY OF THE INVENTION The present invention has been made under such circumstances, and its object is to provide a highly reliable interlock logic which can be easily assembled, and which can easily cope with system changes. It is another object of the present invention to provide a processing apparatus capable of ensuring high work efficiency even when a control mode such as a work level is switched.

[0010]

According to a first aspect of the present invention, there is provided a processing chamber for processing an object to be processed under reduced pressure, a load lock chamber interposed between the processing chamber and the atmosphere, and an atmosphere. 1st opening / closing mechanism between the side and the load lock chamber by an opening / closing mechanism
A second gate for opening and closing between the load lock chamber and the processing chamber, and a pressure sensor for detecting a pressure in the load lock chamber. The opening / closing mechanism for the first gate and the pressure sensor constitute one unit, and an interlock controller provided corresponding to the unit and a unit connected to the interlock controller. , An interlock information transmission path for taking in status information of another device configuration unit into the interlock controller, wherein the interlock controller transmits status information of its own device configuration unit. Self-state storage means for storing, other-state storage means for storing state information of other apparatus constituent units, and own apparatus configuration by performing a logical operation based on the state information stored in these storage means Interface outputs a control command to position - with a locking logic circuit, a, b to the self-state storage means -
When it is stored that the lock chamber is at a normal pressure and the other state storage means stores that the second gate is open, the above-mentioned control request for opening the first gate is received. A control instruction to close the first gate is output from the interlock logic circuit.

According to a second aspect of the present invention, in the first aspect of the present invention, the interlock controller has a work level storage means for storing at least a mode selected from an operation mode or a maintenance mode. When the operation mode is stored in the work level storage means, the self-state storage means stores that the load lock chamber is at a normal pressure, and the second state is stored in the other state storage means. When the open state is stored, even if a control request to open the first gate is received, the first gate is received from the interlock logic circuit.
When the maintenance instruction is output to the work level storage means, the self-state storage means stores that the load lock chamber is at normal pressure and the other state storage means. Even if it is stored that the second gate is open, when the control request to open the first gate is received, the control to open the first gate from the interlock logic circuit is performed. It is characterized by outputting an instruction.

[0012]

The output information of each interlock logic circuit is exchanged with each other via an interlock information transmission line, and each interlock logic circuit outputs the information based on other necessary output information.
Alternatively, an interlock logical operation is further performed in consideration of the state of its own device constituent unit. When control mode information is given to the transmission path, each interlock logic circuit takes in the information and executes an interlock logic operation according to each control mode. For example, when an apparatus configuration unit is added or changed, it can be dealt with by rearranging the logic of only the interlock logic circuit related thereto.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In an embodiment of the present invention, as shown in FIG. 1, interlock controllers B1 to Bn having an interlock function are independently provided for each of the device constituent units A1 to An (details will be described with reference to FIG. 2). The interlock logic circuits B1 to Bn are connected to the system bus 5 to which the system controller 4 is connected.
Connect via Cn. Here, the system bus 5 transmits a control request from the system controller 4 to each of the device constituent units A1 to An, and transmits each of the device constituent units A1 to An
Is a transmission path for transmitting the state to the system controller 4.

The device constituent units A1 to An are connected to the input / output units C1 to Cn, respectively, and control requests output from the system bus 5 are transmitted to the interlock controllers B1 to Bn via the input / output units C1 to Cn, respectively. After being processed here, it is given to the device constituent units A1 to An via the input / output units C1 to Cn, and the device constituent unit A
The input / output units C1 to Cn respectively correspond to the status signals 1 to An.
To the system bus 5 and the interlock controllers B1 to Bn.

Further, each interlock controller B1
To Bn are connected to each other by an interlock bus 6 as an interlock information transmission path. Each interlock controller B1 to Bn supplies the interlock bus 6 with a status signal of its own device configuration unit, and outputs its own device. The status signal of another device constituent unit related to the interlock of the constituent unit is fetched from the interlock bus 6 and handled as one of the input conditions for interlocking the own device constituent unit.

A work mode setting circuit OS for setting a control mode, for example, a work level, is connected to the interlock bus 6, and the work level set here is transmitted to the entire system via the interlock bus 6. Or partly given. The operation levels are classified into, for example, a mode for debugging the apparatus, a mode for starting the apparatus, a mode for maintaining the apparatus, and a mode for operating the apparatus.

Here, an example of the configuration of each interlock controller and each input / output unit will be described with reference to FIG. In this example, the input / output unit 7 (corresponding to each of C1 to Cn) is constituted by a microprocessor 7a and a dual port memory 7b, and these are used to connect the system bus 5 and the interlock controller 8 (each of B1 to Bn). ) And the device configuration unit 9 (corresponding to each of A1 to An).

The interlock controller 8 has a control request register 8a for storing a control request from the system controller 4, a self status register 8b for storing the status of its own device configuration unit, and a current control mode. For example, a work level register 8c for storing a work level and a state of another device constituent unit related to its own interlock (an interlock performed by the interlock controller 8 on the device constituent unit 9) are stored. The other state register 8d and an interlock logic circuit 10 for performing an interlock logical operation using the contents stored in each of the registers 8a to 8d as an input condition and outputting an actual control instruction for the device constituent unit 9 are provided. In the interlock controller 8, the work state register 8c and the other state register 8d are connected to the interlock bus 6 respectively.
Is connected to the microprocessor 7a and the interlock bus 6.

Next, the operation of the above embodiment will be described.

For example, if a control request for the device configuration unit A1 is written into the dual port memory 7b of the input / output unit C1 by the system controller 4 via the system bus 5, this control request is sent to the microprocessor 7
a and is stored in the control request register 8a of the interlock controller B1. On the other hand, the state of the unit A1 is periodically collected by the microprocessor 7a, and its contents are written to the dual port memory 7b for transmission to the system controller 4 and stored in the self-state register 8b.

The interlock controller B1
Fetches the current work level and the state of other device constituent units related to the interlock of its own device constituent unit into the work level register 8c and the other state register 8d by the interlock bus 6, respectively, and registers each of the registers 8a to 8d.
An interlock logic operation is performed by the interlock logic circuit 10 using the output signal of 8d as an input condition, and a control instruction as a result of the operation is given to the device configuration unit A1 via the microprocessor 7a and the interlock bus 6
As output information. Since this output information is the state of the unit A1 at that time, the unit A
The state of 1 is given to the interlock bus 6.

When such an action is made to correspond to the wafer processing step described in the section of “Prior Art”, the load lock chamber 3
The unit that opens and closes the atmospheric gate G1 (see FIG. 3) corresponds to, for example, the unit A1, and the state of the unit stored in the self-state register 8b is, for example, whether the pressure inside the load lock chamber 3 is normal pressure. No, and the status of the other unit captured in the other status register 8d is, for example, whether the gate G2 of the load lock chamber 3 on the processing chamber 1 side is open or closed. Then, when the interlock controller B1 receives a control request to open the gate G1 on the atmosphere side, if the gate G2 on the processing chamber 1 side is open even if the inside of the load lock chamber 3 is at normal pressure, the operation of the apparatus is started. At the level, interlock logic 1
0 outputs a control command to close the gate G1 regardless of the control request. However, for example, at the maintenance work level, when it is required to open the gate G1, an interlock logic may be formed so as to output a control command to open the gate G1.

In this example, since the opening / closing mechanism of the gate G1 and the pressure sensor in the load lock chamber 3 are used as one device constituent unit, the detection result of the pressure is set as the state of the own device constituent unit, and the state of the interlock logic circuit 10 is changed. However, the present invention can also be applied to a system that does not consider its own state as the interlock condition of each device constituent unit. In this case, the input condition of the interlock logic circuit is used as its own device constituent unit. The state of is unnecessary.

In the above, a specific configuration example of each section of the above embodiment will be described.

The interlock controller 8 is configured as, for example, a card unit, and these are installed so as to be housed in the same card gauge, and each interlock controller is wrapped on an interlock bus 6 using a backplane (motherboard). If the system 8 is connected, when the system is changed, only the related card unit can be easily changed, so that it can be easily handled.

The signal path between the input / output unit 7 and the unit 9 may be a serial line or a parallel line. For example, the signal line is a serial line using a microprocessor 7a, and this is an optical fiber. This configuration is advantageous because the signal path can be made narrow, the reliability is high, and the isolation is excellent.

Further, since the software of the microprocessor of the input / output unit 7 does not affect the logic of the interlock, it can be used in common for all the interlock controllers 8.

The work level setting circuit OS is desirably realized by a configuration not controlled by the system controller 4, for example, a keyed switch, so that the software of the system controller 4 can withstand a malfunction.

As for the interlock logic circuit, a PLD (Programmable) is used so that it can be easily changed.
Logic Device) and FPGA (Field)
Programmable Gate array)
Etc. can be used.

The output information of each interlock logic circuit transmitted to the interlock information transmission path is not limited to the result of the logical operation itself. For example, the output information of the device configuration unit controlled by the result of the logical operation May be the detection result of the detection.

[0031]

As described above, according to the first or second aspect of the present invention, the interlock is realized by hardware, so that, for example, a software malfunction due to an abnormality of the system controller can be ensured. Can be interlocked to ensure high reliability.

Rather than gathering information on interlocks in one place, an interlock logic circuit is provided independently for each device configuration unit, and other devices required for each interlock logic circuit through an interlock information transmission path. Since the information of the configuration unit is taken in, even if the system is large-scale, the interlock logic may be assembled for each of the interlock logic circuits distributed, so that the design of the interlock logic becomes easy.

Further, since the interlock logic circuit is independent for each device configuration unit, only the units that are affected by the change of the interlock logic or the increase in the interlock information due to the addition of the device configuration unit are affected. Since the interlock logic circuit unit may be added to the changed or added device configuration unit, it is possible to easily cope with a system change, particularly a local change, and to provide an excellent system diffusibility. I have.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a main part of the embodiment shown in FIG. 1;

FIG. 3 is an explanatory view showing a part of a semiconductor processing step.

[Explanation of symbols]

 Reference Signs List 4 system controller 5 system bus 6 interlock bus A1 to An, 9 device configuration unit B1 to Bn, 8 interlock controller 10 interlock logic circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-84708 (JP, A) JP-A-2-287676 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G05B 9/02 H01L 21/08

Claims (2)

(57) [Claims] 1. A treatment for treating an object under reduced pressure.
And a load interposed between the processing chamber and the atmosphere.
Opening and closing mechanism between the lock chamber and the atmosphere side and load lock chamber
A first gate, which is opened and closed by
A second gate for opening and closing between the processing chamber and the load;
A pressure sensor for detecting a pressure in the lock chamber.
One bets closing mechanism and the pressure sensor - the device, the first gate
Equipment configuration unit, and provided corresponding to this equipment configuration unit.
Interlock controller and other devices connected to the interlock controller.
The status information of the structural unit is stored in the interlock controller.
And an interlock information transmission path for capturing the
The interlock controller has its own device configuration unit.
Self state storage means for storing state information of
State storage for storing state information of each device configuration unit
Means and state information stored in these storage means.
To perform a logical operation and issue a control command to its own device configuration unit.
And an interlock logic circuit for supplying a load to the self-state storage means.
Is stored, and the second gate is opened in the other state storage means.
When the first gate is opened,
Said interlock logic circuit
Output a control instruction to close the first gate.
A processing device characterized by the above-mentioned. 2. The interlock controller has a small number.
Select from at least operation mode or maintenance mode
When the operation mode is stored in the work level storage means .
The load lock chamber has a normal pressure in the self-state storage means.
Is stored and the second state is stored in the other state storage means.
Opens the first gate when it is stored that
Said interlock logic circuit
First gate from - outputs control instructions that closes the door, maintenance work level storing unit mode - de is stored
The load lock chamber is always in the self-state storage means.
Is stored in the other state storage means.
Even if it is remembered that the gate is open, the first
Upon receiving a control request to open the gate, the interro
Control instruction to open the first gate from the logic circuit.
The processing device according to claim 1, wherein the output is performed.