JP2927090B2 - Parallel control computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel control computer,
In particular, the present invention relates to a parallel control computer capable of operating a plurality of arithmetic units in parallel.

[0002]

2. Description of the Related Art Conventionally, there has been a computer that operates a plurality of built-in hardware in parallel by a control method described below.

In the first control method, the bit width of an instruction code is relatively widened, the instruction code is divided into bit fields for each hardware, and an instruction code is input from the outside in each machine cycle, so that a plurality of instruction codes are input. The hardware operates in parallel. This is the 1990 IEE International Solid State Circuits Conference Digest of Technical
Papers (1990 IEEE International)
nal Solid State Circuits
Confence Digest of Techni
cal Papers), No. WPM 3.3, No. 44
Pp. 45, February 1990, a 50 MHz microprocessor with a very long installation word architecture (A 50 MHz)
Microprocessorwith a Very
Long Instruction Word Ar
scheme).

In the second control method, a plurality of instruction codes are decoded at a time, and an erroneous operation result is obtained because of a hardware conflict or a change in the order in which data is written to a memory. Unless otherwise, 1
By issuing a plurality of instruction codes in a cycle, a plurality of hardware are operated in parallel. This is the 80960 CA Users' Manual from Intel, Inc. (80960 CAUser's Manual)
It is described in.

[0005]

In the above-described conventional parallel control computer, when the first control method is used, the bit width of the instruction code is required to be two to three times that in the case where the parallel control is not performed. There is a problem that the number of pins of the transmission connector increases and the bus width of the instruction memory also needs to be increased.

When the second control method is used,
Although hardware conflicts and problems in the calculation order are all determined by internal circuits, the circuit scale for this is large.
There is a problem that this tendency becomes more remarkable when the amount of hardware increases.

[0007]

A parallel control computer according to the present invention operates a plurality of hardware including an arithmetic unit in parallel.
In parallel control computer executing a predetermined process, the double
At least an indication of the usage of each of the hardware
And one or more bits of the plurality of signal lines, and monitors the use status of the plurality of hardware, wait until the state of use state is predetermined for at least one hardware of the plurality of hardware First with a waiting control function for
Enter the instruction code and enter the instruction code
And waiting control means for outputting a holding issue signal for the view, before
Store multiple instruction codes including the first instruction code
An instruction buffer and the holding issue signal are generated.
Only when indicating a line, the first instruction code or
Follows the first instruction code and the first instruction code
Instruction to send a second instruction code to the instruction decoder
Means .

[0008]

[0009]

According to the parallel control computer of the present invention, one instruction causes hardware to operate over a plurality of machine cycles. Here, the parallel operation of the hardware can be realized by executing the next instruction code Q while executing the instruction P for operating the hardware over a plurality of machine cycles. However, if the next instruction Q is issued at random while the preceding instruction P is being executed, the operation result is expected because the instruction Q tries to use the hardware used by the instruction P or the order of writing to the memory changes. The result may differ from the result. The following three methods can be considered as methods for solving the above problems.

(1) A circuit for constantly observing which hardware the instruction P uses and determining when the instruction Q can be issued is mounted.

(2) The hardware used by the advanced instruction P
Which part is completed and the subsequent instruction Q can be issued are described in a part of the instruction Q, and the instruction Q is issued if the conditions are satisfied.

(3) The hardware used by the advanced instruction P
An instruction code dedicated to waiting, which describes which part is completed when the subsequent instruction Q can be issued, is placed immediately before the instruction Q.

The method (1) is a control method similar to the conventional control method 2, and the methods (2) and (3) are control methods used by the parallel control computer of the present invention. In the method (1), when all instructions are issued, it is necessary to check for conflicts in all hardware, the order of data writing, and the like, and the control circuit becomes large-scale. When the number of hardware increases, the scale of the increase is remarkable. For example, when the preceding instruction P accesses consecutive addresses in the built-in register, a conflict must be detected for all addresses, which is not practical when the built-in memory increases.

In the control methods (2) and (3), only the instruction code specified to perform the queuing and the queuing of the specified conditions are performed, so that the control circuit is greatly simplified. Also, even if the number of hardware increases, the increase in the scale of the control circuit can be suppressed.

In particular, the control method (3) can be applied without changing the conventional instruction system by redefining the instruction code for performing a wait in a blank portion of the instruction system conventionally adopted. In this case, by adding a device to the instruction buffer, the instruction sent to the queuing controller is an instruction for queuing, and the instruction sent to the instruction issuer is a normal instruction following the queuing instruction. It is possible to eliminate overhead generated when issuing an instruction.

The basic queuing instruction code has the same bit width as other instruction codes that do not wait for the queuing function,
It shows what combination of signal lines from which the hardware outputs the status of use may execute the subsequent instruction. By adding the instruction code having the waiting function to a conventional instruction code system, the control part of the parallel control computer can be simplified.

Further, a part of the bit field of the instruction code is used exclusively for the waiting function, and the other bit fields are used for hardware control and program control, whereby the waiting instruction code can be obtained. In the case of 2, it is possible to provide any instruction code with an arbitrary waiting function.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3A shows an example of a queuing instruction code dedicated to queuing control, and FIG. 3B shows an example of a queuing instruction code having a bit field for queuing control.

In FIG. 3A, the 32-bit waiting instruction code is composed of a high-order 10-bit identification unit 101, an intermediate 20-bit monitoring instruction unit 102, and a low-order 2-bit function instruction unit 103. ing.

The identification unit 101 is used to identify that this instruction code is an instruction code only for waiting.

In the monitoring instruction unit 102, each bit corresponds to a signal line indicating the use status of the hardware to be monitored. For example, for a bit of "1", a signal line monitoring instruction is issued for each bit, such as monitoring the corresponding signal line. In this embodiment, the states of the 20 signal lines can be monitored.

Function instructing section 103 designates a waiting function, for example, as follows.

Reference numeral 00 denotes the monitoring instruction unit 102, which executes the next instruction when all signal lines corresponding to bits of "1" are "0".

Reference numeral 01 denotes a monitor instruction unit 102 which executes the next instruction when at least one of the signal lines corresponding to the bit of "1" is "0".

Reference numeral 10 denotes a monitoring instruction unit 102 which executes the next instruction when at least one of the signal lines corresponding to the bit of "1" is "1".

11 is unused.

In FIG. 3B, the 32-bit wait instruction code is composed of the upper 25 bits of the normal instruction code section 20.
1, a monitoring instruction unit 202 of 6 intermediate bits, and a valid flag 203 of 1 lower bit.

The normal instruction code unit 201 is used for controlling internal hardware and controlling a program.

The monitoring instruction unit 202 indicates the number of a signal line in the signal line indicating the usage status of the hardware to be monitored. Basically, when the monitoring target bit becomes “0”, the normal instruction code unit 201 is issued.

The valid flag 203 is a flag for validating the waiting control, and performs the waiting control only when it is "1".

FIG. 1 is a block diagram showing a first embodiment of a parallel control computer according to the present invention.

As shown in FIG. 1, the parallel control computer of this embodiment has three hardware components 1 to 1 to be monitored such as a computing unit.
3, an instruction buffer 4 storing a plurality of instruction codes 41 to 4n (n is an integer), a queuing controller 5 for performing queuing control by use status monitoring signals from hardware 1 to 3 to be monitored, and a queuing control An instruction issuer 6 for issuing an instruction under the control of the unit 5; an instruction decoder 7 for decoding the instruction;
3 and data buses 8 to 13 and hardware 1 to
3 is provided with signal lines 14 to 16 of 1 bit or more for transmitting the use state to the waiting controller 5 and a signal line 17 for transmitting an instruction update signal from the instruction issuer 6 to the instruction buffer 4.

Next, the operation of this embodiment will be described.

This embodiment corresponds to the waiting instruction code having the waiting control bit field shown in FIG. 3B.

First, the hardware 1 to 3 to be monitored are:
They are connected by data buses 8-13. In each of the hardware 1 to 3, the instruction buffer 4 that outputs the signal lines 14 to 16 stores instruction codes 41 to 4n to be executed by the computer from now on. The instruction code 41 is located at the top (upper end). The queuing controller 5 determines whether the input instruction code 41 is a queuing instruction code for performing queuing control. This determination is made based on whether the valid flag 203 of the instruction code 41 is “1”.

If the valid flag 203 is "1",
Therefore, if the instruction code 41 is a waiting instruction code, one or more sets of monitoring signals M1 to M3 for monitoring the use status of each of the hardware 1 to 3 input via the signal lines 14 to 16 are monitored. , They are instruction code 4
1 when it is instructed by the monitoring instruction unit 202, and outputs an instruction code P to the instruction issuer 6.
1 is issued.

If the valid flag 203 is "0",
Therefore, if the instruction code 41 is not the waiting instruction code, the instruction issuance signal P is output irrespective of the monitoring signals M1 to M3 input via the signal lines 14 to 16, and the instruction code 41 is output to the instruction issuer 6. Issue it.

The instruction issuer 6 outputs the instruction code 41 to the instruction decoder 7. The instruction decoder 7 decodes the instruction code 41 and generates a control signal C for controlling the hardwares 1 to 3. When the instruction issuer 6 issues the instruction code 41,
An instruction code sequence update signal R is output to the instruction buffer 4, and the stored instruction codes 41 to 4n are shifted to update the next instruction code to be executed. With the above configuration, the hardware 1 to 3 can be operated in parallel.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

This embodiment corresponds to the queuing instruction code dedicated to queuing control shown in FIG.

This embodiment differs from the first embodiment in that not only the first instruction code 41 of the instruction buffer 4 but also the instruction code 42 following the instruction code 41 are input to the instruction issuer 6. And instruction code 4
When 1 is a wait instruction code dedicated to wait control, the instruction issuer 6 can skip this and issue an instruction code 42.

According to the above configuration, there is an advantage that a temporal overhead at the time of issuing an instruction can be suppressed.

[0045]

As described above, the parallel control computer according to the present invention provides a queuing instruction code having a queuing control function.
Use this waiting instruction code and save the instruction code
Or wait to output a holding issue signal to instruct issuance
Control means and a plurality of commands including the waiting instruction code.
Instruction buffer to store the instruction code
Wait only when the hold issue signal indicates issue
Instruction code or wait instruction code and this wait
Instruction decoding is performed with the instruction code following the matching instruction code.
The Rukoto a command issuing means for sending the da, without increasing the bit width of the instruction code, moreover, to operate the hardware in parallel without the circuit scale increases even when increasing the amount of hardware There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a parallel control computer according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the parallel control computer of the present invention.

FIG. 3 is a diagram illustrating an example of a queuing instruction code dedicated to queuing control and an example of a queuing instruction code having a bit field for queuing control.

[Explanation of symbols]

 1-3 hardware 4 instruction buffer 5 queuing controller 6 instruction issuer 7 instruction decoder 8-13 data bus 14-17 signal line 41-4n instruction code 101 identification unit 102, 202 monitoring instruction unit 103 function instruction unit 201 normal instruction Code part 203 valid flag

Claims (5)

(57) [Claims] A plurality of hardware units including an arithmetic unit are connected in parallel.
A parallel control computer that operates and executes a predetermined process
Te, small indicating each state of use of said plurality of hardware
1 or more bits and a plurality of signal lines Kutomo, the use status of the plurality of hardware monitors, the plurality
At least first instruction code to input a command code having a queuing control function for waiting for one hardware used state is a state where a predetermined one of the hardware
Output a hold / issue signal that instructs hold or issue
Queuing control means for storing a plurality of instruction codes including the first instruction code;
Instruction buffer, and only when the holding and issuing signal indicates issuing,
A first instruction code or the first instruction code and the first
The second instruction code following the one instruction code
A parallel control computer comprising: an instruction issuing unit for sending to a coder . 2. The parallel control computer according to claim 1, wherein the first instruction code has a bit field for the waiting control function in a part of the instruction code. 3. The method according to claim 1, wherein the first instruction code is
That the command is an instruction code dedicated to queuing control
And each bit indicates the usage status of the monitored hardware.
A monitoring instruction unit corresponding to the signal line, and a function instruction unit for performing a function instruction of waiting
Wherein the waiting is a control dedicated instruction code 請
The parallel control computer according to claim 1 . (4) The first instruction code is an internal hardware
Normal instruction code part used for controlling hardware and programs
When, Each bit indicates the usage status of the monitored hardware
A monitoring instruction unit corresponding to the signal line; Has a valid flag to enable the wait control
Be characterized by that The parallel control computer according to claim 2. (5) The first instruction code is the first instruction code.
Which part of the first hardware that uses the
If the following instruction code can be issued,
And placed immediately before the subsequent instruction code,
Issue the following instruction code when the instruction issue condition is satisfied
The parallel controller according to claim 2 or 3, wherein
Arithmetic.