JPH08161170A - Microprocessor and its controlling method - Google Patents

Abstract

PURPOSE: To improve internal processing while holding the interchangeability of hardware by providing a microprocessor with a mechanism capable of setting up the line width of an instruction cache equally to the width of an instruction in a VLIW(very long instruction word) architecture type microprocessor and suppressing the issue of an instruction until the line of the cache is satisfied. CONSTITUTION: When the fetch of an instruction is necessary, a bus controller 1 fetches an instruction with n-bit length through an external instruction data bus 4 with n-bit width. The control of a fetch cycle for (n/m)=p times is executed by the bus controller 1 based upon a cache control signal 6 while checking the status of a tag in the cache 2 until the line of the cache 2 is satisfied with n-bit length. Then the instruction is hited in the cache 2 through an internal instruction data bus 5 with n-bit length. Namely the stored n-bit width instruction to be executed is sent to a decoder 3 through an internal instruction data bus 7 with n-bit length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VLIW (Very Long Instr-uction Worth) in a microprocessor system.
d) Concerning the architecture type microprocessor.

[0002]

2. Description of the Related Art As a conventional example, an instruction fetch (fet) in a VLIW architecture type microprocessor is used.
FIG. 3 is a block diagram showing the circuit configuration of ch) and the decoding part. The VLIW architecture type microprocessor allows the compiler to statically (before executing) each ALU (Arithmeti
c and Logic Unit) One execution part having a plurality of ALUs executes the scheduled instruction so that each of them can perform a parallel operation.
For the above reason, one instruction becomes long and cannot be decomposed, and the width of the data bus becomes very long. And for that reason, in the microprocessor,
It also has the drawback that it is difficult to maintain upward compatibility of hardware. This is because the instruction length changes when the number of internal execution units is increased (or decreased), and the width of the external bus also changes. In operation, when it is necessary to fetch an instruction, the bus controller 1 fetches the n-bit long instruction described above through the external instruction data bus 3 having an n-bit width. Thereafter, this instruction is sent to the decoder 2 via the internal instruction data bus 4 which is also n bits long. The instruction is interpreted by the decoder 2 and, for example, ALU0 [0th AL
U] control signal 5, ALU 1 [first ALU] control signal 6 and other control signals to each ALU and other control signals 7 for memory control.

[0003]

However, in the technical means in the conventional example, there is no VLIW architecture type microprocessor provided with a mechanism for solving the above-mentioned drawbacks. Therefore, when the number of internal ALUs is increased in order to increase the speed, the instruction length increases, and therefore the width of the data bus also increases, and there is a problem that upward compatibility at the hardware level cannot be obtained. Therefore, in the present invention, the line width of the instruction cache is mainly made equal to the instruction length in the VLIW architecture type microprocessor, and further, by having a mechanism which does not issue the instruction until the cache line is filled, the data bus width And the instruction length width can be different, the VLIW
The purpose is to maintain upward compatibility at the architecture type hardware level, and also to provide a means to effectively utilize the existing boards and other assets formed in the past, and to migrate to a processor with a new architecture. .

[0004]

In order to solve the above problems, in the present invention, the instruction cache line width is set to VL.
The IW architecture type microprocessor has a width equal to the instruction width, and a mechanism for not issuing an instruction until the cache line is filled is provided. Therefore, by setting the width of the external data bus of the VLIW architecture type microprocessor to a size different from the instruction width of VLIW, even if the data bus length and the instruction length of VLIW architecture are different, the instruction of VLIW architecture is given to the execution unit. Can be executed. In addition, VLI has been expanded due to function expansion.
Since the width of the data bus can be made constant even if the W instruction length increases, it is possible to keep the upward compatibility of the hardware. In this way, the instruction length of the VLIW architecture type microprocessor in the microprocessor system is the line length of the instruction cache, and a circuit for delaying the instruction issue until the line of the instruction cache is filled is provided. It is a microprocessor of VLIW architecture having upward compatibility of hardware because the instruction length can be changed. That is, the present invention is
In the LIW architecture type microprocessor,
A microprocessor of the VLIW architecture type having a circuit for making the line width to the instruction cache equal to the width of the VLIW instruction and not issuing an instruction until the line of the instruction cache is filled. An instruction code is introduced from a connecting m-bit wide bus line, and a bus controller that outputs to the instruction cache by a control signal to the instruction cache sent from itself through the m-bit wide bus line, and from this bus controller When an instruction code continuously input every m bits is repeatedly received p times and the consecutively stored instruction code becomes n bits long, the instruction code is sent to the decoder through the n bit wide bus line. The cache to output and the instruction code accepted from this cache A decoder that force to control the receiving and storing and feeding of the instruction code in the cache,
The microprocessor according to the above paragraph, further comprising a cache controller that accesses a reception of the instruction code by using a bus controller when the instruction code does not hit, and m < n through an m-bit wide bus line,
The microprocessor control method according to the preceding paragraph, wherein an n-bit long instruction is fetched into the instruction cache in an m-bit wide p cycle, and the n-bit long instruction is issued after a line of the instruction cache is filled. Is.

[0005]

According to the present invention, because the instruction length of the VLIW architecture type microprocessor is long and cannot be decomposed, the bus line width of n bits inevitably increases. By storing it in the cache, forming the instruction length again to n bits there, and then outputting it, the instruction bus line from the higher order can be configured with m bits, and the cache from the output stage to the decoder has an n-bit width. Bus line is good, VLI
In the W architecture microprocessor, the bus width can be matched in the past or the future, and the compatibility of the hardware can be maintained.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. In each drawing, the same reference numerals represent the same or corresponding members. FIG. 1 shows a block diagram of an instruction fetch and decode portion showing a circuit configuration of an embodiment of the present invention. It is necessary to fetch the instruction from the cache 2 when the instruction to be executed is in the cache 2 and from the external memory [not shown] when it is not in the cache 2. Thus, when it becomes necessary to fetch an instruction, the bus controller 1 fetches an n-bit long instruction through the m-bit wide external instruction data bus 4. However, in the present invention, since n> m, the fetch cycle is (n / m) = p
Cycle required.

The control of the fetch cycle of (n / m) = p times is performed by the bus controller 1 using the tag of the cache 2.
The status (status) of (Tag) is checked, and the operation is continued until the cache control signal 6 reaches the n-bit length for filling the line of the cache 2. After that, this command is also n
It is stored in the cache 2 through the internal instruction data bus 5 having a bit length. An instruction that is hit in the cache 2, that is, a stored instruction having an n-bit width to be executed, is sent to the decoder 3 through the n-bit internal instruction data bus 7.

Thereafter, the decoder interprets the instruction, and A
A control signal for each ALU such as LU0 control signal 8 and ALU1 control signal 9 and other control signal 10 for performing memory control and the like are generated. Note that the cache 2 has the cache controller 61 under the condition set by the control condition setting 65.
Is controlled by a cache controller control signal 62 from the cache controller, and information is transmitted / received by an answer back signal 63 for the control. Further, the bus controller 1 also performs an operation such as fetching an external instruction by the bus controller control signal 64 from the cache controller 61. To do. The bus controller 1 also serves as an interface between the microprocessor and the outside world such as reading external instructions.

FIG. 2 is a block diagram showing the circuit configuration of another embodiment of the present invention. In this specific example, the VLI
The instruction length of the W architecture type microprocessor is 12
The width of the external data bus is 8 bits and the width of the external data bus is 32 bits. When it becomes necessary to fetch an instruction from an external memory, the bus controller 1 fetches a 128-bit long instruction in four cycles through the 32-bit wide external instruction data bus 4. This control is performed until the bus controller 1 sees the status of the tag of the cache 2 and the cache line is filled with the cache control signal 6. The instruction hitting the cache 2 to be executed is sent to the decoder 3 through the 128-bit internal instruction data bus 7. The decoder 3 interprets the instruction, and the AL
A of each of the U0 control signal 8 and the ALU1 control signal 9
A control signal for the LU and another control signal 10 for controlling the memory are generated.

[0010]

As described above, according to the present invention, the bus width can be made equal to that of a newly created VLIW architecture microprocessor and of course a VLIW architecture microprocessor already designed and existing in the past. It is possible to achieve a special effect that internal processing can be improved while maintaining hardware compatibility. Furthermore, although the processing capacity is somewhat sacrificed, the number of data buses can be suppressed when the LSI is used, and thus it has an effect of reducing simultaneous switching noise due to a change in signals on the bus.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a VLIW instruction fetch and decode unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a VLIW instruction fetch and decode unit according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a circuit configuration of a conventional VLIW instruction fetch and decode unit.

[Explanation of symbols]

1 bus controller 2 cache 3 decoder 4 external instruction data bus [m bit width] 5 internal instruction data bus [n bit width: n> m and n = p
・ M] 6 Cache control signal 61 Cache controller 62 Cache control signal 63 Answer back signal 64 Bus controller control signal 65 Control condition setting 7 Internal command data bus 8 ALU0 control signal 9 ALU1 control signal 10 Other control signals

Claims (3)

[Claims] 1. In a VLIW architecture type microprocessor, the line width to an instruction cache is set to VLI.
VLIW with a circuit that makes the width of the W instruction equal and does not issue the instruction until the line of the instruction cache is filled
A microprocessor characterized by being of architectural type. 2. An instruction code is introduced from an m-bit wide bus line connecting to an external instruction database, and the instruction cache is controlled by a control signal to the instruction cache sent from itself via the m-bit wide bus line. To the bus controller for outputting to the bus controller, and the instruction code continuously input by the m-bit width from the bus controller is repeatedly received p times, and when the continuously stored instruction code becomes n-bit length, the instruction code is output. A cache that outputs to the decoder via a bus line of n-bit width, a decoder that outputs the instruction code accepted from this cache, controls the acceptance, storage, and sending of the instruction code in the cache, and the instruction code hits Access the instruction code acceptance by the bus controller when not The microprocessor according to claim 1, further comprising a cache controller. 3. When fetching an instruction from an external memory, an n-bit long instruction is fetched into the instruction cache in an m-bit wide p cycle through an m-bit wide bus line with m <n, 2. The method of controlling a microprocessor according to claim 1, wherein the instruction of the n-bit length is issued after the line of the instruction cache is filled.