JP2926880B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to the formation of contact wiring of an integrated circuit device formed on a Si substrate. The purpose of the present invention is to form a contact wiring without deteriorating the rectification characteristics of the p / n junction, and to characterize the method of manufacturing a semiconductor device of the present invention. A step of depositing a contact metal layer, usually Ti, on the entire surface of a semiconductor substrate having a connection hole and a second region, for example, a large diameter connection hole in the peripheral circuit portion; Etching the contact metal layer covered in the second region and covering the second region, and after removing the mask layer, contacting the entire surface of the semiconductor substrate with a second thickness contact. A step of depositing a metal layer, wherein the second thickness does not cause an increase in contact resistance when a wiring layer is provided on the contact metal layer via a barrier layer, and the semiconductor substrate The present invention is configured as a thickness that does not degrade the rectification characteristics of the p / n junction formed therein.

[Industrial applications]

The present invention relates to the formation of a contact wiring of an integrated circuit device, and particularly to the formation of a barrier layer when providing an Al contact wiring on a Si substrate.

As an internal wiring material for integrated circuits (hereinafter abbreviated as IC),
Conventionally, various materials have been used. However, as wiring patterns have been miniaturized with higher integration, usable materials tend to be limited to those having low resistivity.

Al is widely used as an IC wiring material because of its low resistivity and easy film formation and patterning.However, if pure Al is used to form IC wiring on a Si substrate,
In some cases, Si on the substrate is sucked up and the shallow pn junction is destroyed. Breakdown of the pn junction due to Si uptake occurs when Al invades the substrate in place of the uptaked Si, and the metallized structure extends inside in a spike shape.

Therefore, in order to prevent Si absorption, Si
However, in order to obtain the effect, it is necessary to add 1 to 2% of Si exceeding the solid solution limit.

However, when such a high concentration of Si is added, epitaxial growth using Si in Al as a raw material occurs at a contact portion with the Si substrate, and a new problem of increasing contact resistance occurs. Although this epitaxial growth does not occur over the entire bottom surface of the connection hole, the Si layer, which has a much higher resistance than Al, partially intervenes at the Al / Si interface, so the effective contact area Is reduced, and the resistance is increased. In particular, since the epitaxially grown Si layer contains Al as a p-type impurity as an impurity, the contact resistance to n-type Si is significantly increased.

[Conventional technology]

Conventionally, the processing to suppress the epitaxial deposition of Si in Al on the substrate surface has been performed by using the wiring layer
A barrier is provided between the Si substrates. Titanium nitride (TiN) is used as the barrier layer material. However, since contact resistance increases with TiN alone, a further titanium (Ti) layer is provided between the film and the Si substrate to reduce the contact resistance. I have. This Ti layer is commonly called a contact metal.

[Problems to be solved by the invention]

In the barrier layer having the TiN / Ti configuration, setting the thickness of the Ti layer is problematic. If it is too thin, the contact resistance will not be sufficiently reduced, and if it is too thick, the pn junction will be easily broken by Al. It is thought that this joint failure is due to the fact that the presence of Ti promotes the transfer of Al into Si.However, it is not necessarily a general tendency that the thicker the Ti layer, the more likely it is that joint failure will occur. Even, the thickness of the Ti layer that is usually adopted 200
It is empirically known that this tendency is observed when the distance is about 300 mm.

Table 1 shows data obtained experimentally by the inventor of the present application.
As shown in the table, when the Ti layer has a thickness of about 100 °, the contact resistance is high, and when the thickness is 200 ° or more, the contact resistance falls to a practical allowable value of 80 to 100Ω. On the other hand, the ratio of the reverse breakdown voltage of the pn junction defining the contact formation region, which maintains the specified value when the Ti layer exceeds 300 °, rapidly decreases. However, the diameter of the connection hole is 1.2 μmφ, acceleration processing for withstand voltage measurement is 450 ° C., 30 minutes + 500 ° C., 30 minutes, and the pass condition is a leak current of 10 ⁻¹⁰ A at a reverse bias of 5 V.

That is, according to the above data, the thickness of the Ti layer, which has low contact resistance and does not cause junction breakdown, is limited to an extremely narrow range centered at 200 °. It can be seen that the allowable range is narrow even if this value slightly varies depending on the contact forming conditions.

The Ti layer is usually formed by sputtering. However, in this method, it is inevitable that the thickness of the Ti layer deposited on the bottom of the small-diameter hole becomes smaller than the thickness of the Ti layer deposited on the open plane. However, in a highly integrated IC such as a 1M-DRAM, a wiring connection hole in a peripheral circuit portion has a diameter of 2 to 3 μmφ, whereas that in a memory cell portion is about 1 μm.

This means that if the thickness of the Ti layer deposited on the bottom of one hole is to be adjusted to the optimum value, the thickness of the Ti layer deposited on the bottom of the other hole deviates from the optimum value, When the allowable range of the thickness of the Ti layer is narrow as described above, it means that one of the contact wirings is likely to be defective.

Therefore, contact resistance is low while avoiding junction destruction.
In order to form an Al wiring, it is necessary to make the thickness of the Ti layer provided at the bottom of the connection hole constant by some measure regardless of the size of the opening diameter. An object of the present invention is to provide a processing method in which the thickness of a Ti layer provided at the bottom of a contact hole is constant regardless of the size of an opening diameter even when a contact metal layer is formed by sputtering. An object of the present invention is to provide a method of manufacturing an IC with further improved integration.

[Means for solving the problem]

In order to achieve the above object, a contact wiring forming process which characterizes the semiconductor device manufacturing method of the present invention includes a first region, for example, having a small-diameter connection hole in a memory cell portion, and a second region, for example, a peripheral circuit portion. A step of depositing a contact metal layer, usually Ti, on the entire surface of the semiconductor substrate having a large-diameter connection hole, covering a first region with a mask layer, typically a photoresist, and depositing it in a second region. Etching the contact metal layer, and applying a second thickness contact metal layer over the entire surface of the semiconductor substrate after removing the mask layer.

As a result of performing these steps, a contact metal layer having the same thickness as the open plane is formed on the bottom of the connection hole having a relatively large opening diameter, 2 above
The contact metal layer having the same thickness as that on the open plane is deposited by the repeated deposition of the contact metal layer.

The second thickness does not cause an increase in contact resistance when a wiring layer is provided on the contact metal layer via a barrier layer, and rectifies a p / n junction formed in the semiconductor substrate. The thickness is set so as not to deteriorate the characteristics.

[Action]

A small hole with an opening diameter of about 1μm, and the depth is 1/3 to 1/2 of the diameter
If it is larger, the thickness of the coating when applied by a method such as sputtering will be much smaller at the bottom of the hole than on the open plane. In an IC such as a DRAM, the memory cell array region has a higher integration density than the peripheral circuit region, and the diameter of the connection hole differs between these two regions, and the film thickness deposited on the bottom of the hole in one process is different. Is inevitable.

In the processing method adopted in the present invention, the contact metal layer applied to the peripheral circuit region is once removed and then applied again to a predetermined thickness. A contact metal layer having a sufficient thickness is formed on the bottom of the connection hole having the diameter by two deposition processes. On the other hand, a contact metal layer having a predetermined thickness is formed at the bottom of the connection hole in the peripheral circuit region only in the second film forming step.
Therefore, according to the processing method of the present invention, a film having a necessary and not excessive thickness is formed at the bottom of the connection hole regardless of the size of the opening diameter.

〔Example〕

1 (a) to 1 (f) are schematic sectional views showing steps of the present invention. Hereinafter, the processes included in the present invention will be described with reference to the drawings.

In FIG. 1A, reference numeral 1 denotes a Si substrate, 2 and 2 'denote diffusion regions provided with contact electrodes, 3 denotes a field oxide film, and 4 denotes a PSG film. 2 is provided with a contact wiring through a connection hole 5 of about 1 μmφ, and 2 ′ is provided with a contact wiring through a connection hole 5 ′ of 2 to 3 μmφ.

First, a Ti film 6 is deposited to a thickness of 100 ° by sputtering as shown in FIG. 4B, and then a photoresist 7 is applied on the entire surface as shown in FIG. Remove. Further, using the resist remaining in the memory cell region as a mask, the exposed Ti layer is etched away by immersion in an ammonium peroxide solution heated to 80 ° C.

The resist is removed using an incinerator, and a Ti layer 6 'is again deposited on the entire surface of the substrate to a thickness of 200 ° by sputtering. This state is shown in FIG. Since the diameter of the connection hole is large in the peripheral circuit area, a Ti layer is deposited to a thickness of approximately 200 mm on the bottom of the hole by the second sputtering, and the total of two sputterings is formed on the bottom of the connection hole in the memory cell area. Thus, a Ti layer having a thickness of about 200 mm is deposited. Although a Ti layer having a thickness of about 300 mm is deposited on the open plane portion of the memory cell region, there is no problem because the Ti layer does not contact the substrate Si.

In this way, the Ti required for the contact metal layer
After forming the layer, as shown in FIG. 4E, a TiN layer 8 is formed by sputtering to a thickness of about 1000 °, and FIG.
As shown in FIG. 1, an Al layer 9 containing 1% Si is formed to a thickness of 0.5 μm by sputtering, and is patterned by RIE to form a predetermined wiring pattern.

FIGS. 2 (a) and 2 (b) schematically show the cross-sectional shape of the contact wiring formed by the above processing. FIG. 3A shows that of a memory cell region, in which a contact memory layer is composed of a first Ti layer 6 and a second Ti layer 6 ′, and the entire thickness of the Ti layer at the bottom of the connection hole is approximately 200 °. On the other hand, that of the peripheral circuit area shown in FIG.
It is approximately 200 ° only for the Ti layer 6 ′.

〔The invention's effect〕

As described above, according to the present invention, a contact metal layer having a substantially constant thickness is formed irrespective of the diameter of the connection hole, so that the contact resistance is low and the pn junction is not broken. A contact wiring is formed.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing the steps of the embodiment, and FIG. 2 is a schematic view showing the difference in the contact wiring structure depending on the aperture. In FIG. 1, 1 is a Si substrate, and 2,2 'is a contact formation. Region, 3 is a field oxide film, 4 is a PSG layer, 5, 5 'are connection holes, 6, 6' are Ti layers, 7 is a resist, 8 is a TiN layer, and 9 is an Al layer.

Claims (2)

(57) [Claims] 1. A semiconductor substrate having a connection hole having a first opening diameter in a first region and a connection hole having a second opening diameter larger than the first opening diameter in a second region. Depositing a contact metal layer of a first thickness, covering the first region with a mask layer, etching away the contact metal layer deposited on the second region, and the mask Removing a layer, depositing a contact metal layer of a second thickness over the entire surface of the semiconductor substrate, the second thickness comprising a wiring layer on the contact metal layer via a barrier layer. Is provided and does not cause an increase in contact resistance and is formed in the semiconductor substrate.
A method for manufacturing a semiconductor device, characterized in that the thickness does not degrade the rectification characteristics of the p / n junction. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said contact metal is titanium (Ti), said barrier layer material is titanium nitride (TiN), said semiconductor substrate material is silicon (Si), and said wiring is Layer material is 1-2% Si
And the second thickness is 18 (Al).
A method for manufacturing a semiconductor device, wherein the angle is 0 ° to 250 °.