JP2925006B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having an MIM type capacitor.
The present invention relates to a semiconductor device such as an MIC.

[0002]

2. Description of the Related Art MESFETs using MESFETs as amplifying elements
MIC (monolithic microwave integrated circuit)
In the MIM, an interlayer insulating film is used as a capacitor dielectric film.
(Metal insulator metal) type capacitors are generally used, but depending on the circuit configuration of the MMIC, capacitors having a wide range of capacitance values (for example, several hundred fF to several tens pF) are required. In particular, a capacitor used for impedance matching or the like is required to have a small capacity and a high accuracy. On the other hand, in order to reduce the area of large-capacity capacitors, there is a trend toward forming thinner capacitor dielectric films in order to reduce the area, and wirings and through holes are also becoming finer.

FIGS. 2A to 2C are cross-sectional views in the order of steps showing a method for manufacturing a conventional MIM capacitor in an MMIC. First, a metal film is deposited on a semi-insulating GaAs substrate 1 and patterned to form a capacitor lower electrode 2a.
And the lower wiring 2b are formed. Next, CVD (chemical
A silicon nitride film 3 serving as a capacitor dielectric film is formed by using a vapor deposition method (FIG. 2A). Next, a photoresist film 10 having an opening at a predetermined position is formed by a photolithography method, and RIE (reactive ion etching) is performed using the photoresist film 10 as a mask to form a through hole 5 for connecting a wiring to the silicon nitride film. A hole is formed [FIG. 2 (b)]. Next, a metal film is deposited by a sputtering method, and the metal film is patterned to form a capacitor upper electrode 7a and an upper wiring 7b (FIG. 2C).

As the through-hole size is reduced by the structure and method of the prior art, a reaction product generated when the through-hole is formed by RIE adheres to the side and bottom surfaces of the through-hole. The contact resistance increases. Therefore, immediately before sputtering the metal film of the upper electrode and the upper wiring, the residue is removed by sputter etching to easily and effectively avoid the above-mentioned inconvenience (Electronic Materials, 1994, Vol. 40, etc.). For example, 5μ
In a through hole of m × 5 μm, the contact resistance is about 0.1Ω without sputter etching, but 1 μm × 1 μm
In the case of the through hole of m, it may be 1Ω or more. However, if the interlayer insulating film is a silicon nitride film,
By applying a sputter etch of about nm,
0.2 Ω contact resistance for through holes of m × 1 μm
Can be improved to a degree.

[0005]

For example, in the case of a matching circuit in an MMIC, a capacitor having a small capacitance value and a high precision (for example, 0.1 ± 5% pF) is required.
In the conventional manufacturing method in which sputter etching is performed in response to miniaturized wiring, it is becoming difficult to form the capacitor dielectric film with required accuracy due to the variation in film thickness reduction of the capacitor dielectric film due to sputter etching. In particular, since the capacitor dielectric film tends to be thinner in order to realize a large capacity without increasing the pattern size, the influence of the variation in the film reduction on the capacitance accuracy is increasing. For example, when a 10 nm sputter etch is applied to a silicon nitride film in a large area, a small area capacitor of 0 to 1
There may be a variation of 0 nm. The MMIC may also need a large-capacity capacitor.
When a silicon nitride film having a thickness of nm is used, after a sputter etch, a large-capacity capacitor is almost 70 nm thick and uniform, but a small-capacity capacitor has a variation between 70 and 80 nm, and is considered to be 75 ± 5 nm. Since the capacitance value C is C∝1 / d with respect to the film thickness d, the variation in the capacitance value is -6 to + 7.5%. Further, in the conventional manufacturing method, the difference in the thickness of the dielectric film between the large-capacitance capacitor and the small-capacity capacitor is different. There was also an inconvenience that the displacement increased. In addition, the capacitor portion is covered with a photoresist during RIE when a through hole is formed. However, if the coverage of the photoresist is poor, the capacitor dielectric film may be reduced in thickness, which also reduces the accuracy of the capacitance value. It was the cause of worsening.

Therefore, the problems to be solved by the present invention are:
Even if a sputter etch for removing a reaction product is performed after the opening of the through hole, the capacitor dielectric film (interlayer insulating film) does not decrease in film thickness, and a highly accurate capacitor can be formed with high reproducibility. Is to do so.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a high resistance to sputter etching and RIE on an interlayer insulating film prior to forming a through hole in the interlayer insulating film (capacitor dielectric film). The problem can be solved by forming a platinum layer in advance .

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, a lower electrode and a lower wiring of a MIM type capacitor are formed on a semiconductor substrate, and an interlayer insulating film serving also as a dielectric film is coated thereon. An upper electrode and an upper wiring of the MIM type capacitor are formed on the film, and the upper electrode and the upper wiring are formed on the interlayer insulating film.
And lower layer is etched by RIE and sputter etching
It is characterized by being formed of two or more conductor layers which are metal layers including a platinum layer having a low running speed .

Further, the method of manufacturing a semiconductor device according to the present invention comprises the following steps: (1) forming a first metal layer on a semiconductor substrate and patterning the first metal layer to form a lower electrode and a lower wiring of the MIM capacitor; (2) forming an interlayer insulating film also serving as a dielectric film on the lower electrode and the lower wiring of the MIM capacitor; and (3) forming a platinum layer having a low etching rate of RIE and sputter etching on the interlayer insulating film. Forming a second metal layer including : (4) forming a photoresist film having an opening on the lower wiring on the second metal layer; and (5) masking the photoresist film. Forming an opening by selectively removing the second metal layer, and (6) etching the interlayer insulating film using the photoresist film as a mask to form a through hole on the lower wiring. (7) forming a third metal layer on the front surface and patterning the third metal layer to form an upper electrode of the MIM capacitor and an upper wiring connected to the lower wiring via a through hole; And a process.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention and a method of manufacturing the same in order of steps. First, a tungsten silicide (WSi) film is deposited on a semi-insulating GaAs substrate 1 by a sputtering method to a thickness of 1000 .ANG., And a gold (Au) film is deposited to a thickness of 2000 .ANG. By photolithography. A resist film (not shown) is formed, and the gold film and the tungsten silicide film are selectively removed by ion milling using the resist film as a mask to form a capacitor lower electrode 2a and a lower wiring 2b. Then, over the entire surface of the semi-insulating GaAs substrate 1, the capacitor lower electrode, and the lower wiring, a silicon nitride film 3 serving as both a capacitor dielectric film and an interlayer insulating film for the wiring is grown to a thickness of 1000.degree. Let it.
Further, a platinum (Pt) film 4 having a thickness of 200 ° is deposited thereon by sputtering (FIG. 1A).

Next, a photoresist film (not shown) having an opening at a place where a through hole is formed is formed by photolithography, and the platinum film is partially removed by ion milling using this as a mask, and further by RIE. The silicon nitride film 3 is etched to form through holes 5 between wiring layers. Next, a sputter etch is performed on the entire surface (FIG. 1 (b)), and titanium (Ti) having a thickness of 500 mm is continuously formed.
A titanium film and a gold film having a thickness of 3000 mm are then deposited by sputtering to form a titanium / gold film 6. The sputter etching is performed for 10 nm by the etching amount of the silicon nitride film in a wide flat portion. Next, the titanium / gold film 6 is processed by an ion milling method using a photoresist film as a mask to form a capacitor upper electrode 7a and an upper wiring 7b (FIG. 1C).

Although the platinum film has a sufficient RIE resistance, the resistance to sputter etching is not sufficiently large, and the adhesion to the base may be insufficient. Therefore, when it is desired to increase the etching amount of the sputter etch to cope with finer through holes, or when there is a problem in the adhesion with the underlying silicon nitride film in a large area,
It is preferable to employ a two-layer film in which titanium is disposed under the platinum film, which has a smaller sputtering yield and good adhesion to the silicon nitride film.

[0013]

As described above, the semiconductor device according to the present invention includes the MIM type capacitor. The upper electrode of the capacitor and the upper wiring formed simultaneously therewith have a structure of two or more layers. Metal with low etching rate of RIE and sputter etching (such as platinum)
Since the film is employed, it is possible to prevent the capacitor dielectric film from being reduced in sputter etching for removing the reaction products attached to the through holes. Therefore, according to the present invention, it is possible to form a MIM capacitor having a wide range of capacitance values within the same IC with high accuracy irrespective of the capacitance value, while ensuring good contact properties of through holes between fine wirings. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in the order of steps showing an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional example in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 semi-insulating GaAs substrate 2a capacitor lower electrode 2b lower wiring 3 silicon nitride film 4 platinum film 5 through hole 6 titanium / gold film 7a capacitor upper electrode 7b upper wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/04 H01L 21/822 H01L 21/321 H01L 21/3213 H01L 21/3215

Claims (6)

(57) [Claims] A lower electrode and a lower wiring of the MIM capacitor are formed on a semiconductor substrate, and an upper surface thereof is covered with an interlayer insulating film also serving as a dielectric film, and the MIM capacitor is formed on the interlayer insulating film. upper electrode and the semiconductor device upper wiring is formed to be connected to the lower wiring, the upper electrode and the upper wiring is the interlayer insulating film
Metal layer der including slow platinum (Pt) layer underlying portion of the etching rate of RIE and sputter etching in the above
It is formed by two or more layers of conductor layers that, and, prior to
The metal layer is formed only on the upper surface of the interlayer insulating film.
Wherein a it is. 2. The metal layer has an upper platinum layer and a lower titanium layer.
2. A two-layer film of a Ti (Ti) layer.
13. The semiconductor device according to claim 1. 3. An upper layer of the upper electrode and the upper wiring.
The part is a two-layer film with the lower layer being a titanium layer and the upper layer being a gold (Au) layer.
The semiconductor device according to claim 1 or 2, wherein the being made. 4. A step of (1) forming a first metal layer on a semiconductor substrate and patterning the first metal layer to form a lower electrode and a lower wiring of the MIM capacitor; and (2) a lower electrode of the MIM capacitor. Forming an interlayer insulating film also serving as a dielectric film on the entire surface including over the lower wiring, and (3) forming a second metal layer including a platinum layer having a low etching rate of RIE and sputter etching on the interlayer insulating film. Forming; (4) forming a photoresist film having an opening on the lower wiring on the second metal layer; and (5) forming the second metal layer using the photoresist film as a mask. (6) etching the interlayer insulating film using the photoresist film as a mask to form a through hole exposing the surface of the lower wiring. And (7) forming a third metal layer on the entire surface and patterning the third metal layer to form an upper electrode of the MIM capacitor and an upper wiring connected to the lower wiring via a through hole. Of manufacturing a semiconductor device having the same. 5. The etching in the step (6) is performed by RI
5. The method according to claim 4, wherein the method is performed by an E method. 6. The method according to claim 4, further comprising, after the step (6), removing a residue in the through hole by sputter etching prior to the step (7). 6. The method for manufacturing a semiconductor device according to item 5.