JP2924856B2 - Semiconductor device mounting method - Google Patents

Semiconductor device mounting method

Info

Publication number
JP2924856B2
JP2924856B2 JP9144056A JP14405697A JP2924856B2 JP 2924856 B2 JP2924856 B2 JP 2924856B2 JP 9144056 A JP9144056 A JP 9144056A JP 14405697 A JP14405697 A JP 14405697A JP 2924856 B2 JP2924856 B2 JP 2924856B2
Authority
JP
Japan
Prior art keywords
solder cream
solder
semiconductor device
terminal
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9144056A
Other languages
Japanese (ja)
Other versions
JPH1070359A (en
Inventor
久則 丸山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP9144056A priority Critical patent/JP2924856B2/en
Publication of JPH1070359A publication Critical patent/JPH1070359A/en
Application granted granted Critical
Publication of JP2924856B2 publication Critical patent/JP2924856B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の実装
方法に係り、さらに詳しくは、プリント基板等に設けた
端子に半導体装置のリードを接続するためのはんだクリ
ーム塗布の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device, and more particularly to an improvement in applying a solder cream for connecting a lead of the semiconductor device to a terminal provided on a printed circuit board or the like.

【0002】[0002]

【従来の技術】半導体装置をプリント基板等に取り付け
る場合、従来は半導体装置のリードをプリント基板等の
端子に設けたスルーホールに挿通してはんだ付けしてい
たが、最近は電子機器の小形化、薄形化等の要請から、
プリント基板等の表面に半導体装置を載置して、リード
を直接端子に接続する表面実装方式が増加している。
2. Description of the Related Art Conventionally, when a semiconductor device is mounted on a printed circuit board or the like, the lead of the semiconductor device is inserted into a through hole provided in a terminal of the printed circuit board or the like and soldered. , From requests for thinning, etc.
2. Description of the Related Art A surface mounting method in which a semiconductor device is mounted on a surface of a printed circuit board or the like and leads are directly connected to terminals is increasing.

【0003】特に最近は、客先の仕様に応じて製造する
分野が拡大しており、高機能化によるI/O端子の増大に
伴って半導体装置はますます多リード化する傾向にあ
る。例えば、外形28mm×28mm、厚さ3.6mmの半導
体装置において、リードの数は160本、各リードの幅
が300μm、間隔が650μm程度のものが実用されて
おり、したがって、この半導体装置のリードが接続され
るプリント基板等の端子もこれに整合するものでなけれ
ばならない。
[0003] In particular, recently, the field of manufacturing according to the specifications of the customer is expanding, and with the increase in the number of I / O terminals due to the high functionality, semiconductor devices tend to have more and more leads. For example, in a semiconductor device having an outer shape of 28 mm × 28 mm and a thickness of 3.6 mm, a device having 160 leads, a width of each lead being about 300 μm, and an interval of about 650 μm is practically used. Must be matched to the terminal of the printed circuit board or the like to which is connected.

【0004】図6はこのような実装構造の一例を拡大し
て示したもので、(a)は正面図、(b)は側面図、
(c)は平面図である。図において、1はプリント基板
等、2はプリント基板等の表面に形成された導電パター
ンの如き端子、11はプリント基板等1に実装される半
導体装置、12はそのリードである。3ははんだの微粉
末とフラックスとをねり合わせてなるいわゆるはんだク
リームで、例えば図7に示すように、端子2の寸法、形
状に整合した窓8を有するマスク7を用い、端子2の表
面にスキージにより印刷したものである(以下塗布とい
う)。
FIG. 6 is an enlarged view of an example of such a mounting structure, in which (a) is a front view, (b) is a side view,
(C) is a plan view. In the figure, reference numeral 1 denotes a printed board or the like, 2 denotes a terminal such as a conductive pattern formed on the surface of the printed board or the like, 11 denotes a semiconductor device mounted on the printed board or the like 1, and 12 denotes its lead. Reference numeral 3 denotes a so-called solder cream formed by bonding fine powder of solder and flux. For example, as shown in FIG. 7, a mask 7 having a window 8 matching the size and shape of the terminal 2 is used. It is printed with a squeegee (hereinafter referred to as coating).

【0005】このようにして、各端子2にはんだクリー
ム3を塗布したのち、半導体装置11をプリント基板等
1の上に載置してリード12を端子2にそれぞれ当接
し、リフロー装置によりリフローすれば、リード12と
端子2はそれぞれ接続され、半導体装置11はプリント
基板等1に実装される。
After the solder cream 3 is applied to each terminal 2 in this manner, the semiconductor device 11 is placed on a printed circuit board 1 or the like, and the leads 12 abut on the terminals 2 respectively. For example, the leads 12 and the terminals 2 are respectively connected, and the semiconductor device 11 is mounted on a printed board 1 or the like.

【0006】[0006]

【発明が解決しようとする課題】上記のような半導体装
置の実装構造においてはマスク7の窓8の寸法、形状
は、端子2の寸法、形状と全く同じに形成されており、
一方、端子2の幅及び間隔はますます狭くなっているた
め、マスク7を利用してはんだクリームを塗布する際、
図8に示すようにはんだクリーム3が隣接する端子2間
を橋絡するいわゆるはんだブリッジ4が発生しやすい。
はんだブリッジ4が発生したときは、手作業によりこれ
を除去しているので、外観検査及びはんだクリーム3の
修正に多くの時間と人手がかかるばかりでなく、はんだ
クリーム3の修正によって二次的不良が発生することも
ある。
In the mounting structure of the semiconductor device as described above, the size and shape of the window 8 of the mask 7 are exactly the same as the size and shape of the terminal 2.
On the other hand, since the width and the interval of the terminals 2 are becoming increasingly narrower, when applying the solder cream using the mask 7,
As shown in FIG. 8, a so-called solder bridge 4 in which the solder cream 3 bridges adjacent terminals 2 is likely to occur.
When the solder bridge 4 occurs, since it is manually removed, the appearance inspection and the repair of the solder cream 3 take much time and labor, and the repair of the solder cream 3 causes secondary defects. May occur.

【0007】また、リフロー装置によってリード12を
端子2に接続すると、図9に示すように、はんだは外端
部5には裾を引かず、外部から見難いリード12の奥の
方(内側)6に引き込まれるため、外観検査によっては
んだ付けの良否を判定することが困難であった。
When the lead 12 is connected to the terminal 2 by a reflow device, as shown in FIG. 9, the solder does not have a skirt at the outer end portion 5 and the solder is hardly seen from the outside (inside). 6, it was difficult to judge the quality of soldering by visual inspection.

【0008】本発明は上記の問題点を解決すべくなされ
たもので、リフローの際にはんだクリームがリードの奥
に引き込まれることもなく、はんだ付け状態の外観検査
を容易にし、はんだブリッジの除去も容易にする半導体
装置の表面実装構造を得ることを目的としたものであ
る。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the solder cream is not drawn into the lead at the time of reflow. Another object of the present invention is to obtain a surface mounting structure of a semiconductor device which also facilitates the above.

【0009】[0009]

【課題を解決するための手段】本願発明の半導体装置の
実装方法は、基板上に設けられた複数の端子の表面には
んだクリームを塗布した後、リフローすることにより前
記複数の端子と半導体装置の複数のリードとを接続する
半導体装置の実装方法において、前記複数の端子それぞ
れに、前記はんだクリームの塗布量が、前記リードの先
端に近い側が前記半導体のパッケージに近い側より多く
なるように前記はんだクリームを塗布することを特徴と
する。
According to a method of mounting a semiconductor device of the present invention, a solder cream is applied to a surface of a plurality of terminals provided on a substrate, and then the reflow is performed to re-flow the plurality of terminals and the semiconductor device. In the semiconductor device mounting method for connecting a plurality of leads, the solder cream is applied to each of the plurality of terminals such that a side closer to a tip of the lead is larger than a side closer to the semiconductor package. It is characterized by applying cream.

【0010】[0010]

【0011】[0011]

【0012】[0012]

【0013】[0013]

【作用】リードの先端に近い側が半導体のパッケージに
近い側より多くなるようにはんだクリームを塗布するこ
とで、リフローの後、はんだがリードの奥に引き込まれ
ることが防止される。これによって、リード先端に半田
が集中して裾を広げるので、外部からのはんだ付け状態
が観察容易となる。これによってはんだ付け外観検査を
容易にし、はんだブリッジの除去も容易にする
By applying the solder cream so that the side closer to the tip of the lead is larger than the side closer to the semiconductor package, the solder is prevented from being drawn into the lead after reflow. As a result, the solder is concentrated on the tip of the lead and the skirt is widened, so that the state of soldering from the outside can be easily observed. This makes it easier to inspect the appearance of soldering and makes it easier to remove solder bridges

【0014】[0014]

【0015】[0015]

【発明の実施の形態】図1は本発明実施例の平面図であ
る。本実施例においては、はんだクリーム3の塗布長l
を端子2の長さlに対しl≠lとし、その幅W
を端子の幅Wに対してW<Wとしたものである。実
施例でははんだクリーム3の幅Wを0.6〜0.9W
とした。
FIG. 1 is a plan view of an embodiment of the present invention. In this embodiment, the application length l of the solder cream 3
1 is l ≠ l with respect to the length l of the terminal 2 and its width W 1
Is set to W 1 <W with respect to the width W of the terminal. 0.6~0.9W the width W 1 of the solder cream 3 in the embodiment
And

【0016】図5ははんだクリーム3の幅Wとリー
ド12の付着強度との関係を示す線図で、端子2に接続
したリード12に引張力を与えてその付着強度を試験し
たものである。図から明らかなように、W/Wが1
〜0.7までは6kg/mm以上の付着強度を有し、0.
6で約4kg/mmとなるが、0.5になると2kg/mm
と急に低下する。したがって、W/Wがほぼ
0.6〜0.9の範囲であれば、信頼性を失うことなく
実用に耐えうることがわかった。
[0016] FIG. 5 is obtained by testing the adhesion strength graph showing the relationship between adhesion strength, giving a tensile force to the lead 12 connected to the terminal 2 of the width W 1 and the lead 12 of the solder cream 3 . As is clear from the figure, W 1 / W is 1
Up to 0.7 has an adhesion strength of 6 kg / mm 2 or more.
6 is about 4 kg / mm 2 , but 0.5 is 2 kg / mm 2
It suddenly drops to 2 . Therefore, it was found that if W 1 / W was in the range of approximately 0.6 to 0.9, the device could be put to practical use without losing reliability.

【0017】また、W/Wが0.5〜1.0窓を有
するマスクを使用してそれぞれはんだクリーム3を印刷
したところ、はんだブリッジ4の発生はおおむね表1の
通りであった。
When the solder creams 3 were printed using a mask having a window of W 1 / W of 0.5 to 1.0, the occurrence of the solder bridges 4 was almost as shown in Table 1.

【0018】[0018]

【表1】 [Table 1]

【0019】図2は本発明の別の実施例を示すもので、
(a)図の実施例は、はんだクリーム3の幅Wは端
子2の幅Wと同じでW ≠Wであるが、端子2の半導
体装置11が載置される側(以下内側という)の端部に
ははんだクリーム3を塗布せず、反対側(以下外側とい
う)は端子2からはみ出してはんだクリーム2を塗布し
たものである。換言すれば、端子2とほぼ同じ長さで同
じ幅のはんだクリーム3を、端子2に対して外側にずら
せて塗布したものである。
FIG. 2 shows another embodiment of the present invention.
(A) In the embodiment of the figure, the width W of the solder cream 3 is shown.1Is the end
Same as the width W of the child 2 and W 1≠ W, but semi-conductive
At the end on the side on which the body device 11 is placed (hereinafter referred to as the inside)
Is not coated with solder cream 3 and is on the other side
) Protrudes from terminal 2 and applies solder cream 2
It is a thing. In other words, the terminal 2 has almost the same length and the same length.
Shift solder cream 3 of the same width outward with respect to terminal 2
And applied.

【0020】実施例では、はんだクリーム3を塗布しな
い部分の端子2の長さlと、端子2からはみ出した
部分のはんだクリーム3の長さlを、端子2の長さ
lに対してそれぞれ0.1〜0.41とした。この場
合、l=lとする必要はなく、適宜変更するこ
とができる。
[0020] In the embodiment, the length l 2 of the terminal 2 of the portion not coated with the solder cream 3, a length l 3 of the solder cream third portion which extends from the terminal 2, the terminal 2 with respect to the length l Each was set to 0.1 to 0.41. In this case, it is not necessary to set l 2 = l 3 and can be changed as appropriate.

【0021】(b)図の実施例は、端子2とほぼ同じ幅
のはんだクリーム3を、長さ方向に3つに分割(3a,
3b,3c)し、各はんだクリーム3a,3b,3cを
適宜間隔で塗布すると共に、外側のはんだクリーム3c
を端子2からはみ出して塗布したものである。なお、上
記の実施例では、はんだクリーム3を3つに分割した場
合を示したが、2つに分割してもよく、あるいは4つ以
上に分割してもよい。
(B) In the embodiment shown in the figure, the solder cream 3 having substantially the same width as the terminal 2 is divided into three in the longitudinal direction (3a, 3a).
3b, 3c) and apply the solder creams 3a, 3b, 3c at appropriate intervals,
Protruding from the terminal 2 and applied. In the above embodiment, the case where the solder cream 3 is divided into three is described, but the solder cream 3 may be divided into two or four or more.

【0022】また、(C)図の実施例は、はんだクリー
ム3を内側は端子2の幅より狭く、外側は広くかつ外側
にはみ出すように塗布したものであり、さらに(d)図
の実施例は(c)図の実施例のはんだクリーム3を分割
したものである。
In the embodiment shown in FIG. 2C, the solder cream 3 is applied so that the inner side is narrower than the width of the terminal 2 and the outer side is wider and protrudes outward. (C) shows the solder cream 3 of the embodiment shown in FIG.

【0023】上記図2(a)〜(d)に示した実施例に
おいては、はんだクリーム3を内側では少量に、外側は
多量に塗布したので、図4に示すようにリフローの際は
んだクリーム3が内側に引き込まれることはほとんどな
く、また先端部は十分裾を引くことができる。
In the embodiment shown in FIGS. 2A to 2D, a small amount of the solder cream 3 is applied on the inside and a large amount of the solder cream is applied on the outside. Therefore, as shown in FIG. Is hardly drawn inward, and the tip can be fully pulled down.

【0024】内側のはんだクリーム3を塗布しない部分
の長さlを種々変えて実験した結果は、表2の通り
である。
[0024] variously changed result of the experiment the length l 2 of the portion not coated with the inside of the solder cream 3 are shown in Table 2.

【0025】[0025]

【表2】 [Table 2]

【0026】図3は本発明のさらに別の実施例の平面図
で、(a)図の実施例は図1と図2(a)の実施例を組
み合せたもの、(b)図の実施例は図1と図2(b)の
実施例を組み合わせたもので、これらによれば、はんだ
クリーム3を塗布した際のはんだブリッジの発生を防止
できるばかりでなく、リフロー時のはんだクリームの内
側への引込みを防止することができる。
FIG. 3 is a plan view of still another embodiment of the present invention. FIG. 3 (a) shows an embodiment combining the embodiments of FIGS. 1 and 2 (a), and FIG. 3 (b) shows an embodiment of FIG. 1 is a combination of the embodiments of FIGS. 1 and 2 (b). According to these embodiments, not only the occurrence of solder bridges when the solder cream 3 is applied but also the inside of the solder cream during reflow can be prevented. Can be prevented from being pulled in.

【0027】以上の説明から明らかなように、図1の実
施例は端子2の幅Wとはんだクリーム3の幅Wとの
関係をW>W≧0.6Wに設定したことにより、は
んだクリーム3を塗布した際にはんだプリッジ4の発生
を防止することができるので、端子間隔の狭いプリント
基板等1に半導体装置11を実装する場合に実施して、
特に有効である。
As is apparent from the above description, the embodiment of Figure 1 by setting the relationship between the width W 1 of creams 3 and solder width W of the terminal 2 to W> W 1 ≧ 0.6 W, solder Since the generation of the solder bridge 4 when the cream 3 is applied can be prevented, the method is implemented when the semiconductor device 11 is mounted on a printed circuit board 1 having a narrow terminal interval.
Especially effective.

【0028】また、図2の実施例は、はんだクリーム3
の幅は端子2の幅とほぼ同じであるが、はんだクリーム
3の塗布量を内側は少なく外側は多くしたので、リフロ
ー時にはんだクリーム3が内側に引き込まれることがな
く、また外側端部には充分裾を引かせることができる。
したがって、端子間隔の比較的広い場合に実施して特に
有効である。
The embodiment of FIG.
Is almost the same as the width of the terminal 2. However, since the amount of the solder cream 3 applied is small on the inside and large on the outside, the solder cream 3 is not drawn into the inside at the time of reflow. The hem can be pulled sufficiently.
Therefore, the embodiment is particularly effective when the terminal interval is relatively wide.

【0029】さらに、図3の実施例は、端子2の幅Wと
はんだクリーム3の幅Wとの関係をW>W
0.6Wに設定すると共に、はんだクリーム3の塗布量
を内側は少なく、外側は多くしたので、はんだクリーム
3を塗布した際はんだブリッジの発生を防止するばかり
でなく、リフロー時にはんだクリーム3が内側に引き込
まれるのを防止し、外側端部には充分裾を引かせること
ができる。したがって、本実施例は、半導体装置を各種
の寸法、形状の端子を有するプリント基板等に実装する
場合に実施してきわめて有効である。
Furthermore, the embodiment of Figure 3, the relationship between the width W 1 of creams 3 and solder width W of the terminal 2 W> W 1
At the same time, the solder cream 3 was applied to the inside at a small amount and the outside was increased, so that the solder cream 3 was applied not only to prevent the occurrence of solder bridges but also to prevent the solder cream 3 from being applied at the time of reflow. Can be prevented from being pulled into the outer end, and the hem can be pulled sufficiently at the outer end. Therefore, the present embodiment is extremely effective when implemented when a semiconductor device is mounted on a printed circuit board or the like having terminals of various sizes and shapes.

【0030】[0030]

【発明の効果】以上の説明から明らかなように、本発明
は、はんだクリームの塗布量を内側は少なく外側は多く
したので、リフロー時にはんだクリームの引込みを生ず
ることもなく、はんだ付け状態の外観検査を容易にし、
はんだブリッジの除去も容易にする半導体装置の表面実
装構造を得ることができる。
As is clear from the above description, according to the present invention, since the amount of solder cream applied is small on the inside and large on the outside, the solder cream does not draw in during reflow, and the appearance of the soldered state does not occur. Make inspection easier,
A surface mounting structure of a semiconductor device that also facilitates removal of a solder bridge can be obtained.

【0031】このためはんだブリッジの除去のために多
くの時間をかける必要がなく、はんだクリームの付着状
態の検査も容易になる等、生産性の向上に大きく貢献す
ることができる。
Therefore, it is not necessary to take much time for removing the solder bridge, and the inspection of the adhesion state of the solder cream can be easily performed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(d)はいずれも本発明実施例の平面
図。
1A to 1D are plan views of an embodiment of the present invention.

【図2】(a)〜(d)はいずれも本発明実施例の平面
図。
FIGS. 2A to 2D are plan views of an embodiment of the present invention.

【図3】(a)、(b)はいずれも本発明実施例の平面
図。
FIGS. 3A and 3B are plan views of an embodiment of the present invention.

【図4】その作用説明図。FIG. 4 is an explanatory diagram of the operation.

【図5】本発明に係るはんだクリームの幅と端子の幅と
の関係と、付着強度との関係を示す線図。
FIG. 5 is a diagram showing the relationship between the width of the solder cream and the width of the terminal according to the present invention and the relationship between the width and the adhesion strength.

【図6】表面実装構造を説明するためのもので、(a)
は正面図、(b)は側面図、(C)は平面図。
FIG. 6 is a view for explaining a surface mounting structure, and FIG.
Is a front view, (b) is a side view, and (C) is a plan view.

【図7】端子とマスクとの関係を示す斜視図。FIG. 7 is a perspective view showing a relationship between a terminal and a mask.

【図8】はんだブリッジの発生状態を示す平面図。FIG. 8 is a plan view showing a state in which a solder bridge is generated.

【図9】従来のリフロー後の状態を示す側面図である。FIG. 9 is a side view showing a state after the conventional reflow.

【符号の説明】[Explanation of symbols]

1…プリント基板等 2…端子 3…はんだクリーム 4…はんだブリッジ 6…引込み 7…マスク 8…窓 11…半導体装置 12…リード DESCRIPTION OF SYMBOLS 1 ... Printed circuit board etc. 2 ... Terminal 3 ... Solder cream 4 ... Solder bridge 6 ... Retraction 7 ... Mask 8 ... Window 11 ... Semiconductor device 12 ... Lead

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板上に設けられた複数の端子の表面には
んだクリームを塗布した後、リフローすることにより前
記複数の端子と半導体装置の複数のリードとを接続する
半導体装置の実装方法において、 前記複数の端子それぞれに、前記はんだクリームの塗布
量が、前記リードの先端に近い側が前記半導体のパッケ
ージに近い側より多くなるように前記はんだクリームを
塗布することを特徴とする半導体装置の実装方法。
1. A method of mounting a semiconductor device, comprising: applying solder cream to a surface of a plurality of terminals provided on a substrate; and reflowing the solder cream to connect the plurality of terminals to a plurality of leads of the semiconductor device. A method of mounting a semiconductor device, comprising: applying the solder cream to each of the plurality of terminals such that an amount of application of the solder cream is larger on a side closer to a tip of the lead than on a side closer to a package of the semiconductor. .
【請求項2】基板上に設けられた複数の端子の表面には
んだクリームを塗布した後、リフローすることにより前
記複数の端子と半導体装置の複数のリードとを接続する
半導体装置の実装方法において、 前記複数の端子それぞれに、前記リードの先端に近い側
に塗布される前記はんだクリームの幅を、前記半導体の
パッケージに近い側に塗布される前記はんだクリームの
幅よりも広くなるように、前記はんだクリームを塗布す
ることを特徴とする半導体装置の実装方法。
2. A method of mounting a semiconductor device, comprising applying solder cream to surfaces of a plurality of terminals provided on a substrate and then reflowing the plurality of terminals and a plurality of leads of the semiconductor device. Each of the plurality of terminals, the width of the solder cream applied to the side near the tip of the lead, the width of the solder cream is wider than the width of the solder cream applied to the side near the semiconductor package, A method for mounting a semiconductor device, comprising applying a cream.
JP9144056A 1997-06-02 1997-06-02 Semiconductor device mounting method Expired - Lifetime JP2924856B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9144056A JP2924856B2 (en) 1997-06-02 1997-06-02 Semiconductor device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9144056A JP2924856B2 (en) 1997-06-02 1997-06-02 Semiconductor device mounting method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP63112615A Division JP2832716B2 (en) 1988-05-11 1988-05-11 Semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPH1070359A JPH1070359A (en) 1998-03-10
JP2924856B2 true JP2924856B2 (en) 1999-07-26

Family

ID=15353295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9144056A Expired - Lifetime JP2924856B2 (en) 1997-06-02 1997-06-02 Semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JP2924856B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4143280B2 (en) 2001-06-01 2008-09-03 日本電気株式会社 Mounting structure, method for manufacturing mounting structure, mask for printing, and printing method
US20030201303A1 (en) * 2002-04-24 2003-10-30 Jones Heidi N. Modified aperture for surface mount technology (SMT) screen printing

Also Published As

Publication number Publication date
JPH1070359A (en) 1998-03-10

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