JP2921135B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for plating a semiconductor package. In recent years, ASICs (Application Sp
ecific IC) is used for various purposes.

Here, since an ASIC requires many input / output terminals, a PGA (Pin Grid Array Package) suitable for increasing the number of pins is often used as a package form. By the way, CPGA (Ceramic Pin Grid Array Package), whose package substrate is made of porcelain (Ceramics), is currently used as a highly reliable package.On the other hand, research on organic insulating materials with improved heat resistance and moisture resistance has been conducted. Going forward, a glass-BT resin (a glass fiber woven into a cloth shape impregnated with a bismaleimide / triazine copolymer) or a plastic package using a glass-modified polyimide resin (PPGA, Plastic Pin Grid Array Package) )
Has been put to practical use and its reliability has been shown to be comparable to that of CPGA. There is a tendency to replace CPGA from the viewpoint of cost reduction.

[0003]

2. Description of the Related Art PGA, including CPGA and PPGA, has a concave portion for mounting a semiconductor chip in the upper center of a package substrate, and plating is applied to the chip mounting portion and lead pins constituting input / output terminals.

FIG. 2 is a sectional view showing the structure of the PPGA.
There is a concave portion in the upper center of the package substrate 1, a plating layer 2 is provided on the inner surface thereof, and a conductive paste (for example, silver paste)
, The semiconductor chip 3 is mounted.

[0005] A conductor pattern 4 is formed on the upper surface of the package substrate 1, and an end of the conductor pattern 4 serves as a bonding pad, which is wire-bonded to a pad provided around the semiconductor chip 3 by a bonding wire 5. ing.

The other end of the conductor pattern 4 is configured to be connected to a large number of lead pins 6 provided on the package substrate 1. That is, the package substrate 1 is provided with a large number of through holes for circuit connection with the conductor pattern 4 on the upper surface centering on the upper central concave portion, and the lead pins 6 are inserted and fixed in these through holes.

A metal cap 7 is fitted over the package substrate 1 to protect the semiconductor chip 3. Next, FIG. 1 is a cross-sectional view showing the structure of the CPGA, in which a recess is formed in the upper center of a package substrate 11, a plating layer 12 is provided on the inner surface, and a semiconductor chip 13 is mounted with a conductive paste (for example, silver paste). Have been.

Further, bonding pads are formed on the upper surface of the package substrate 11 so that the bonding wires 15 are formed.
The wire bonding is performed with pads provided around the semiconductor chip 13.

Further, the bonding pads are configured to be connected to the lead pins 16 which are provided by being brazed to the package substrate 11 through inner layer metallization and vias.

Further, a metal cap 17 is sealed above the package substrate 11 by a seam welding method or the like to protect the semiconductor chip 13. Take this structure
In the CPAG package, the plating layer 12 formed in the central concave portion of the package substrate 11 and the plating performed on the surface of the lead pins 16 are basically plated with two layers of nickel (Ni) and gold (Au). Is a watt bath for Ni plating,
For Au plating, soft Au plating (for example, Templex 402) was used.

Here, as a method of mounting the PGA package on the printed wiring board, the PGA package is inserted into a through-hole provided in the printed wiring board and then welded by a method such as flow soldering. It is detachably mounted on a socket provided on the printed wiring board. There are two cases.

Here, Kovar made of iron-nickel-cobalt (Fe-Ni-Co) alloy is often used for the lead pin. Solder immersion is performed, and in this state, supplied to the user and inserted.

[0013] In addition, since the terminal insertion portion of the socket made of phosphor bronze or the like is subjected to two-layer plating of Ni and Au for the use of, the fine sliding corrosion with the socket following the Ni plating is prevented. In order to prevent this, Au plating is performed and supplied to the user in this state.

However, the Ni plating and the Au plating performed in this manner are not necessarily suitable for lead pins since the main purpose is to form a plating layer on a package substrate on which a semiconductor chip is mounted, and therefore, after aging, There were problems such as cracks occurring in the bending test to be performed and a high degree of wear when inserting and removing from the socket.

[0015]

In the conventional CPGA plating process, plating on a package substrate and plating on lead pins are performed in the same process, and plating is performed with focus on plating on the package substrate.

[0016] For this reason, there have been problems such as cracks occurring in the lead pins in a bending test performed after aging and a high degree of wear upon insertion and removal from the socket.

[0017]

SUMMARY OF THE INVENTION An object of the present invention is to provide a package substrate formed of plastic, a chip mounting region on the package substrate, a first plating layer provided on a conductor pattern, and a chip mounting region. A semiconductor chip mounted and connected to one end of the conductor pattern ,
More provided on the package substrate, the lead pins which are connected to the other end of the conductor pattern, and a second plating layer provided on the lead pin, the second plating layer small
At least the surface layer is harder than the first plating layer.
Wherein a that, and a step of forming a predetermined conductor pattern on a package substrate made of plastic, chip mounting regions for the said package substrate, and a first plating layer on the conductor pattern on the forming a semiconductor chip mounted on the chip mounting region where the first plating layer is provided, the semiconductor chip and the second
A step 1 of the plating layer is connected to one end of the conductor pattern provided, the lead pins, by a separate process from the first plating layer forming step, the rigid than the first plating layer
Forming a second plating layer;
Press-fitting the lead pin and the first
To the other end of the conductor pattern provided with the plating layer of
It is solved by the method for manufacturing a semiconductor device according to claim to have a the step of.

[0018]

According to the present invention, the plating performed on the package substrate and the plating performed on the lead pins are performed using separate plating baths.
Each performs optimal plating.

That is, the manufacturing process of the CPGA requires the lead pin to be soldered to the via portion provided on the ceramic substrate using silver brazing or the like, so that a high temperature treatment of about 800 ° C. is required. Therefore, the plating performed on the package substrate and the plating performed on the lead pins have been performed in the same step under the conditions suitable for the former.

However, in the PPGA, the mounting of the lead pins can be performed by a press-fitting method (press-fitting), and the quality does not deteriorate due to the high temperature treatment. This is to solve the conventional problem by performing it separately.

That is, conventionally, a watt bath having the following bath composition is used for Ni plating as a plating bath for a package substrate and a lead pin in the CPGA, and a Vickers hardness of 140 to 160 and a residual stress of about 1260 kg / cm ² . Ni film 2
It was formed to a thickness of ８8 μm.

Watt bath composition: nickel sulfate 330 g / l nickel chloride 45 硼 boric acid 38 〃 Also, for Au plating, a so-called “soft gold plating” such as trade name Temperex 402 (Nippon Electroplating Engineers) was used. Vickers hardness is 50 ~ 80
Was formed to a thickness of 1.5 to 4.0 μm.

For this reason, there is no problem in terms of chip attaching property and wire bonding property. However, since the residual stress of Ni plating is large, plating cracks are easily generated in a bending test after aging, and the hardness of Au plating is small. For this reason, there is a problem that the wear is extremely large when inserting and removing the socket.

Therefore, according to the present invention, the plating of the PPGA package substrate is performed by forming a Cu plating to a thickness of 10 to 20 μm and then using a conventional Ni or Au plating bath. As for the sulfur plating bath, a bath having a small residual stress of about 35 kg / cm ² and a Vickers hardness of 250 to 350 as large as that of a sulfamic acid bath is used, and the Au plating bath is made of Au-Co or Au-Ni. By using an Au alloy plating bath commonly called "hard gold plating" like a system, an Au film having high hardness is obtained.

Sulfamic acid bath: Nickel sulfamate 450 g / l Boric acid 30 〃 Hard gold plating bath: Au-Co based solution (Autronex C) Vickers hardness 200 to 240 Au-Ni based solution (Autronex N) Vickers hardness 160 to 200 Au-Ni-based liquid (Autronex NW) 390-430 (all manufactured by Nippon Electroplating Engineers) In addition, Au plating has a thickness of PPGA in the chip attaching stage of the package substrate and the wire bonding pad forming part. If the thickness is not at least 1.0 μm, the bonding property is degraded, but the lead pin only needs to obtain an ohmic contact, and does not need such a large thickness.

The present invention solves the conventional problems by separately plating the package substrate and the lead pins. In addition, if palladium (Pd) plating is performed as a base plating for Au plating, it is possible to further reduce the thickness of the Au plating.

[0027]

EXAMPLE 1 After a Cu plating was formed to a thickness of 15 μm as a plating of a PPGA package substrate, a Ni plating was formed to a thickness of 7.5 μm using a Watt bath, and an Au plating was formed to a thickness of 1.5 μm using a Temperex 402.
It was formed to a thickness of μm.

On the other hand, as a lead pin, Kovar having a diameter of 0.46 mm was plated with Ni to a thickness of 3 μm using a sulfamic acid bath, and then Auroneck C was used as an Au plating bath, and Au-Co-based hard gold was plated with 0.5%. One having a thickness of μm was used.

The package formed in this manner did not suffer from abrasion as in the prior art even after repeated insertion and extraction, and no cracks were observed even in a bending test. Example 2 A Cu plating was formed to a thickness of 15 μm as a plating of a PPGA package substrate, a Ni plating was formed to a thickness of 7.5 μm using a Watt bath, and an Au plating was formed to a thickness of 1.5 μm using a Temperex 402.
It was formed to a thickness of μm.

On the other hand, as a lead pin, Kovar having a diameter of 0.46 mm was plated with Ni to a thickness of 3 μm using a sulfamic acid bath, and then Pd plating was performed to a thickness of 0.5 μm, followed by Au plating.
The plating bath used was Autolonex NW, and Au-Ni-based hard gold was formed to a thickness of 0.2 μm.

The package formed in this manner did not suffer from the conventional abrasion even after repeated insertion and extraction, and no crack was observed even when subjected to a bending test.

[0032]

As described above, the practice of the present invention eliminates the occurrence of cracks in the lead pins, reduces the wear of Au when inserting and removing the socket repeatedly, and the case where the lead pins are directly inserted into the printed wiring board. However, solderability can be improved, and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a CPGA.

FIG. 2 is a cross-sectional view illustrating a configuration of a PPGA.

[Explanation of symbols]

 1,11 Package substrate 2,12 Plating layer 3,13 Semiconductor chip 5,15 Bonding wire 6,16 Lead pin 7,17 Cap

Claims (4)

(57) [Claims] 1. A package substrate formed of plastic, a first plating layer provided on a chip mounting region and a conductor pattern on the package substrate, and connected to one end of the conductor pattern mounted on the chip mounting region. A semiconductor chip, a lead pin provided on the package substrate by a press-fitting method and connected to the other end of the conductive pattern, and a second plating layer provided on the lead pin. A semiconductor device, wherein at least a surface layer of a plating layer is plated harder than the first plating layer. 2. The method according to claim 1, wherein the first plating layer is formed by three-layer plating in which copper, nickel and gold are applied in this order, and the second plating layer is formed by applying nickel and gold in this order.
It consists of two-layer plating , and the three-layer plating gold plating
Formed in a soft gold plating bath, the two-layer plating gold plating
There semiconductor device according to claim 1, wherein the der Rukoto those formed by the hard gold plating bath. Wherein said first plating layer is copper, is composed of three layers plating deposited nickel and gold in this order, the second plating layer is composed of gold plating, the three-layer menu
The gold plating of the stick is formed in a soft gold plating bath,
Gold plating of the plating layer is formed in the hard gold plating bath
The semiconductor device according to claim 1, wherein Monodea Rukoto. 4. A step of forming a predetermined conductor pattern on a package substrate formed of plastic; a step of forming a first plating layer on an area where the package substrate is to be mounted with a chip; and a step of forming a first plating layer on the conductor pattern. In the chip mounting area where the first plating layer is provided ,
A semiconductor chip is mounted, and the semiconductor chip and the first message are mounted .
A step of connecting one end of the conductor pattern provided with a lead layer, and a step different from the step of forming the first plating layer on the lead pin.
The second plating layer harder than the first message key layer
Forming a, and characterized in that organic and the step of connecting the steps of press-fitting the lead pin to the package substrate, and the other end of the conductor pattern in which the lead pin and the first plating layer is provided Semiconductor device manufacturing method.