JP2920642B2 - Driving method of liquid crystal display element - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a dot matrix type liquid crystal display element, and more particularly, to a driving method of a vertical n-times double display.

[Conventional technology]

A typical liquid crystal display element 30 has transparent electrodes 32a (signal-side electrodes) and 32b (scanning-side electrodes) and alignment films 33a and 33b deposited as shown in FIGS. A liquid crystal material 34 is sandwiched between the two transparent substrates 31a and 31b, and polarizing plates 35a and 35b are arranged on the outer surfaces of the two transparent substrates 31a and 31b, respectively.

The liquid crystal display element 30 configured as described above includes a transparent electrode 32
By applying a predetermined electric field to the liquid crystal material 34 through the a and 32b, the arrangement of the initial liquid crystal molecules defined by the alignment films 33a and 33b such as a polyimide resin changes, and passes or blocks only a predetermined light beam, A predetermined display was achieved.

In the displayable region D, a transparent electrode 32a in one direction (X direction) formed on the transparent substrate 31a and a transparent electrode 32b in another direction (Y direction) formed on the transparent substrate 31b intersect (dot). ), And a dot matte-rick display was formed. As the display drive control, when the capacity of the dot matrix increases, multiplex drive is generally widely used.

In the multiplex driving, potentials to be applied to, for example, 640 signal-side electrodes 32a and, for example, 200 scanning-side electrodes 32b are accurately controlled using the driving ICs 36a and 36b. The signal-side drive IC 36a for the signal-side electrode 32a and the scan-side drive IC 36b for the scan-side electrode 32b are easy to form wiring,
To improve IC mounting workability, ease of input of driving voltage and data signal to IC, and increase the mounting density of the board, it is placed on one of the boards, for example, 31a (the board on which the signal side electrode 32a is formed) Have been.

The signal-side driving IC 36a includes a shift register, a driver, a voltage controller, and the like. Input signals include a clock pulse (CP), a data signal, a DF signal, and the like.
The load signal includes a display signal as an output signal, and a voltage system includes a plurality of types of drive voltages, IC drive voltages, and grounds.

The total number of shift registers of the plurality of signal-side driving ICs 36a corresponds to the number of the signal-side electrodes 32a, and data signals of 1 to 4 bits are serially input corresponding to clock pulses (CP). It is stored in a shift register. For example, with a 2 MHz CP, a 4-bit parallel data display signal is stored in a shift register with 160 CPs. When the display data is stored in all the shift registers, the LOAD signal is input, and the predetermined signal side electrode 32a among 1 to 640 is activated.
At this time, one of a plurality of types of drive voltages is selected by a voltage controller controlled by the DF signal, and the selected drive voltage is applied to the signal side electrode 32a for a predetermined period.

Scan-side drive IC 36b is a shift register, driver,
There are a voltage controller and the like. Input signals include a DF signal and a LOAD signal, and voltage systems include a plurality of types of drive voltages, IC drive voltages, and grounds. And LO
When the AD signal is input, the scanning electrodes 32b are sequentially scanned one by one. At this time, one of a plurality of types of driving voltages is selected by a voltage controller controlled by the DF signal, and the selected driving voltage is applied for a predetermined period of the scanning-side electrode 32b.

By inputting 200 LOAD signals, one screen (1
An image of a frame is formed, and this one screen is sequentially displayed at a period of 70 to 80 Hz.

Then, a predetermined voltage is applied to the liquid crystal material 34 by the sum (or difference) of the drive voltage determined by the signal side drive IC 36a and the drive voltage determined by the scan side drive IC 36b.

In the above-described driving method of the liquid crystal display element, for example,
When displaying in double-height mode (n = 2 in vertical-height mode), registering of the data display signal in the signal-side driving IC 36a is normally performed, and if the LOAD signal is different between the scanning-side driving IC 36b and the signal-side driving IC 36a. Let That is, the scanning-side driving IC 36b
The LOAD signal is doubled in frequency from the signal side driving IC 36a, and the two scanning side electrodes 42b are scanned with the data for one row, and the first line and the second line are converted to the data for the next row. Displayed the third and fourth lines.

[Problems of the prior art]

However, doubling the frequency of the LOAD signal only on the scanning side driving IC 46b side is equivalent to the LOAD of the signal side driving IC 36a.
Signal and the same LOAD of the scanning side driving IC 36b as the LOAD signal.
A signal and a LOAD signal for double-height display are required.These signals must be separated into the LOAD signal of the signal-side driving IC and the LOAD signal of the scanning-side driving IC, so that the LOAD signal can be used in common. Did not.

(Object of the present invention)

The present invention has been devised in view of the above-described problems, and has as its object the purpose of using a common LOAD signal without providing a special input terminal to which a LOAD signal for vertical n-fold display is input, Another object of the present invention is to provide a driving method of a liquid crystal display element that achieves a display with n times the size of a vertical axis.

[Specific means for solving the problem]

According to the present invention, in order to solve the above-described problems, a plurality of signal-side electrodes connected to the display data storage register,
In a driving method of a liquid crystal display element in which a liquid crystal layer is sandwiched between a plurality of scanning electrodes sequentially scanned by a load signal, display data corresponding to all signal electrodes is conveyed to the register in synchronization with a clock pulse signal. In the meantime, a driving method of a liquid crystal display element in which a load signal with a small duty ratio of the clock pulse is generated and the scanning electrode is activated is proposed.

〔Example〕

Hereinafter, a driving method of the liquid crystal display device of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram for explaining a driving method of a liquid crystal display element according to the present invention. FIG. 2 (a) is a pulse diagram showing a main signal generation state in the block circuit diagram of FIG. FIG. 2B is a pulse diagram showing the duty ratio of the pulse between the clock pulse signal and the first LOAD signal. The structure of the liquid crystal display device is shown in FIG.
Since (b) is indicated by, the detailed description is omitted.

The signal side driving IC 36a includes an output stage 21 and a shift register 22 connected one by one to the signal side electrode 32a, and further,
It comprises a voltage controller 23 and the like. A plurality of signal-side driving ICs 36a are used to supply signals to all the signal-side electrodes 32a.

The signal side driving IC 36a has a display data input terminal D for storing data to be displayed in the shift register 22.
i, an output terminal Do for sequentially sending display data to the shift register of the next driving IC 36a, a clock pulse terminal Cp for controlling the timing of the display data, and latching data to be displayed on the output stage 23 from the shift register 22. A load signal terminal L for controlling, a DF (alternating) signal terminal DF for controlling an applied voltage output from the output stage 21, voltage terminals V0 to V3 to which plural kinds of applied voltages are supplied, IC driving A voltage terminal VD and a ground terminal G are provided.
The scanning-side driving IC 36b includes an output stage 24 and a register 25 connected one by one to the scanning-side electrode 32b, and further includes a voltage controller 26 and the like. One or two signal-side driving ICs 36b are used to supply signals to all the scanning-side electrodes 32b.

A load (LOA) for latching and controlling the next scanning electrode 32b to be scanned from the output stage 24 is provided in the scanning driver IC 36b.
D) a signal terminal L, a DF (alternating current) signal terminal DF for controlling an applied voltage output from the output stage 24, voltage terminals V4 to V7 to which a plurality of types of applied voltages are supplied, an IC driving voltage terminal VD, and ground. A terminal G and the like are provided.

Then, the signal side driving IC 36a and the scanning side driving I
The C36b is connected to an external controller IC, a clock generator, and a display RAM (not shown).

In the full-width display, as shown in FIG. 2A, the display data D for one row (for one scanning electrode 32b) is supplied to the shift register 22 of the plurality of signal-side driving ICs 36a by a 2 MHz clock pulse (CP). Are input serially as 4-bit parallel data and stored in all the shift registers 22 (period a). When storage of the display data to all the shift register 22 is completed, after the display data reading stop period corresponding to several clock pulses (period b), LOAD signal L ₀ is input, the display housed in all the shift registers 22 Data D
Are latched in the output stage 21. The output stage 21 selects one of a plurality of types of drive voltages by a voltage controller 23 controlled by the DF signal, and outputs the drive voltage to the signal electrode 32a for a predetermined period.

On the other hand, the scanning electrode 32b is the input of the LOAD signal L ₀ inputted to the scanning side driving IC36b (in synchronization with the latch in the output stage 24 from the shift register 25 by signal side driving IC36a), scanning to The next scan electrode 32b to be activated is activated. At this time, one of a plurality of types of drive voltages is selected by the voltage controller 26 controlled by the DF signal, and the drive voltage is output to the scan-side electrode 32b for a predetermined period.

Then, LOAD signal L ₀ is the number of scans one screen (e.g. 200
Times), one screen (one frame)
Are formed, and this one screen is sequentially displayed at 70 to 80 Hz.

Due to the potential difference between the signal side electrode 32a and the scanning side electrode 32b (one of the combinations is determined by the DF signal), a predetermined electric field is applied to the liquid crystal to enable display.

 Next, the double height display in the present invention will be described.

According to the present invention, while the display data D for one row is being output from the output stage 21, the data D of the shift register 22 is not latch-controlled, and a LOAD signal (second LOAD) that only scans the scanning electrode 32b sequentially is used. signal) L ₂ is input to a normal LOAD signal (first LOAD signal) terminal L of the double-byte display. This allows
One row of display data D output from the output stage 21 is applied with a predetermined potential to the liquid crystal 34 at intersections with the scanning electrodes 32b of a plurality of rows, thereby enabling display. In order to latch and control the data in the shift register 22, a normal LOAD signal (first
LOAD signal L ₁ ). As a result, the data of the shift register 22 is latched, and the next scanning electrode 32b is sequentially scanned.

That is, in order to perform the double height display, one line (one scanning electrode 32
Display data of b min), applied to the second LOAD signal L ₂ for signal side driving IC36a and the scanning side drive IC36b until being housed in the entire shift register 22 of the signal side driving IC36a, further line after the partial display data is stored in all the shift register, it may be given a first LOAD signal L ₁ to the signal side driving IC36a and the scanning side driving IC36b.

The second LOAD input of the signal L _2, IC36a signal side driving
The data stored in the shift register does not perform the latch operation, and the scanning is sequentially performed only by the scanning-side driving IC 36b.

To achieve the above-described operation, as shown in FIG. 2 (c), the second LOAD signal L ₂ is that the pulse width T is short shopping than the pulse width CPT clock pulse is important. Thus, the second LOAD signal L ₂ is housed in the shift register of IC36a for even signal side driving is input data is the never operate the latch. Note that the pulse width of the scan-side drive IC 36b must be 50 nsec or more to be able to be the LOAD signals L ₁ and L ₂ . Therefore, the second LOAD signal L ₂ be the pulse width T is equal to or greater than 50 nsec.

The second LOAD signal L ₂ generates intermediate the first LOAD signal L ₁ and the first LOAD signal L ₁ below. For example, as described above, 4 if the bit by bit transfer is the display data is stored in 640 of the shift register as the display data for one line in the 160 clock pulses, the second LOAD signal L ₂
Generate it with the 81st clock pulse.

Accordingly, by approximating the effective voltage value of the second line of the display that is scanned by the first LOAD signal L ₁ of the first line scanned by the display and the second LOAD signal L _2, the display grayscale It is possible to display a double double-width character with no difference.

Generally, display data is transferred to a shift register at the falling edge of a clock pulse. Therefore, the second LO
AD signal L ₂ generates when the clock pulse is High, (H state). Thus, there is no adverse effect such as lack of display data transferred to the shift register.

As described above, the first LOAD signal is input from the LOAD signal input terminal L.
Display data is stored in the shift register 22 between the signal L ₁ and the next first LOAD signal L _1, and one or more _second LOAD signals L ₂ for scanning only the scanning electrode 32 b are stored during this time. by generating the vertical n combination angle display plus 1 in the generation number n-1 of the second LOAD signal L ₂ is readily achieved. Further, since the first and second LOAD signals L ₁ and L ₂ can be inputted to the same LOAD signal input terminal L, the vertical n-fold angle can be easily obtained by using the conventional signal side driving IC 36a and the scanning side driving IC 36b. Display becomes possible.

FIG. 2 (d) shows a LOAD signal generation circuit for performing the driving method of the present invention using the conventional signal side driving IC 36a and scanning side driving IC 36b as they are.

That is, the counter 27 counts, for example, the 81st clock pulse CP. In addition, a signal having a width smaller than the duty ratio of the clock pulse CP is generated in the oscillation section 28.

When the counter 27 has counted the 81st clock pulse CP, it outputs the _second LOAD signal L2. This allows LOAD
By interposing the signal generating circuit between the conventional display controller and the LOAD signal input terminal L, it is possible to display a double-width image.

In the above-described embodiment, the transmission type liquid crystal display device having the backlight 37 has been described. However, the reflection type liquid crystal display device can be used widely, such as a stacked type liquid crystal display device in which a plurality of liquid crystal layers are stacked.

[Effects of the present invention] As described above, according to the driving method of the liquid crystal display element of the present invention, the plurality of signal electrodes connected to the display data storage register and the plurality of scans sequentially scanned by the load signal are provided. In the driving method of the liquid crystal display element sandwiching the liquid crystal layer with the side electrodes, the duty of the clock pulse is kept until the display data corresponding to all the signal side electrodes is carried in synchronization with the clock pulse signal in the register. Since a load signal with a small ratio was generated and the scanning electrode was activated, the LOAD signal of the conventional signal-side driving IC and scanning-side driving IC was eliminated without providing a special LOAD signal input terminal for vertical n-fold display. By using the input terminal as it is, it is possible to easily achieve the display of n times the vertical size.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram for explaining a driving method of a liquid crystal display element of the present invention. 2 (a) and 2 (b) are signal pulse generation diagrams for explaining the operation of the liquid crystal display element driving method of the present invention, and FIG. 2 (c) is for explaining the second LOAD signal. FIG. 2 (d) is a circuit diagram for generating a second LOAD signal. FIG. 3 (a) is a plan view showing the structure of a typical liquid crystal display element, and FIG. 3 (b) is a sectional view taken along line XX of FIG. 3 (a). 31a, 31b: transparent substrate 32a: signal side electrode 32b: scanning side electrode 34: liquid crystal layer 36a: signal side driving IC 36b: scanning side driving IC

Claims (1)

(57) [Claims] A plurality of signal electrodes connected to a signal driving IC comprising a display data storage shift register and an output stage for transferring display data in synchronization with a clock pulse signal; A liquid crystal display element comprising a plurality of scanning electrodes connected to a scan driving IC comprising a shift register and an output stage, and wherein each data stored in both shift registers is latched at an output stage by a load signal. A common load signal is input to the signal driving IC and the scanning driving IC, and the load signal is input during a period in which the input of the clock pulse signal is stopped, and the signal side electrode and the scanning side are input. It comprises a first load signal for activating the electrodes, and (n-1) second load signals that are input during the display data transfer period and activate only the scanning electrodes. Second load signal driving mode of the liquid crystal display device for use in a vertical n combination angle display, which is a signal of a small consisting pulse width than the pulse width of the clock pulse signal.