JPH0335291A - Driving system for liquid crystal display element - Google Patents

Abstract

PURPOSE:To commonly use LOAD signals and to attain vertical n-times height size display by generating plural pieces of the LOAD signals which are small in the duty ratio of clock pulses before the display data corresponding to all signal side electrodes is carried to registers and starting only the scanning side electrodes. CONSTITUTION:The LOAD signals which are small in the duty ratio of the clock pulses CP are generated before the display data D corresponding to all the signal side electrodes is carried to the registers 22 to start the scanning side electrodes. The 2nd LOAD signal L2 is generated between the 1st LOAD signal L1 and the next 1st LOAD signal L1 before the display data for one line is housed in all the shift registers 22 of an IC 36a for driving the signal side in order to make the double height size display. The scanning side electrodes are subjected to the intermediate starting by generating the LOAD signals of the small duty ratio in such a manner. The n-times height size display is thus executed by utilizing the LOAD signal input terminals for the IC for driving the signal side and the IC for driving the scanning side as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a driving method for a dot matrix type liquid crystal display element, and more particularly to a driving method for an n-fold vertical display.

[Conventional technology]

As shown in FIGS. 3(a) and 3(b), a typical liquid crystal display element 30 consists of two transparent electrodes 32a (signal side electrode L32b (scanning side electrode) and alignment films 33a, 33b). A liquid crystal material 34 is sandwiched between transparent substrates 31a and 31b, and polarizing plates 35a and 35b are arranged on the outer surfaces of the two transparent substrates 31a and 31b, respectively.

The liquid crystal display element 30 configured in this way has transparent electrodes 3
By applying a predetermined electric field to the liquid crystal material 34 through 2a and 32b, an alignment film 33a made of polyimide resin or the like is formed.
, 33b, the initial alignment of liquid crystal molecules changed, allowing only certain light rays to pass through or being blocked, thereby providing a distant relative to a certain display.

In the displayable area, a transparent electrode 32a formed on the transparent substrate 31a in one direction (X direction) and a transparent electrode 32b formed on the transparent substrate 31b in the other direction (Y direction) intersect (dot). ), he used a dot muff trick display. As the capacity of dot matrix has increased, multiplex drive has generally been widely used for display drive control.

Multiplex driving uses the driving ICs 36a and 36b to accurately control the potentials to be applied to, for example, 640 signal-side electrodes 32a and, for example, 200 scanning-side electrodes 32b. Note that the signal side driving IC 36a of the signal side electrode 32a and the scanning side driving IC 36b of the scanning side electrode 32b are designed for ease of wiring formation, ease of IC mounting work,
In order to improve the ease of inputting drive voltages and data signals to the IC and the mounting density of the board, they are placed on one of the boards, for example 31a (the board on which the signal side electrode 32a is formed).

This signal side driving IC 36a is equipped with a shift register, a driver, a voltage controller, etc., and input signals include a clock pulse (CP), a data signal, and a DF.
There is a double signal LOAD signal, a display signal as an output signal, and multiple types of drive voltages as a voltage system, IC! S.I.
There are dynamic voltages, grounding, etc.

The total number of shift registers of the plurality of signal-side driving ICs 36a is equal to the number corresponding to the signal-side electrodes 32a, and 1 to 4-bit data signals are input serially in response to clock pulses (CP), and all shift registers are stored in a shift register. For example, a 4-bit parallel data display signal is stored in a shift register using 2MH2 CPs and 160 CPs.

When display data is stored in all shift registers, LOA
The D signal is input, and the predetermined signal side electrode 3 among l~640
2a is activated. At this time, one of the plurality of types of drive voltages is selected by a voltage controller controlled by the DF multiplied signal, and the selected drive voltage is applied to the signal side electrode 32a for a predetermined period.

The scanning side driving IC 36b includes a shift register, a driver, a voltage controller, etc., the input signal is a DF multiplied signal LOAD signal, and the voltage system includes multiple types of drive voltages, IC drive voltage, ground, etc.

When the LOAD signal is input, the scanning electrode 32b
are sequentially scanned book by book. At this time, one of the plurality of drive voltages is selected by a voltage controller controlled by the DF multiplication signal, and the scanning side electrode 3
2b A selected drive voltage is applied for a predetermined period.

One screen (l frame) of image is constructed by inputting 200 LOAD signals, and this one screen consists of 70~
It is displayed sequentially at a cycle of 80Hz.

Then, a predetermined voltage is applied to the liquid crystal material 34 based on the sum (or difference) of the drive voltage determined by the signal side drive IC 36a and the drive voltage determined by the scan side drive IC 36b.

In the above-mentioned driving method of the liquid crystal display element, for example, when performing a double-height display (n-times vertical display: n = 2), the signal side drive IC 46a normally takes in the data display signal into a register, and the LOAD signal is sent to the scanning side. Drive IC46
b and C46a for signal side drive. That is, the LOAD signal of the scanning flight driving IC 46b is transferred to the signal side driving IC 46b.
By doubling the frequency of C46a and scanning the two scanning side electrodes 42b with the data for the - line, the data for the next line is used to scan the 3rd and 4th lines.
It was showing the line.

[Problems with conventional technology]

However, the scanning side drive ICA6b (L only 11)
Doubling the frequency of the OAD signal means that the I
A LOAD signal of the C46a, a LOAD signal of the scanning side driving IC 46b which is the same as the LOAD signal, and a LOAD signal for double height display are required, and the LOAD signal of the signal side driving IC and the scanning side driving IC are required. The LOAD signal had to be separated from the LOAD signal, and the LOAD signal could not be used in common.

[Object of the present invention]

The present invention was devised in view of the above problems, and
The purpose is to provide a driving method for a liquid crystal display element that uses the LOAD signal in common without providing a special input terminal for manually inputting the LOAD signal for n-fold vertical display, and which is a distant relative of n-fold vertical display. It is something.

[Specific Means for Solving Problem C] According to the present invention, in order to solve the above-mentioned problem, a plurality of signal-side electrodes connected to a display data storage register and a plurality of signal-side electrodes that are sequentially scanned by a load signal are provided. In a driving method for a liquid crystal display element in which a liquid crystal layer is sandwiched between a plurality of scanning side electrodes, until display data corresponding to all signal side electrodes is transferred to the register in synchronization with a clock pulse signal, This paper proposes a driving method for a liquid crystal display element in which a load signal with a small duty ratio of a clock pulse is generated to activate a scanning side electrode.

〔Example〕

Hereinafter, the driving method of the liquid crystal display device of the present invention will be explained based on the drawings.

FIG. 1 is a block circuit diagram for explaining the driving method of the liquid crystal display element of the present invention, and FIG. FIG. 2(b) shows the clock pulse signal and the first
FIG. 3 is a pulse diagram showing the duty ratio of the pulse with the LOAD signal of FIG.

The structure of the liquid crystal display element is shown in FIGS. 3(a) and 3(b), so detailed explanation will be omitted.

The signal side drive IC 36a includes an output stage 21 and a shift register 22 connected to each of the signal side electrodes 32a, and further includes a voltage controller 23 and the like. A plurality of signal side drive ICs 36a are used to provide signals to all the signal side electrodes 32a.

The signal side drive IC 36a includes the shift register 22.
A display data input terminal Di for storing data to be displayed on the drive IC 36a, an output terminal Do for sequentially sending the display data to the shift register of the next driving IC 36a, and a clock pulse terminal C for controlling the timing of the display data.
p, LOAD signal terminal L for latching data to be displayed from the shift register 22 to the output stage 23, and ti4fI for the applied voltage output from the output stage 21.
A DF (alternating current) signal terminal DF, voltage terminals VO to V3 to which a plurality of types of applied voltages are supplied, an IC driving voltage terminal VD, a ground terminal G, and the like are provided. The scanning side driving IC 36b includes an output stage 24 and a register 25 connected to each scanning side electrode 32b', and further includes a voltage controller 26 and the like. One or two signal side drive ICs 36b are used to apply signals to all scanning side electrodes 32b.

The scan side drive IC 36b has a DF (AC converter) that controls the applied voltage output from the output stage 24 to a load (LOAD) signal terminal L1 for latching 1411 the next scan side electrode 32b to be scanned from the output stage 24. ) Signal terminal DF, voltage terminals v4 to V7, I to which multiple types of applied voltages are supplied
A C drive voltage terminal VD, a ground terminal G, and the like are provided.

The signal side driving IC 36a and scanning side driving IC 36b described above are connected to an external controller (2) C1 clock generator and display RAM (not shown).

In the full-width display, as shown in FIG. 2(a), the display delta D (-scanning electrode 32b) is 2MHz
The data is input serially as 4-bit parallel data in response to the clock pulse (CP), and is stored in all shift registers 22 (period a). All shift registers 22
When storage of display data is completed, after a display data reading stop period (period b) corresponding to several clock pulses, a LOAD signal L0 is input, and all shift registers 22
The display data D stored in is latched at the output stage 21. The output stage 21 selects one of a plurality of types of drive voltages by a voltage controller 23 controlled by the DF multiplied signal, and outputs the drive voltage to the signal side electrode 32a for a predetermined period.

On the other hand, the scanning side electrode 32b is connected to the input of the LOAD signal input to the scanning side driving IC 36b (signal side driving IC
36a from the shift register 25 to the output stage 24), the next scan electrode 32 to be scanned is
b is activated. At this time, one of the plurality of drive voltages is selected by the voltage controller 26 which is tilted by the DF multiplied signal, and the drive voltage is applied to the scanning electrode 32b for a predetermined period.

Then, send a LOAD signal. By inputting the number of scans for one screen (for example, 200 times), one screen (i-frame) image is formed, and this one screen has a frequency of 70 to 80 Hz.
are displayed sequentially.

The potential difference (
, one of the combinations is determined from the DF multiplied signals. ), a predetermined electric field is applied to the liquid insect to enable display.

Next, the double height display according to the present invention will be explained.

In the present invention, while the display data D for one line is being output from the output stage 21, the data D in the shift register 22 is not latched, but the LOAD signal (second The L OAD double signal Lz is input to the normal LOAD signal (first LOAD signal) terminal in full-width display.As a result, one line of display data D outputted from the output stage 21 is converted into multiple lines of display data D. scanning m electrode 3
A predetermined potential is applied to the liquid crystal 34 at the intersection with 2b, enabling display. Note that in order to latch control the data in the shift register 22, the normal LOAD signal (first LOA
This is done by the D signal. As a result, the data in the shift register 22 is latched, and the next scan (
11 electrodes 32b are sequentially scanned.

That is, in order to perform double-height display, - rows (- scanning electrodes 32
b) until the display data of the second L O
The AD signal L2 is applied to the signal side driving IC 36a and the scanning side driving IC 36b, and after the display data for - rows is stored in all the shift registers, the first L OA D
It is sufficient to apply the signal L to the signal gg driving IC 36a and the scanning side driving IC 36b.

By inputting the second LOAD signal Lt, the signal side drive I
The data stored in the shift register of C36a is not latched, and sequential scanning is performed only by the scanning side driving IC 36b.

To distantly relate the above operation, as shown in FIG. 2(c), the second LOAD signal I7□ has its pulse 11i
It is important that the pulse width CPT is shorter than the pulse width CPT of the T pulse. This allows the second LOAD
Even if the signal L2 is input, the data stored in the shift register of the signal side driving IC 36a will not be latched.

In addition, the LOAD signal J for the scanning scratch drive IC: 36b
, Lx, the pulse width must be 50nse.
E or more is required. Therefore, the second LOAD signal also has a pulse width T of 50 nsec or more.

Further, the second LOAD signal L2 is generated between the first LOAD signal Lx and the next first LOADfs number Li. For example, as described above, when the display data transferred 4 bits at a time is stored in 640 shift registers as one line of display data using 160 clock pulses, the second LOAD signal L2 is transferred to the 81st clock pulse. Make it generate in pulses.

As a result, by approximating the effective voltage values of the l-th line scanned by the first LOAD signal L2 and the second line scanned by the second LOAD signal L2, the display Double-height display with no difference in shading is possible.

Generally, display data is transferred to a shift register at the falling edge of a clock pulse. For this reason, the second LO
The AD signal R is generated when the clock pulse is High (H state). This prevents any negative effects such as loss of display data transferred to the shift register.

As described above, from the LOAD signal input terminal, the first L
The display data is stored in the shift register 22 between the OAD signal L1 and the next first (7) LOA [[9 shame], and during this period, the second LO input signal L that scans only the scanning electrode 32b is generated.
By generating one or more of 2, the second LO
It is easily distantly related to the vertical n times angle display obtained by adding 1 to the number of occurrences n-1 of the AD signal L2. Furthermore, since the first and second LOAD signals LIXLx can be input to the same LOAD signal input terminal, it is possible to easily display an n-vertical angle using the conventional signal side drive IC36a and scanning side drive IC36b. becomes.

FIG. 2(d) shows a LOAD signal generation circuit for performing the driving method of the present invention by using the conventional signal side driving IC 36a and scanning side driving IC 36b as they are.

That is, the counter 27 counts, for example, the 81st clock pulse CP. Further, the oscillation portion 28 creates a signal having a width smaller than the duty ratio of the clock pulse CP.

When the counter 27 counts the 81st clock pulse CP, it outputs the second LOAD signal L2. As a result, by interposing the LOAD signal generation circuit between the conventional display controller and the LOAD signal input terminal, double-height display is possible.

Although the above-mentioned embodiment has been explained using a transmission type liquid crystal display device having a backlight 37, it can be widely used not only a reflective type but also a stacked type liquid crystal display device in which a plurality of liquid crystal layers are stacked.

[Effects of the present invention]

As described above, according to the driving method of a liquid crystal display element of the present invention, a plurality of signal-side electrodes connected to a display data storage register and a plurality of scanning-side electrodes sequentially scanned by a load signal form a liquid crystal layer. In a driving method of a liquid crystal display element sandwiching a clock pulse signal, a load signal whose duty ratio of the clock pulse signal is small until the display data corresponding to all signal side electrodes is transferred to the register in synchronization with the clock pulse signal. Since the scanning side electrode is activated by generating the
Conventional signal side drive IC and scanning g4!9! By using the LOAD signal input terminal of the dynamic IC as is, it is possible to easily achieve n-fold vertical display.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram for explaining a driving method of a liquid crystal display element according to the present invention. FIGS. 2(a) and 2(b) are signal pulse generation diagrams for explaining the operation of the driving method of the liquid crystal display element of the present invention, and FIG. 2(c) is for explaining the second LOAD signal. FIG. 2(d) is a circuit diagram for generating the second LOAD signal. FIG. 3(a) is a plan view showing the structure of a typical liquid crystal display element, and FIG. 3(b) is a sectional view taken along the line X--X in FIG. 3(a). 31a, 31b--Transparent substrate 32a...Signal side electrode 32b...Scanning side electrode 34...Liquid crystal layer 36a...Signal side drive IC 36b ...Pa... Scanning side drive IC

Claims (1)

[Scope of Claim] A driving method for a liquid crystal display element in which a liquid crystal layer is sandwiched between a plurality of signal-side electrodes connected to a display data storage register and a plurality of scanning-side electrodes that are sequentially scanned by a load signal, the register comprising: Until the display data corresponding to all the signal side electrodes is conveyed in synchronization with the clock pulse signal,
A driving method for a liquid crystal display element, characterized in that a plurality of load signals having a small duty ratio of the clock pulses are generated to activate only a scanning side electrode.