JP2920115B2 - Digital correlator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlator for calculating a correlation coefficient between a pair of input signals, and more particularly to a digital correlator having an improved S / N ratio of the calculated correlation coefficient.

[0002]

2. Description of the Related Art In a satellite communication system using a communication satellite, a mobile communication system, an international communication system using an optical fiber, and the like, there are various reasons such as a long transmission line distance and a large output power. The signal received by the receiving station has a low signal level, is mixed with high-level noise, and has a significantly reduced S / N ratio.

As a technique for detecting a weak signal from a received signal mixed with such large noise, a spread spectrum communication system (SSC Spread Spectum Communication) is employed. In this spread spectrum communication system,
As is well known, an information transmitting station spreads the spectrum of an information signal to be transmitted over a wide frequency band using, for example, a pseudo-random signal (PN pattern signal) or the like, and transmits the spread signal to a transmission path.

[0004] When the information receiving station receives the spread weak signal, it despreads (converges) the spectrum of the received signal and restores the original information signal. Further, by performing a correlation process on the restored signal, S / N
The ratio can be improved.

[0005] The signal processing circuit of the receiving station in which the correlation processing process is incorporated is configured as shown in FIG. 5, for example.

A received signal a ₁ having a waveform shown in FIG. 7 received via an antenna (not shown) is input to an analog correlator 2 from an input terminal 1 of the signal processing circuit.
The reference signal a ₂ having a waveform shape shown in FIG. 7 to another input terminal 3 is input. The received signal a ₁ is, for example, a signal obtained by synthesizing a PN pattern signal and a carrier signal (not shown), and the reference signal a ₂ is a delayed PN pattern signal obtained by delaying the PN pattern signal by a predetermined time τ _S and the carrier signal. Is a signal obtained by combining the signals.

The analog correlator 2 is an analog multiplier 2a
And an analog integrator 2b.

[0008] received signals a ₁ and the reference signal a ₂ is input from the input terminals 1 and 3 to the multiplier 2a. Multiplier 2a
As shown in FIG. 7, the received signal a ₁ and the reference signal a ₂ are multiplied in an analog manner, and the multiplied signal b is converted to the next integrator 2b.
Send to

The integrator 2b comprises, for example, a resistor 2, a capacitor 2d, an OP amplifier 2e and a switch 2f, as shown in FIG. 6, and transfers the charge of the input multiplication signal b to the capacitor 2d via the resistor 2c. accumulate. Then, the integrator 2b outputs the terminal voltage of the capacitor 2d as the correlation coefficient j. The integration time (measurement time) T _I in the integrator 2b is given in advance from the outside via the input terminal 4.

As shown in the time chart of FIG. 7, when the reset signal from the outside is released, the switch 2f is opened to start integration, and the designated integration time (measurement time) T ₁ is reduced. After elapse, the switch 2f is closed, the electric charge accumulated in the capacitor 2d is discharged, and the correlation coefficient j is reset to “0”.

The correlation coefficient j output from the analog correlator 2 is calculated by the A / D converter 5 at a predetermined sampling period f _S.
/ D conversion and input to the next data processing unit 6.

The data processing unit 6 reproduces a weak signal from a received signal containing a large noise component by using the correlation coefficient j inputted every time the above-mentioned integration time (measurement time) T _I elapses, In addition, if necessary, the transmission quality of the signal transmission path is evaluated.

Thus, by using the analog correlator 2,
Calculating a correlation coefficient j of the received signal a ₁ and the reference signal a ₂ is, reference signal a ₂ at all does not include noise in the received signal a ₁ is the delay time tau _S delayed with respect to the received signal a ₁ since the signal to become the analog correlator 2 will be calculates the autocorrelation coefficients of the received signal a _1. Generally, by calculating the autocorrelation coefficient of a signal, it is possible to remove a noise component having no frequency component contained in the signal.

[0014]

However, the signal processing circuit incorporating the analog correlator 2 shown in FIG. 5 still has the following problems to be solved.

The correlation coefficient j obtained by the analog correlator 2
Depends on the calculation accuracy of the analog multiplier 2a and the calculation accuracy of the analog integrator 2b, as shown in FIG. However, in general, the analog multiplier 2a has two input signals a
If there is a large level difference between ₁ and a ₂ , there is a concern that a large multiplication error will occur. This multiplication error appears as an offset (DC bias) of the output multiplication signal b.

Further, even if the signals a having substantially the same signal level
_1, even a ₂ is input, due to ambient temperature or the like,
There is a concern that a DC drift occurs in the output multiplication signal b.

When a DC drift occurs in the multiplied signal b output from the multiplier 2a, the DC drift is directly applied to the correlation coefficient j as an integration result of the analog integrator 2b constituted by the above-described resistor and capacitor. Remains.

For example, when the positive offset voltage + V _OS is generated, the multiplied signal b ₁ shifted to the positive side as shown in FIG. 7 is output and input to the integrator 2b. As a result, as shown in the figure, the correlation coefficient j ₁ output from the integrator 2b has a larger slope and a larger maximum value than the correct correlation coefficient j without the offset voltage V _OS as shown in the figure. Value.

Conversely, when the negative-side offset voltage −V _OS is generated, the multiplied signal b ₂ shifted to the negative-side as shown in FIG. 7 is output and input to the integrator 2b. as a result,
As shown in the drawing, the correlation coefficient j ₂ output from the integrator 2b has a negative slope and a smaller maximum value than the correct correlation coefficient j when there is no offset voltage V _OS. Value.

Also, in the analog integrator 2b,
There is a concern that a DC drift occurs in the correlation coefficient j that is the output integration result due to the ambient temperature or the like.

As described above, S of the obtained correlation coefficient j
In order to increase the / N ratio, it is necessary to increase the integration time (measurement time) T _I in the integrator 2b. However, if the integration time T _I is increased, the above-described DC drift included in the multiplication signal b is reduced. Since it is included in the correlation coefficient j, it is difficult to obtain a correct correlation coefficient j as long as the analog correlator 2 is used.

Further, analog multipliers 2a and integrators 2b in which the generation of DC drift is suppressed as much as possible are extremely expensive and have a problem that the circuit configuration is complicated.

The present invention has been made in view of such circumstances, and by constructing a multiplier and an integrator using digital circuit elements, an analog multiplier and an integrator have a simple digital circuit configuration. The present invention provides a digital correlator that can prevent the occurrence of a DC drift caused by using the above, can always obtain a correct correlation coefficient, and can easily improve the calculation accuracy of the correlation coefficient by increasing the measurement time. The purpose is to:

[0024]

[0025]

[Means for Solving the Problems] In order to solve the above problems
In the digital correlator according to the present invention, a PN pattern generator for outputting a PN pattern signal, and an A / D converter for A / D converting the PN pattern signal output from the PN pattern generator and received via the transmission line are provided. A D converter and a delay PN for outputting a delay PN pattern signal delayed by a predetermined time with respect to the PN pattern signal output from the PN pattern generator
Each signal value of the received PN pattern signal output from the A / D converter is sequentially input as a first input value to the pattern signal generating means and the input terminal, and the delayed PN pattern from the delayed PN pattern signal generating means is input to the control terminal. Each signal value of the signal is sequentially input as a second input value represented by a binary value, and outputs a first input value when the second input value input to the control terminal indicates one of binary states. A logic inverter for outputting a one's complement value of the first input value when the second input value indicates the other state of binary, an integrated value latch circuit for latching the input integrated value, When the input value is in one of two states, the output value of the logic inverter and the integrated value latched by the integrated value latch circuit are added and sent to the integrated value latch circuit as a new integrated value. When the value is in the other state of binary A full adder which adds 1 to 2 and complements it to send it to the integrated value latch circuit as a new integrated value, and outputs the integrated value latched by the integrated value latch circuit in response to the input output command. An output gate circuit for sending the integrated value to the integrated value latch circuit every time a preset integration cycle elapses, and a timing control unit for sending the output command to the output gate circuit.

[0026]

The basic operation of the digital correlator constructed as described above is, for example, in synchronization with the sampling signal, the correlation coefficient between the first digital input value and the second digital input value sequentially inputted. calculate.

That is, the first input value is F (t),
If the second input value is F (t + τ), the correlation coefficient R
(Τ) is expressed by equation (1).

[0028]

(Equation 1)

Since the second input value G (t) has a 1-bit configuration, if [1] is regarded as [+1], and if [0] is regarded as [-1], F (t + τ) = [1], F (t) F (t + τ) = F (t), where F (t + τ) = [0], F (t) F (t + τ)
= −F (t).

That is, when the second input value is [1],
It indicates that the first input value is added to the integrated value, and when the second input value is [0], it indicates that the first input value is subtracted from the integrated value.

As is well known, subtracting in a digital adder / subtractor means adding the two's complement of the value to be subtracted.

Therefore, in the present invention, when the second input value is [1] in the logical inverter, the input first input value is sent to the next full adder as it is, and the second input value is output. Is [0], the complement of the input first input value is sent to the next full adder.

In the full adder, the output value from the logical inverter is sequentially added to the integrated value latched in the integrated value latch circuit. When the second input value is [0],
The above equation (1) is realized by further adding [1] to the addition value. Therefore, a highly accurate correlation coefficient R (τ) can be obtained with a simple digital circuit configuration.

In addition to the above-described logic inverter, integrated value latch circuit and full adder, a PN pattern generator and a delay P
An N-pattern signal generator, an A / D converter, an output gate circuit, and a timing controller are provided.

In such a configuration, the first input value sequentially input to the logical inverter is subjected to A / D conversion of the PN pattern signal output from the PN pattern generator and received via the measured object. Input value. The second input value sequentially input to the logic inverter is a delayed PN pattern signal delayed by a predetermined time from the PN pattern signal output from the PN pattern generator.

The timing control section sends a command to clear the integrated value to the integrated value latch circuit and an output command to the output gate circuit every time a preset integration cycle elapses.

As a result, every time the integration period elapses, the integrated value latched in the integrated value latch circuit is output as a correlation coefficient.

[0038]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a distance measuring apparatus in which a digital correlator of the embodiment is incorporated. 2 and 3 are time charts showing the operation of the distance measuring device.

The PN pattern generator 11 includes, for example, an N-stage shift register and one exclusive OR gate. When a start signal ST is input from the input terminal 12,
An M series PN pattern signal d having a data period of (2 ^N -1) is output in synchronization with a clock signal c having a predetermined clock period T ₀ (frequency f ₀ ) input from another input terminal 12a. I do.

The P output from the PN pattern generator 11
The N-pattern signal d is phase-modulated in the signal transmission processing unit 13 by a signal combiner (mixer) 14 with a carrier signal h having a carrier frequency f _C output from a carrier oscillator 15. The phase modulation signal e output from the signal combiner (mixer) 14 is amplified by the amplifier 16 and then radiated, for example, via an antenna 17.

The signal reception processing unit 18 includes the signal transmission processing unit 1
The radio wave radiated from the antenna 17 of the antenna 3
9.

The antenna 17 of the signal transmission processing unit 13
The transmission path between the antenna and the signal reception processing unit 18 is a measured transmission path. In actual measurement, the measured transmission path is a round-trip path to a communication satellite or an optical fiber laid between cities. Signal transmission processing unit 1
3 and the signal reception processing unit 18 are housed in the same case. Therefore, there is no time delay of the carrier oscillator 15 between the signal transmission processing unit 13 and the signal reception processing unit 18.

The received signal g received by the antenna 19 is band-limited by a band-pass filter (BPF) 20,
The signal is amplified by the amplifier 21. The received signal amplified by the amplifier 21 is input to the next demodulator 22.

The demodulator 22 converts the received signal to the carrier wave
Is demodulated to a signal corresponding to the original PN pattern signal with the carrier signal h output from the. The demodulated signal output from the demodulator 22 has its high-frequency noise component removed by a low-pass filter (LPF) 23 and is input to the A / D converter 24 as a new demodulated signal k.

The A / D converter 24 is composed of, for example, a bipolar A / D converter, and is synchronized with a sampling signal SK having a frequency f _S (period T _S ) input from a clock input terminal 25. Then, the input demodulated signal k is A / D converted into, for example, 8-bit data. The digital demodulated signal p as the demodulated PN pattern signal output from the A / D converter 24 is input as a first input value to one input latch circuit 27 via the input terminal 26a of the next digital correlator 26. You.

On the other hand, the clock signal c input from the input terminal 12a is input to a PN pattern generator 11a having the same configuration as the PN pattern generator 11. When the start signal ST is input from the input terminal 12, the PN pattern generator 11a receives the start signal ST by the delay time τ stored in the delay time setting register 28.
P delayed from the PN pattern signal d output from
And outputs the N pattern signal d _1.

The delay time τ stored in the delay time setting register 28 is read and downloaded by the control unit 39 by reading the time stored in the control signal register 40.

The delayed PN pattern signal d ₁ output from the PN pattern generator 11 a is input to the other input latch circuit 29 via the control terminal 26 b of the digital correlator 26.

Each of the input latch circuits 27 and 29 is a kind of D
Input terminal 25a.
The 8-bit demodulated signal p applied to the input terminal D in synchronization with the rising of the sampling signal SK input from the
And the delay PN pattern signal d ₁ is taken out and output from the output terminal Q.

The 8-bit demodulated signal p ₁ output from one input latch circuit 27 is applied to the input terminal IN of the next logical inverter 30. The delayed PN pattern signal d ₂ output from the other input latch circuit 29 is applied to the control terminal COM of the logical inverter 30.

When the value of the delay PN pattern signal d ₂ applied to the control terminal COM is in the state of [1], that is, in the H level state, the logic inverter 30 changes from the output terminal OUT to the input terminal IN. It applied the same to output a demodulated signal p ₂ and demodulated signal p ₁ of 8 bits are. On the other hand, the control terminal COM applied value of the delay PN pattern signal d ₂ is the [0] state, i.e., in the L level, the demodulated signal of 8 bits which is applied from the output terminal OUT to the input terminal IN p wherein the inverted bit values of ₁ indicating the complement of the demodulated signals p ₁ and outputs a demodulated signal p _2.

The 8-bit demodulated signal p ₂ output from the output terminal OUT of the logic inverter 30 is output to the next intermediate latch circuit 3
1 is applied to the input terminal D. On the other hand, the delayed PN pattern signal d ₂ output from the other input latch circuit 29 is applied to the input terminal D of another intermediate latch circuit 32.

Each of the intermediate latch circuits 31 and 32 has, for example, D
The flip-flop comprises an 8-bit demodulated signal p ₂ and a delayed PN pattern signal d ₂ applied to an input terminal D in synchronization with a rise of the sampling signal SK. Output.

The 8-bit demodulated signal p ₃ output from the intermediate latch circuit 31 is applied to one input terminal A of the next full adder 33. Further, the delayed PN pattern signal d ₃ output from the intermediate latch circuit 32 is applied to the carry terminal CI of the full adder 33. That is, the intermediate latch circuit 3
Reference numerals 1 and 32 denote latch circuits having a function of matching the timings at which the demodulated signal p ₃ and the delayed PN pattern signal d ₃ are applied to the full adder 33.

To the other input terminal B of the full adder 33, the integrated value SM ₂ of a plurality of bits output from the next integrated value latch circuit 34 is applied.

The full adder 33 has a carry terminal C
The delayed PN pattern signal d ₃ applied to I is [1]
State, i.e., in the H level state, the synchronization with the rising edge of the sampling signal SK, adds the value of the demodulated signal p ₃ being applied to the input terminal B to the integrated value SM ₂ which is applied to the input terminal A to be applied to the input terminal D of the integrated value latch circuit 34 as a new cumulative value SM ₁ of the 12-bit addition result from the output terminal S.

On the other hand, the delayed PN pattern signal d ₃ applied to carry terminal CI is in the [0] state, that is, L
In level state, the full adder 33, in synchronization with the rise of the sampling signal SK, the value of the demodulated signal p ₃ being applied to the input terminal B to the integrated value SM ₂ which is applied to the input terminal A The addition is performed, and 1 is added to the addition result. The addition result is applied to the input terminal D of the integrated value latch circuit 34 from the output terminal S as a new integrated value SM ₁ of a plurality of bits.

That is, when the delay PN pattern signal d ₃ is in the [0] state, the logical inverter 30 and the full adder 33
Constitutes a circuit for adding the two's complement of the input demodulated signal p, and consequently executes the function of subtracting the value of the demodulated signal p from the integrated value SM ₂ .

The integrated value latch circuit 34 takes in the integrated value SM ₁ of a plurality of bits applied to the input terminal D in synchronization with the rise of the sampling signal SK, and
To the input terminal D of the full adder 33 and the output gate circuit 35 as a new integrated value SM ₂ .

[0061] Further, the integrated value latch circuit 34, the clear signal CL from the timing controller 36 is applied to the clear terminal CL, it clears the integrated value SM ₂ which is currently latched in the 0 value.

The output gate circuit 35 is formed of, for example, a D-type flip-flop. When an output command OUT is input from the timing control unit 36 to the control terminal EN, the output gate circuit 35 is connected to the input terminal D at that time. The integrated value SM ₂ of bits is sent to the external control unit 39 as a new correlation coefficient R (τ) having a plurality of bits.

To the timing control section 36, the sampling signal SK is applied through an input terminal 25a, and the read signal RE is input through other input terminals 37 and 38.
The AD and the reset signal RES are input.

When the reset signal RES input from the outside is released, the timing control unit 36
In synchronization with the next rising of the sampling signal SK, and sends a clear signal CL to the integrated value latch circuit 34 clears the integrated value SM ₂ temporarily to zero value. Further, the counting of the preset integration time T _M is started, and when the integration time T _M ends, the output command OU is sent to the output gate circuit 35.
T is transmitted, and the accumulated integrated value SM ₂ is correlated with the correlation coefficient R
(Τ).

The control section 39 is composed of a kind of microcomputer, reads out various control commands stored in the control signal memory 40, sends out various signals to the timing control section 36, and measures the distance. Controls the operation of the entire device.

Specifically, the delay time τ set in the delay time setting register 28 is sequentially changed, and each correlation coefficient R (τ) output from the digital correlator 26 when each delay time τ is set. Are collected in order. Then, a delay time τ _{S at} which a maximum correlation coefficient R (τ) _max is obtained is determined, and this delay time τ _S is set as a transmission time of a signal on a transmission path formed between the antennas 17 and 19, and Time τ _S
Is multiplied by the signal transmission speed V to calculate the distance L (= τ _S × V) of the transmission path.

The operation of the digital correlator 26 in the distance measuring apparatus thus configured will be described with reference to the time charts shown in FIGS.

First, when the reset signal RES rises at time t ₁ , the operation starts. Then, at the same time t ₁ , the clear signal CL is output, and the integrated value latch circuit 34
Integrated value SM ₂ of the is cleared to 0. When the read signal RED is input, the integration time T _M starts and the clear state is released.

Input latch circuit 27 of digital correlator 26
Is an 8-bit demodulated signal p (x ₀ , for example) sequentially output from the A / D converter 24 in synchronization with the sampling signal SK.
x ₁ , x ₂ . _{x 3, x 4, x 5} , x 6, x 7, x 8, x
₉ …)). Then, the demodulated signals p sequentially captured are time-shifted by one sampling period T _{S and} output as demodulated signals p ₁ .

Similarly, the input latch circuit 29 sequentially reads the value of the delayed PN pattern signal d ₁ output from the PN pattern generator 11 a in synchronization with the sampling signal SK, and shifts the value by one sampling period T _S. Delay P
And outputs as the N pattern signal d _2.

Then, at time t ₂ , when the delayed PN pattern signal d ₁ rises from [0] to [1], at time t ₃ delayed by one sampling period T _S , the control terminal COM of the logic inverter 30 is turned on. Changes from [0] to [1]. Therefore, in this time t ₃ before, the values of the demodulated signal p ₁ from the logic inverter 30 (x
₀₎ is the inverted complement has output as a demodulated signal p _2, and in this time t ₃ after each value of the demodulated signal p ₁ and _{(x 1, x 2 .x 3} ) directly as a demodulated signal p ₂ Output.

[0072] Then, at time t _5, the delay when the PN pattern signal d ₁ is falls to [0] [1], in one sampling period T _S delayed time t ₆ was the control terminal COM of the logic inverter 30 Input signal value of [1] to [0]
Changes to Thus, at time t ₆ after outputs the inverted complement each value of the demodulated signal _{p 1 (x 4, x 5} ) as a demodulated signal p _2.

The demodulated signal p output from the logical inverter 30
Each value of _{2 (x 0, x 1,} ...) and each value of the input latch circuit 29 delays PN pattern signal d ₂ output from is again one sampling period T _S partial time shift in the intermediate latch circuits 31, 32 Then, the demodulated signal p ₃ and the delayed PN pattern signal d ₃ are applied to the full adder 33.

Therefore, before the time t ₄ when the delay PN pattern signal d ₃ indicates the [0] state, the full adder 3
3 executes consequently subtraction, the delay PN pattern signal d ₃ [1] period between times t ₄ to time t ₇ shows a state executes consequently addition.

The time t after the lapse of the accumulated time T _M
When the output command OUT rises to ₈ , the integrated value latch circuit 3
The integrated value SM ₂ output from the output gate circuit 3
5 to the control unit 39 as a correlation coefficient R (τ).

Time t when output of correlation coefficient R (τ) is completed
In _9, the clear signal CL is falling, the integrated value integrated value SM ₂ which is latched in the latch circuit 34 is cleared to zero.

In the digital correlator configured as described above, since the analog multiplier 2a and the analog integrator 2b are not incorporated as in the conventional analog correlator 2 shown in FIG. Even if the product-sum operation is performed over the range, the DC drift does not occur, so that the correlation coefficient R (τ) can be calculated with high accuracy.

Next, a signal component embedded in noise is calculated from the demodulated signal p received and demodulated by the signal reception processing unit 18 using the digital correlator configured as described above to calculate a correlation coefficient. FIG. 4A and FIG. 4B will be used to explain in detail the reason why a high S / N ratio can be detected.

Each sampled instantaneous value of the noise component is distributed over a wide range represented by, for example, a normal distribution over positive and negative polarities. On the other hand, since the signal component maintains a constant value, as shown in FIG. 4 (a), the noise component is reduced during the execution of the product-sum operation shown in the above-mentioned equation (1) at a fixed integration time T _M. However, since the signal component maintains a constant value, the S / N ratio is improved.

Next, a description will be given of a case where the noise component increases as the signal component increases, as shown in FIG.

In the case where the magnitude of the signal and the magnitude of the noise have a correlation as described above, the S / N ratio may increase by N ^1/2 if the product-sum operation represented by the equation (1) is executed N times. Are known. This is shown below.

Now, assuming that the product-sum operation is performed N times, when the signal component of the measurement data Xi (t) of the i-th correlation coefficient is si and the noise component is ni, the signal component of the N-times measurement is calculated. The sum is given by equation (2).

[0083]

(Equation 2)

Is obtained. In equations (2) and (3), s and n are the average amplitudes of the signal and noise. As a result, S after product-sum operation
/ N is the S / N = Ns / (N 1/2 n) = N 1/2 (s / n) ... (4). In the equation (3), the signal component becomes N times and the noise component becomes N ^1/2 times by the N times of the product-sum operation, and the S / N ratio obtained by summing them becomes N ^1/2 times as a whole. I can understand.

Therefore, a weak signal buried in the noise component is detected from the demodulated signal having a large noise component.

The degree of improvement in the S / N ratio is shown in FIG.
(A) As shown in (b), in addition to the measurement time T _M (product-sum operation time), the frequency f _S of the sampling signal when the signal is A / D converted is increased, and the product-sum operation is performed. In such a case, the number of data may be increased.

In the distance measuring apparatus in which the digital correlator of this embodiment is incorporated, the combined signal e transmitted from the transmission signal processing unit 13 via the antenna 17 is generally received by the reception signal processing unit 18. In the process of being transmitted through the transmission path to be measured, large noise is mixed in, and the S / N ratio of the received signal g and the demodulated signal p is greatly reduced.

However, by calculating the correlation coefficient R (τ) between the demodulated signal p and the delayed PN pattern signal d ₁ by the digital correlator, the maximum correlation coefficient R (τ) when the delay time τ is changed is calculated. ) _Max can be detected with high accuracy.

By setting the measurement time T _M of the correlation coefficient R (τ) at one delay time τ large, the measurement accuracy of the correlation coefficient R (τ) at each delay time τ can be further improved. Therefore, the measurement accuracy of the finally obtained distance L of the transmission path to be measured can be further improved.

Further, in this digital correlator,
As shown in FIG. 1, a logic inverter 30, a full adder 33, an integrated value latch circuit 34, and a plurality of latch circuits 27 , 29 , 31.32 for adjusting the input timing of each signal value ,
A / D converter 24, PN pattern generators 11, 11a,
The delay time setting register 28, the output gate circuit 35, and the
Since it is composed of relatively inexpensive digital circuit elements such as the imaging control unit 36 , the circuit configuration does not become complicated and the manufacturing cost does not increase significantly.

[0091]

[0092]

As described above, in the digital correlator according to the present invention, a logical sum, a full adder and an integrated value latch circuit are used to digitally execute a summation operation for obtaining a correlation coefficient. ing.

Therefore, since the analog multiplier and the analog integrator are not incorporated as in the conventional analog correlator, the product-sum operation is performed for a long time even for the purpose of improving the S / N ratio. However, since no DC drift occurs, the correlation coefficient can be calculated with high accuracy.

Further, since it is composed of relatively inexpensive digital circuit elements such as a logical inverter, a full adder, and an integrated value latch circuit, the circuit configuration does not become complicated and the manufacturing cost does not increase significantly. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a distance measuring device in which a digital correlator according to an embodiment of the present invention is incorporated.

FIG. 2 is a time chart showing an operation of the digital correlator of the embodiment.

FIG. 3 is a time chart showing the operation of the digital correlator in the same embodiment.

FIG. 4 is a diagram showing a relationship between a signal and noise in a demodulated signal input to the digital correlator of the embodiment.

FIG. 5 is a block diagram showing a schematic configuration of a signal processing circuit using a conventional analog correlator;

FIG. 6 is a circuit diagram showing an analog integrator incorporated in the analog correlator;

FIG. 7 is a time chart showing the operation of the analog correlator.

[Explanation of symbols]

11, 11a: PN pattern generator, 13: signal transmission processor, 14: signal synthesizer, 15: carrier oscillator, 1
6, 31 amplifier, 17, 19 antenna, 18 signal reception processing unit, 20 bandpass filter, 22 demodulator, 23 low-pass filter, 24 A / D converter, 2
6 Digital correlator, 27, 29 Input latch circuit, 2
8 ... Delay time setting register, 30 ... Logic inverter, 31,
32 ... Intermediate latch circuit, 33 ... Full adder, 34 ... Integrated value latch circuit, 35 ... Output gate circuit, 36 ... Timing control unit, 39 ... Control unit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yukio Horiuchi 2-3-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (72) Inventor Shu Yamamoto 2-3-Nishi-Shinjuku, Shinjuku-ku, Tokyo No. 2 International Telegraph and Telephone Corporation (72) Inventor Shigeyuki Akiba 2-3-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo International Telegraph and Telephone Corporation (72) Inventor Hiroharu Wakabayashi 2 Nishi-Shinjuku, Shinjuku-ku, Tokyo No. 3-2, International Telegraph and Telephone Corporation (56) References JP-A-63-223870 (JP, A) JP-A-64-26976 (JP, A) JP-A-49-11242 (JP, A) JP-A-5-2470 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04J 13/00 G06F 17/15

Claims (1)

(57) [Claims] 1. A PN pattern generator (11) for outputting a PN pattern signal, and an A / D converter for A / D converting a PN pattern signal output from the PN pattern generator and received via a transmission line. vessel (24), delayed PN pattern signal generating means for outputting a delayed PN pattern signal delayed a predetermined time relative to the PN pattern signal output from the PN pattern generator and (11a, 28), wherein the input terminal a Each signal value of the received PN pattern signal output from the / D converter is sequentially input as a first input value, and each signal value of the delayed PN pattern signal is binary to the control terminal from the delayed PN pattern signal generating means. The second represented
The first input value is output when the second input value input to the control terminal indicates one of the binary states, and the second input value is the binary value A logical inverter ( 30 ) for outputting the one's complement value of the first input value when indicating the other state of the first input value, and an integrated value latch circuit (34) for latching the input integrated value
And when the second input value is in one of the two states, adding the output value of the logical inverter and the integrated value latched by the integrated value latch circuit to obtain a new integrated value as the integrated value latch. And, when the second input value is in the other state of the binary, adds 1 to the added integrated value to form a two's complement and sends it to the integrated value latch circuit as a new integrated value. A full adder (33), an output gate circuit (35) for sending out the integrated value latched in the integrated value latch circuit in response to the input output command, and a preset integration period A digital correlator comprising: a timing controller (36) for sending a command to clear the integrated value to the integrated value latch circuit and sending an output command to the output gate circuit every time.