JPH0964783A - Spread spectrum communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of a digital correlation device and to miniaturize circuit scale by receiving the output of a subtraction means and controlling the phase of the sampling clock inputted in an A/D conversion means. SOLUTION: This equipment is provided with digital correlation means 15 and 16 for correlating the signal converted into a base band with a desired signal, a delay means 18 for delaying the outputs of the correlation means 15 and 16, a subtraction means 19 for subtracting the outputs of the correlation means 15 and 16 and the output of the delay means 18 and a control means 20 receiving the output of a subtraction means 19 and controlling the phase of the sampling clock inputted in h/D conversion means 13 and 14. By controlling the phase of the sampling clock from the difference of the signal passed through the delay circuit 18 and the signal which is not passed through or controlling the phase of the sampling clock according to the deviation amount of a correlation peak for which the sampling is performed, circuit scale can be miniaturized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication device, and more particularly to a receiving device using a digital correlator.

[0002]

2. Description of the Related Art A spread spectrum communication system uses a spread code sequence such as a pseudo noise code (PN code) from a normally transmitted digital signal to generate a signal having an extremely wider bandwidth than the original data. It is converted into an RF (radio frequency) signal and transmitted.

The transmission data is spread-modulated by a spreading code having a wider band than the transmission data output from the code generator, and then converted into a predetermined frequency by a carrier wave and transmitted.

On the receiving side, the same spreading code for demodulation as on the transmitting side is used to perform despreading (spread demodulation) for correlating with the received signal.
Then, the received signal is converted into a narrow band signal having a bandwidth corresponding to the original data. Then perform normal data demodulation,
Play back to the original data.

FIG. 14 shows a conventional demodulation circuit. The received signal is subjected to signal processing such as amplification and filtering, and is frequency-converted to an intermediate frequency in some cases, and then branched into two, and converted into baseband band signals (Ich.Qch) by orthogonal carrier waves. Correlation calculations are performed on the signals in each baseband band by the demodulating correlators 15 and 16, the lead phase correlators 31 and 32, and the lag phase correlators 33 and 34, respectively. Here, the lead phase correlators 31, 32
Is for the demodulation correlators 15 and 16 in a phase advanced by Δ chips, and the delayed phase correlators 33 and 34 are for the demodulation correlators 15 and 16 in a phase delayed by Δ chips. . A calculator 35 calculates a lead movement correlation value from the outputs of the Ich lead phase correlator 31 and the Qch lead phase correlator 32, and the calculator from the outputs of the Ich lag phase correlator 33 and the Qch lag phase correlator 34. 36, the delayed phase correlation value is calculated, and the delayed phase correlation value is subtracted from the advanced phase correlation value by the subtractor 39 to detect the phase shift, and the control circuit 30 controls the voltage controlled oscillator through a filter as necessary. A signal is input and synchronization is maintained. In the synchronization holding state, the data reproducing section 21 calculates the amplitude / phase from the outputs of the Ich demodulation correlator 15 and the Qch demodulation correlator 16 and demodulates the data.

[0006]

However, in the above conventional example, a large number of digital correlators are required,
There was a problem that the circuit scale was large.

[0007]

According to the present invention, a digital correlating means for correlating a signal converted into a baseband band with a desired signal, a delay means for delaying the output of the correlating means, and the correlating means. It is characterized by further comprising: subtraction means for subtracting the output of the means and the delay means; and a control means for receiving the output of the subtraction means and controlling the phase of the sampling clock input to the A / D conversion means.

With this configuration, the number of digital correlators can be reduced and the circuit scale can be reduced.

[0009]

FIG. 1 is a demodulation circuit of a first spread spectrum communication apparatus embodying the present invention. In FIG. 1, 2 is a high frequency signal processing unit 11, 12 is a first and second frequency converter for converting the received signal into a signal in the base band. The frequency converter 11 is composed of an oscillator 11A, a mixer 11B and a filter 11C, and the frequency converter 12 is composed of a mixer 12A which shifts the oscillator output by 90 degrees, a mixer 12B and a filter 12C. 13,
14 is an analog / digital converter, 15 and 16 are correlators that correlate with a desired spread code, 17 is a synthesizing circuit that synthesizes the correlation outputs of the two correlators 15 and 16, and 18 is the output of the synthesizing circuit 17. A delay circuit for delaying by a predetermined time, 19 is a subtraction circuit for subtracting the output of the combining circuit 17 and the output of the delay circuit 18, and 20 is an analog /
A clock control circuit for controlling the phase of the sampling clock input to the digital converters 13 and 14, 21 is 2
The data reproducing unit 200 which receives the correlation outputs of the two correlators 15 and 16 and reproduces data is a clock output unit.

The operation of this apparatus will be described with reference to FIG. The received signal r (t) · exp (jωt) that has been subjected to processing such as amplification and filtering by the high frequency unit 2 and has been converted to the input frequency or the intermediate frequency is branched into two.
The signals r ₁ (t) and r _Q (t) in the baseband bands, which are input to the first frequency converter 11 and the second frequency converter 12, respectively, are output. Here, when the phase difference between the received signal and the output signal of the oscillator 11A is α, r ₁ (t) = r (t) cos α, r _Q (t) = r (t)
Expressed as sin α.

Next, the baseband signal r ₁ (t),
r _Q (t) is the analog / digital converter 1
Samples 3 and 14 are sampled at a frequency that is at least twice the chip rate of the spread code and input to correlators 15 and 16 to perform correlation calculation with a predetermined spread code. Here, the predetermined spreading code is usually the same code as the spreading code used for spreading modulation on the transmitting side. The outputs of the correlators 15 and 16 are c
_{If 1} (t) and c _Q (t), then C ₁ (t ₁ ) = c (t) cos α, c _Q (t) = c
It is expressed as (t) sin α. However, c (t) is an output when the signal r (t) is input to the correlators 15 and 16.

Outputs c ₁ of the two correlators 15 and 16
The synthesis circuit 17 synthesizes (t) and c _Q (t). An example of the combining circuit 17 is shown in FIG. In FIG. 2A, 2
The outputs c ₁ (t) and c _Q (t) of the two correlators 15 and 16 are respectively squared and then added to perform a square root operation. By this calculation, the absolute value output of c (t) is obtained.
Another example of the synthesizing circuit 17 is shown in FIGS. 2 (B), (C) and (D). In FIG. 2B, the amount of calculation is reduced by omitting the square root calculation of FIG. In FIG. 2C, the absolute value calculation is performed instead of the square calculation,
The calculation amount is further reduced from that of FIG. FIG.
In (D), by providing a selector that selects one of the two signals instead of addition, the amount of calculation can be further reduced compared to FIG. 2 (C).

Now, the output of the synthesizing circuit 17 is branched into two,
The subtraction circuit 19 subtracts the signal that has passed through the delay circuit 18 and the signal that does not pass through the delay circuit 18. Here, the operation will be described in detail with reference to FIG. In FIG. 3, as an example,
With 1 chip 2 sampling, the delay amount of the delay circuit 18 is 1 chip, that is, 2 sampling, and the black circles in the figure represent the sampling points. Also, the dotted line shows the case where the analog amount, that is, the sampling frequency is infinite. First, when the phase of the sampling clock is delayed, the output of the synthesis circuit 17 in FIG.
The output of the subtraction circuit 19 at the point t1 which is half the delay amount of the delay circuit 18 from the point t0 which is the maximum in the cycle, that is, at the point t1 after 1/2 chip (1 sampling) becomes negative. If the phase of the sampling clock is advanced (see Fig. 3
(B), the output of the subtraction circuit 19 at the point t1 becomes positive. Moreover, since its magnitude represents the degree of deviation, the point t
Clock phase synchronization can be achieved by controlling the output of the subtraction circuit 19 at 1 to approach 0.

Therefore, the point t1 (that is, the combining circuit 19)
The clock control circuit receives the output of the subtraction circuit 19 from the time point (detected by the peak detection circuit 25) that gives the maximum value within one cycle of Clock synchronization is maintained by controlling the phase of the sampling clock by 20.

The clock control circuit 20 is shown in FIG.
As shown in (A), the delay circuit 20A, the latch 20B, the filter 20C, and the digital-analog converter (D / A) 2
0D, voltage controlled oscillator (VCO) 20E. Here, the filter 20C and the digital converter (D /
A) The order of 20D may be changed. As another example of the clock control circuit 20, as shown in FIG. 4B, the signal output from the reference signal generator 20F may be phase-shifted by the output from the subtraction circuit 19 and output as a clock. Good.

The delay time by the delay circuit 20A is half the delay time by the delay circuit 18. The latch 20B is
The output of the subtraction circuit 19 is latched when the delay time of the delay circuit 20A elapses from the peak of the output of the synthesis circuit 17. Then, the clock control circuit 20 uses the latch 20B.
The clock is controlled so that the output of becomes small.

When the clock synchronization is maintained, the data reproducing section 21 extracts the outputs from the two correlators 15 and 16 at the point t1 and obtains the amplitude and / or the phase from the two signals to perform the data demodulation. .

Next, an embodiment of a code division multiplex communication system which modulates a plurality of parallel data by different spreading codes, multiplexes and transmits the same will be described.

FIG. 5 is a block diagram of a transmitter of a code division multiplex communication system. In FIG. 5, n parallel transmission data are spread-modulated by n different spreading codes, combined, converted to a desired frequency, and transmitted.

FIG. 6 is a block diagram showing a second embodiment of the receiving apparatus of the present invention.

Reference numerals 13 and 14 denote frequency converters 11 and 1 shown in FIG.
2 converted baseband signals r ₁ (t), r _Q
An analog / digital converter for digitally converting (t), 200 is a clock output section, 15 and 16 are correlators for correlating with a desired spread code PN _r, and 17 are correlation outputs of the two correlators 15 and 16. A synthesizing circuit for synthesizing, a delay circuit 18 for delaying the output of the synthesizing circuit 17 for a predetermined time (a time corresponding to 1 to 2 chips of the spread code), and 19 subtracts the output of the synthesizing circuit 17 and the output of the delay circuit 18. Subtraction circuit,
Reference numeral 20 denotes a clock control circuit that receives the output of the subtraction circuit 19 and controls the phase of the sampling clock input to the analog / digital converters 13 and 14;
Reference numeral _{n denotes} a correlator that takes the correlation between the input signal and the spread codes PN _{1 to} PN _n , 24-1 to 24-n are data determination circuits, and 25 is a peak detection circuit that detects the peak of the output of the synthesis circuit 17.

Also in the present embodiment, the signals r ₁ (t) and r _Q (t) in the baseband are sampled by the analog / digital converters 13 and 14 at a frequency which is more than twice the chip rate of the spread code. , And input to the correlators 15 and 16 to perform correlation calculation with the desired spread code PN _r . Here, the predetermined spreading code PN _r is usually the same code as the spreading code used for the spreading modulation on the transmitting side, and the predetermined spreading codes PN _{1 to} PN
_A code D that is the same as any one of _{n is} a code for synchronization other than that.

In the present embodiment, when synchronization is established, the outputs from the two analog / digital converters 13 and 14 are decimated by the decimating / combining circuit 22 into 1 chip 1 sampling, and the received signal and The phase difference α with the oscillator output signal is corrected. For example, the combination can be performed from the phase difference α by r
₁ (t) cosα + r _Q (t) sinα. The output of the thinning / combining circuit 22 is branched into n pieces, and the n correlators 23-1 to 23-n respectively use n pieces of spreading codes P used for spread modulation on the transmission side.
After the correlation with N _{1 to} PN _n is obtained, the data determination circuits 24-1 to 24-n demodulate the data to obtain n demodulation data. Data determination circuits 24-1 to 24-n
Performs data determination for each cycle of the spreading code in synchronization with the peak detected by the peak detection circuit 25.

With this configuration, the deviation of the sampling clocks can be corrected with a small-scale configuration, and the thinning / combining circuit 22 thins out one chip to one sampling. Therefore, the subsequent n correlators 23-1 to 23-n The circuit scale can be reduced.

In the second embodiment, a serial-parallel converter for converting high-speed data into a plurality of parallel data is added to the transmitting side, and a parallel-serial conversion for converting a plurality of demodulated parallel data into a serial data in the receiving side. High-speed data transmission becomes possible by adding a device.

In the first and second embodiments,
It is also possible to transmit information by quadrature modulation. In the case of a quadrature modulated signal, the decimating / combining circuit 22 converts the quadrature signal into a quadrature signal in which the phase difference α has been corrected, and the correlation is determined by n correlators and data determination is performed.

FIG. 7 shows the configuration of the correlators 15 and 16 in the case of 1-chip 2-sampling. When the spreading code is m bits, 15A is a 2 × m bit shift register, which shifts the outputs of the A / D converters 13 and 14 bit by bit in synchronization with the clock CLK from the clock control circuit 20. The correlators 15 and 16 further include the shift register 1
5A and the spread codes (a ₁ , a ₂ , a
₃ , ..., Am) 2 × m multipliers and the output of the multiplier 15B are added, and the adder 1 outputs as a correlation value.
With 5C.

FIG. 8 shows the configuration of the correlators 23-1 to 23-n. 23A is an m-bit shift register, 23
B is an m number of multipliers for multiplying the data stored in the shift register 23A by the spread codes (a ₁ , a ₂ , a ₃ , ... Am), and 23C is a correlator that adds the output of the multiplier 23B. It is an adder that outputs. The adder 23C outputs the adder for each spreading code-cycle according to the peak detection by the peak detection circuit 25.

The spreading codes input to the correlators 23-1 to 23-n are different. On the other hand, the spreading codes input to the correlators 15 and 16 are common.

The correlators 15 and 16 perform correlation calculation using the output clock CLK of the clock control circuit 20.
That is, assuming that the frequency of the output clock of the clock control circuit 20 is f _c , the correlators 15 and 16 perform the correlation calculation in synchronization with the clock CLK having the frequency f _c .

On the other hand, the correlators 23-1 to 23-n perform the correlation calculation using the clock generated by dividing the output clock CLK of the clock control circuit 20 in half. That is, the correlators 23-1 to 23-n have a half (1
If chip l sampling is performed, correlation calculation is performed in synchronization with a clock of 1 / l).

The clocks input to the correlators 23-1 to 23-n are set so that the correlation calculation is performed when the output of the synthesizing circuit 17 has a peak (time t _{0 in} FIG. 10C). Is generated by dividing the output clock of the clock control circuit 20.

Further, the thinning / combining circuit 22 is provided for the A / D converter 13 when a peak occurs in the output of the combining circuit 17,
A / D converter 1 so that the 14 outputs are combined and output
The thinning-out of the outputs of 3 and 14 is also combined into one sampling for one clock.

As described above, the clock frequencies of the correlators 23-1 to 23-n for despreading are set lower than the clock frequencies of the correlators 15 and 16 for correctly sampling the received signal. Therefore, accurate sampling can be performed and despreading can be realized with a small-scale configuration.

As described above, the delay amount by the delay circuit 18 is preferably a time corresponding to about 1 to 2 chips of the spread code. The delay amount may be 1 chip if it is about 1 chip and 2 samplings, but the delay amount is preferably 2 chips when the sampling frequency is higher.

Next, FIG. 9 shows another form of the clock output section 200 (FIGS. 1 and 6).

Reference numeral 20I is a peak shift detection circuit for detecting the peak shift amount from the output of the synthesis circuit 17. 20F is a reference signal generating circuit, 20H is a phase for receiving the output of the peak shift detecting circuit 20I and shifting the phase of the output signal of the reference signal generating circuit 20F, and generating a sampling clock to be supplied to the analog / digital converters 13 and 14. It is a shift circuit.

The output of the synthesis circuit 17 is input to the peak shift detection circuit 20I, and the peak shift amount is output. Here, the operation will be described in detail with reference to FIG. In FIG. 15, 1
As an example, 1 chip 2 sampling is performed, and sampling points are represented by black circles in the figure near the peak output. The dotted line shows the case of continuous time sampling. Assuming continuous-time sampling, the correlation peak is an isosceles triangle as shown by the dotted line. However, since the discrete time sampling is performed by the A / D conversion, the sampling period T _{s has} a discrete value as indicated by a black circle in the figure. Therefore, 1 of the output of the synthesis circuit 17
Detecting the maximum value alpha ₀ in the cycle, the values before and after the sampling points at which the maximum value alpha ₀ alpha _-, the deviation ΔT of the time and the true peak position having the maximum value alpha ₀ from alpha _+,
It is calculated by the following equation.

ΔT / T _s = (α ₋ −α ₊ ) / (2 · Δα)

Here, Δα is (α ₀ −α ₋ ) and (α ₀ −
It is the smaller of α ₊ ).

In the phase shift circuit 20H, the phase of the output signal of the reference signal generator 20F is shifted according to the shift amount output from the peak shift detection circuit 20I, and the sampling clock with which synchronization is established is converted from analog to digital. Output to the devices 13 and 14.

FIG. 11 shows an example of the phase shift circuit 20H. In the figure, delay circuits are cascade-connected to generate a plurality of signals having different delay amounts, and one of them is selected by a selector.

Here, as the reference signal generator 20F, T
By using a highly stable oscillator such as a CXO (temperature compensated crystal oscillator) and selecting a clock from 8 to 16 or more signals having different delay amounts, very high precision synchronization can be established. In particular, it is effective for transmission limited to the data length such as packet transmission.

When the clock synchronization is established, the data reproducing section 21 extracts the outputs from the two correlators 15 and 16 at the point t1 and obtains the amplitude and / or the phase from the two signals to perform the data demodulation. .

Further, the peak shift detection circuit 20I performs peak shift detection a plurality of times to detect the average value, the median value, and the maximum frequency, so that the influence of noise can be reduced.

FIG. 12 is a block diagram showing a third embodiment of the receiving apparatus of the present invention. According to this embodiment, the same components as those of the second embodiment shown in FIG. 6 are designated by the same reference numerals. In this embodiment, a baseband conversion circuit 6 and a carrier reproduction circuit 5 are provided instead of the quasi-baseband conversion circuit. Further, in the present embodiment, the peak detection circuit 25
Detects the peak of the correlator 15. The delay circuit 18 delays the output of the correlator 15, and the subtraction circuit 19 subtracts the output of the delay circuit 18 from the output of the correlator 15.

Further, the thinning circuit 22A includes the A / D converter 1
Decimate the output of 3 in half. The decimation circuit 22A outputs A / D so that the output of the A / D converter 13 when the output of the correlator 15 has a peak is output to the correlators 23-1 to 23-n.
The output of the D converter 13 is thinned out.

A / D converter 13, clock control circuit 2
0, correlators 23-1 to 23-n, data determination circuit 24-
The operations 1 to 24-n are common to the second embodiment shown in FIG.

Further, in FIG. 12, the clock output unit 20
0A may be configured according to FIG. In this case, Qc
Since there is no h, the correlator 16 and the synthesis circuit 17 are unnecessary.

In this embodiment, the peak shift detection circuit 20I
Calculates the deviation ΔT between the maximum value α ₀ (FIG. 10) of the output of the correlator 15 and the true peak value. Phase shift circuit 20H
Shifts the output clock of the reference signal generator 20F according to the deviation ΔT.

The structure of the carrier reproducing circuit 5 is shown in FIG.

The input signal is squared by the squaring circuit 261 and
The filter 262 extracts a carrier having twice the frequency, and the PLL 263 divides the frequency by two to reproduce the carrier. The reproduced carrier is input to the baseband conversion circuit 6, and the output from the high frequency signal processing unit 2 is converted into a baseband signal.

[0053]

According to the present invention, the phase of the sampling clock is controlled based on the difference between the signals passing through the delay circuit and the signal not passing through the delay circuit, and the phase of the sampling clock is controlled according to the deviation amount of the sampled correlation peak. The circuit scale can be reduced by controlling the.

Further, since the clock phase control is performed by the phase shift, the feedback control becomes unnecessary,
The cycle can be established at high speed.

Also, high speed communication becomes possible by performing code division multiplexed communication.

Further, by thinning out the received signal for synchronization and then demodulating it, the structure for demodulation can be downsized while ensuring accurate synchronization.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a combining circuit.

FIG. 3 is an output signal diagram of a synthesis circuit, a delay circuit, and a subtraction circuit.

FIG. 4 is a circuit diagram of a clock control circuit.

FIG. 5 is a configuration diagram of a transmitter of a code division multiplex communication system.

FIG. 6 is a configuration diagram of a second embodiment.

FIG. 7 is a circuit diagram of a correlator for synchronization.

FIG. 8 is a circuit diagram of a correlator for demodulation.

FIG. 9 is a circuit diagram of another form of the clock output unit.

FIG. 10 is an output waveform diagram of a synthesis circuit.

FIG. 11 is a circuit diagram of a phase shift circuit.

FIG. 12 is a configuration diagram of a third embodiment.

FIG. 13 is a circuit diagram of a carrier reproducing circuit.

FIG. 14 is a configuration diagram of a conventional spread spectrum device.

[Explanation of symbols]

 13 analog / digital converter 15 correlator 18 delay circuit 19 subtraction circuit 20 clock control circuit 25 peak detection circuit 200 clock output unit

Claims (15)

[Claims] 1. A spread spectrum communication device for communicating with a signal spread spectrum modulated by a spread code, and frequency conversion means for converting a received signal into a signal in a base band band, and a signal in the base band band to a digital signal. A / D converting means, a digital correlating means for correlating the digital signal with a predetermined signal, a delaying means for delaying the correlating means output, and a subtracting means for subtracting the correlating means output and the delaying means output. Control means for receiving the output of the subtracting means and controlling the phase of the sampling clock input to the A / D converting means,
A spread spectrum communication device comprising: 2. A peak detecting means for detecting a peak from the output of the correlating means is further provided, and the control means receives the output of the subtracting means and the output of the peak detecting means and inputs them to the A / D converting means. The spread spectrum communication device according to claim 1, wherein the phase of the sampling clock is controlled. 3. The frequency conversion means includes first and second frequency conversion means for converting a received signal into a signal having orthogonal baseband bands, and the A / D conversion means includes the first and second frequency conversion means. The outputs from the second frequency conversion means are first and second
And A / D converting means for converting the first and second digital signals into a predetermined signal, and the digital correlating means correlates the first and second digital signals with a predetermined signal. Digital correlating means and synthesizing means for synthesizing the outputs of the first and second correlating means, the delaying means delays the synthesizing means output, and the subtracting means outputs the synthesizing means output and the delaying means output. 2. The spread spectrum communication device according to claim 1, wherein and are subtracted. 4. The spread spectrum communication device according to claim 1, wherein the control means includes a digital-analog conversion means, a filter means, and a voltage-controlled oscillator. 5. The spread spectrum communication device according to claim 1, wherein the control means includes a filter means and a clock phase shift means. 6. The demodulation means for demodulating a code-division-multiplexed received signal by further despreading the output of the A / D conversion means with a plurality of spreading codes. Spread spectrum communication device. 7. In a spectrum system in which a signal spread-spectrum-modulated by a spread code is used for communication, a received signal is converted into a signal in a baseband band, and the baseband band signal is converted into a digital signal in accordance with a sampling signal, Correlating the digital signal sequence with a predetermined signal sequence, obtaining a difference between the correlation output and a signal obtained by delaying the correlation output, and receiving the difference signal to control the timing of the sampling signal. Spread spectrum communication method. 8. A spread spectrum communication device for communicating with a signal spread spectrum modulated by a spread code, and frequency conversion means for converting a received signal into a signal in a base band band, and a signal in the base band band to a digital signal. A / D converting means, a digital correlating means for correlating the digital signal with a predetermined signal, a peak deviation detecting means for detecting a peak deviation amount from the output of the correlating means, and an output of the peak deviation detecting means. And a control means for controlling the phase of the sampling clock input to the A / D conversion means. 9. The frequency conversion means includes first and second frequency conversion means for converting a received signal into a signal having orthogonal baseband bands, and the A / D conversion means includes the first and second frequency conversion means. First and second digital correlating means for correlating the desired signals with the first and second digital signals for converting the outputs from the second frequency converting means into the first and second digital signals, and 9. The spread spectrum communication device according to claim 8, further comprising a synthesizing unit for synthesizing the outputs of the first and second correlation units, wherein the peak shift detecting unit detects the peak shift amount from the output of the synthesizing unit. 10. The peak deviation detecting means detects a maximum value in one cycle of the spreading code and calculates a peak deviation amount from values before and after a point giving the maximum value. Spread spectrum communication device. 11. The spread spectrum communication device according to claim 8, wherein said control means includes clock phase shift means. 12. A demodulation unit for demodulating a code-division-multiplexed received signal by despreading the output of the A / D conversion unit with a plurality of spreading codes. Spread spectrum communication device. 13. In a spectrum system in which a signal spread-spectrum-modulated by a spread code is used for communication, a received signal is converted into a signal in a baseband band, and the baseband band signal is converted into a digital signal in accordance with a sampling signal, A spread spectrum communication method, wherein a correlation between the digital signal sequence and a predetermined signal sequence is obtained, a peak deviation amount is detected from the correlation output, and the timing of the sampling signal is controlled by receiving the peak deviation amount. 14. A frequency conversion means for converting a received signal into a baseband signal, an A / D conversion means for converting the baseband signal into a digital signal, and a correlation between the digital signal and a predetermined signal. And a control means for controlling the sampling clock input to the A / D conversion means according to the output of the digital correlation means, a thinning means for thinning the digital signal, and an output of the thinning means. A spread spectrum communication device, comprising: a demodulation unit that demodulates a received signal based on a spread code. 15. A received signal is converted to a signal in a base band band, the signal in the base band band is converted to a digital signal, the digital signal is correlated with a predetermined signal, and the correlation is obtained according to a result of the correlation. A spread spectrum communication method comprising controlling a sampling clock input to the A / D conversion means, thinning out the digital signal, and demodulating a received signal from the thinned output based on a spread code.