JP2919180B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus,
In particular, the present invention relates to an information processing apparatus having an ultraviolet erasing type electrically programmable read only memory (hereinafter abbreviated as PROM) in the same semiconductor substrate.

[0002]

2. Description of the Related Art A single-chip microcomputer (hereinafter, abbreviated as a single-chip microcomputer) will be described as an example of an information processing apparatus. A single-chip microcomputer generally includes a central processing unit (hereinafter abbreviated as CPU), a program memory, a data memory,
And a peripheral I / O unit including an input / output port.
In a normal operation, a program consisting of a series of instructions stored in the program memory is only supplied to the CPU and is not output to the outside via the input / output port.
The same applies to those having a PROM as a program memory.

However, since a program is written from the outside into the PROM, a path is provided between the PROM and the input / output port, and the path is a PR path.
In the mode of writing a program to the OM, the PROM
And the input / output port are electrically connected. This allows P
An external program can be written to the ROM. In order to determine whether or not the written program is correct, a mode for outputting the contents of the PROM to the outside (hereinafter referred to as a verify mode) is set. In this mode, the path connects the PROM and the input / output port. The program electrically connected again and written in the PROM is output from the above path to the outside via the input / output port.

Thus, in the normal operation mode, the PROM
Cannot be output to the outside, but if the verify mode is set, it is possible to output the program from the PROM to the outside, which causes a problem of plagiarism of the program by a third party.

[0005] For this reason, several means have been proposed for protecting a program by preventing theft of the program. One of them is to provide a verify mode control information storage cell in a PROM and to control the intermittent of the path by the storage contents of the cell. The PROM changes its threshold value between the written state and the unwritten state,
Data "0" or "1" is stored. When electrons are injected into the floating gate when the transistor of the PROM cell is Nch, the threshold value becomes a second threshold value higher than the unwritten first threshold value. By using a voltage intermediate between the first threshold value and the second threshold value as the read voltage, the unwritten P
The transistor of the ROM cell is turned on, and the transistor of the written PROM cell is turned off.

To prevent program plagiarism, PR
After the writing of the program into the OM and the verification for confirmation are completed, the verify mode control information storage cell is set to the write state. When a third party sets the verify mode for program plagiarism, first, the contents of the verify mode control information storage cell are read. Since the cell is in the write state, it is turned off, and as a result, the path between the PROM and the input / output port is electrically disconnected.

In the conventional single-chip microcomputer, since the verify mode control information storage cell has the same characteristics as the PROM cell for actually storing the program, the data stored in the verify mode control information storage cell is "0". In either the (written state) or the "1" (unwritten state), only one of the data is not likely to be output, and the ease of outputting the data is the same.

[0008]

The above program protection means does not provide sufficient program protection. That is, since the read voltage of the PROM is usually generated from the power supply voltage of the single-chip microcomputer, the read voltage can be made higher than the second threshold value of the PROM cell by increasing the power supply voltage. As a result, although the verify mode control information storage cell is in the written state, it is equivalently in the unwritten state.
The path between the ROM and the input / output port is electrically connected, and the program can be read out to the outside.

Therefore, an object of the present invention is to provide an information processing apparatus having means for sufficiently enhancing a program protection function.

[0010]

According to the present invention, there is provided an information processing apparatus comprising: a program memory;
Storage means for storing at least one bit of control information having a characteristic different from that of the program memory due to having a thick gate insulating film; a sense amplifier for reading the contents of the program memory and the storage means; Means for permitting or prohibiting output of the contents of the program memory to the outside of the information processing device based on the contents of the storage means.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a single-chip microcomputer 32 according to one embodiment of the present invention. The single-chip microcomputer 32 is configured as an integrated circuit on one semiconductor substrate, and has a PROM 5 as a program memory for storing a program consisting of a series of instructions. PROM5
Is set by a program counter (hereinafter abbreviated as PC) 3, and the designated instruction is
It is supplied to the CPU 6 via the instruction bus 36 and executed. An address control circuit (hereinafter abbreviated as ACC) 4 is interposed between the PC 3 and the PROM 5, and the ACC 4 is provided with an address control signal (hereinafter abbreviated as ADRE) as described later.
If 21 is not active, the output of PC3 is supplied to PROM5 as it is. Single chip microcomputer 32
Has a RAM 8 as a data memory and a peripheral I / O unit 31 which are interconnected by a CPU 6 and an internal bus 7. The peripheral I / O unit 31 has two input / output ports 9 and 10, other input / output ports (not shown), an A / D converter, a serial data transfer unit, and the like. Transfer gates (hereinafter abbreviated as TGs) are provided between the input / output ports 9 and 10 and the internal bus 7, respectively.
11 and 12 are interposed.

The input / output port 10 functions as a port for transmitting and receiving data to and from an external device during a normal operation.
It also functions as a buffer for writing and reading program data to and reading data from M5. Therefore, a data bus 16 is provided between the PROM 5 and the input / output port 10, and a TG 14 is interposed in series. The control of writing the program data to the PROM 5 and reading the data is performed by the PROM controller 1. The input / output port 9 also functions as a port for transmitting and receiving data to and from the outside during normal operation,
It functions as an operation command data input buffer to the PROM controller 1. Therefore, the PROM controller 1
A bus 15 is provided between the I / O port 9 and the I / O port 9, and a TG 13 is interposed in series. TG13 is PR
A PROM mode signal (hereinafter referred to as P
RMM) 22 and TG11,
And TG12 are the inverted signal of PRMM22 (PRM bar).
M) 23. PRMM22 is VPP
When the voltage applied to the terminal 20 becomes higher than the normal power supply voltage (5 V) (for example, 12.5 V), it becomes the active level. The TG 14 is a PRMM 22 and an output VE2 of a verify enable detection circuit (hereinafter abbreviated as VEDET) 2.
4 is controlled by a signal PWVC25 generated from VEDET2 receives the most significant 1-bit data VCD26 of the read data from the PROM 5,
Only when the VCD 26 is "1" in response to the signal VDR27 from the PROM controller 1, the output signal VE24 of the VEDET 2 is set to the active level "1". This V
The CD 26 is stored in the most significant bit cell 35 of the verify mode control information storage area 34.
The ROM cell and the PROM cell in the program storage area 33 have different characteristics.

Referring to FIG. 2, the sense amplifier 18 comprises
It is a current sense type sense amplifier. If the first PROM cell 44 selected by the first address signal 54 is in an unwritten state, the first PROM cell 44 is turned on, and a current flows through the first Nch transistor 41.
Then, a current also flows through the first Pch transistor 39, and a current also flows through the second Pch transistor 40 by the current mirror effect. As a result, the output of the third inverter 45 becomes "0" and the sense amplifier output 55 becomes "1". If the first PROM cell 44 is in the written state, the first PROM cell 44 is turned off, and the current does not flow through the first Nch transistor 41, contrary to the above. Then, the first and second Pch transistors 39,
No current flows to 40, the output of the third inverter 45 becomes "1", and the sense amplifier output 55 becomes "0".

Referring to FIG. 3, VEDET2 has a D-type flip-flop 57. Data VCD26 is latched by D-type flip-flop 57 by signal VDR27. Therefore, signal VE24 is equal to data VCD2.
When 6 is "1", the active level becomes "1". TG
The signal PWVC 25 for controlling the control signal 14 is supplied to the AND gate 56.
Accordingly, when the signals VE24 and PRMM22 are both at the active level "1", they become the active level "1".

Returning to FIG. 1, the PROM controller 1
Is a series of write control signals PWC for writing a program to the PROM 5 in response to a command supplied from the input / output port 9 via the bus 15 and the TG 13.
30 and a series of read control signals P for verification.
VC28 is generated. In this embodiment, the PC 3 is used for the program write address and the read address for verification. The PC 3 is initialized by a reset signal RS29 from the PROM controller 1, and every time a one-command write signal (not shown) is generated,
It is incremented by one.

As shown in FIG. 4, the PROM 5 has a program storage area 33 and verify mode control information VCD 26.
Storage area 35. In the present embodiment, the area 33 is from “0000H” (H represents a hexadecimal number) to “1F”.
7FH ”and the area 34 is“ 1F80 ”.
The verify mode control information VCD 26 is stored in the most significant bit 35 of the area 34.

In the PROM 5, the PROM cell in the program storage area 33 and the PROM cell in the verify mode control information storage area 34 have different characteristics. That is, the PROM cells in the program storage area 33 are likely to output only one of the stored data, regardless of whether the stored data is “0” (written state) or “1” (unwritten state). Not that
The ease of data output is the same, but in the PROM cells in the verify mode control information storage area 34, data is easier to output when "0" (written state) than when "1" (unwritten state). . In this embodiment, the characteristic difference is created by changing the gate oxide film thickness of the transistor between the PROM cell in the program storage area 33 and the PROM cell in the verify mode control information storage area. For example, the verify mode control information storage area 3
The gate oxide film thickness of the PROM cell transistor No. 4 is made thicker than that of the PROM cell transistor in the program storage area 33.

In this embodiment, each memory cell of the PROM 5 has a floating gate FG6 as shown in FIG.
0, an Nch field effect transistor MC63 having a control gate CG59, a drain D61, and a source S62.

The transistor MC63 stores data "0" by injecting electrons into the floating gate FG59 (ie, in a write state). FIG. 5B shows a VGS-IDS characteristic showing the relationship between the voltage applied to the control gate CG59 and the current flowing from the drain D61 to the source S62. The PROM cell transistor in the program storage area 33 has a first threshold voltage (VT1) 64 when not yet written, but has a second threshold voltage (VT2) 65 (after writing). 10V to 12V). This threshold voltage is a gate voltage at which the current flowing through the PROM cell transistor becomes larger than (IT) 58, and the output of the sense amplifier is "1" from (IT) 58.
Shows the current flowing through the PROM cell when it starts to change from "0" to "0". Therefore, the read voltage (VRD) 6
Assuming that 6 is an intermediate voltage between (VT1) 64 and (VT2) 65 (the normal power supply voltage is 5 V, use this), the cell transistor is turned on when writing is not performed.
Since a current of (IT) 58 or more flows and the output of the sense amplifier becomes “1” and remains off after writing, no current of (IT) 58 or more flows and the output of the sense amplifier becomes “0”. Become. However, (VRD) 66 is raised (that is, the power supply voltage is raised), and (VRD) 66 becomes (VT).
2) If it exceeds 65, even the cell transistor after writing is turned on, and the output of the sense amplifier becomes "1".

On the other hand, in the PROM cell transistor in the verify mode control information storage area 34, the gate oxide film thickness 69 between the floating gate FG60 and the control gate CG59 is larger than that of the PROM cell transistor in the program storage area 33. Therefore, when not written, it has a first threshold voltage (VT1 ') 67 higher than (VT1) 64, and after writing (VT2) 6
A second threshold voltage (VT2 ′) 68 higher than 5 is obtained. Therefore, by increasing the power supply voltage (VRD)
Even if 66 is increased, the cell transistor after writing is difficult to turn on, and the output of the sense amplifier remains "0".

Returning to FIG. 1, when the PC 3 is initialized by the signal RS29, the PROM controller 1
A signal ADRE21 is generated for CC4. Signal AD
The RE 21 causes the ACC 4 to change the initialized address “0000H” of the PC 3 to “1F80H”
Transfer to ROM5. FIG. 6 shows a configuration example of the ACC4.
As shown in FIG.
ORs 71 to 76 are provided in the first to sixth bits from the B side, and the address 77 supplied to the PROM 5 becomes “1F80H” by the signal ADRE21. Also, PROM
The controller 1 generates a read control signal PVC28 and a signal VDR27 together with the signal ADRE21, whereby the level of the signal VE24 is changed based on the control data VCD26 stored in one memory cell 35 of the PROM 5 at the address "1F80H". It is determined.

In such a configuration, the PROM 5 of the single-chip microcomputer 32 is delivered to the user in a state where the entire area has not been written. As is well known, PROM
5 is written by a PROM writer. This single chip microcomputer 32 is a PROM
When set in the writer, first the PROM writer
A VPP voltage (12.5 V) is applied to the P terminal 20. In response, the PROM controller 1 sets the PRMM 22 to the active level "1", opens the TG 13, and sets the TG 1
1, and TG12 are closed. After this, the PROM writer
A reset command is supplied to the PROM controller 1 via the input / output port 9 and the bus 15. As a result, the RS 29 is generated, the PC 3 is initialized, and the one-shot pulse signals ADRE21, VDR27, and PVC 28 are generated. As a result, “1” of the PROM 5
The control data VCD26 is "1" because the address F80H "has been read and has not been written yet.
Generates an active high level signal VE24. Also, the PWVC 25 becomes active level “1” and the TG
14 is opened, so that writing and verifying of the program become possible. The program is I / O port 1
0, and written in the PROM 5 via the bus 16, and the written program is confirmed in the verify mode. Thereafter, the content of PC3 is incremented to address "1F80H", and memory cell 35
Is written with data "0". That is, the control data VCD35 is changed from "1" to "0". As a result, processing for protecting the program is performed.

If a third party sets this single-chip microcomputer 32 in a PROM writer in order to steal a program using the verify mode,
As described above, the writer first applies the VPP voltage to the VPP terminal 20, and supplies a reset command to the PROM controller 1. As a result, the control data VCD 26 of “0” is read from the PROM 5 and the output VE 24 of the D-type flip-flop 57 becomes “0”. That is, TG1
4 remains closed, and even if a command in the verify mode is supplied to the PROM controller 1, the program written in the PROM 5 is not output to the outside.

Even if the power supply voltage to the single-chip microcomputer 32 is increased, the cell transistors in the control data storage area 34 in the PROM 5 can easily output "0" as described above. The VCD 26 does not become unwritten data "1" unless a voltage high enough to destroy the other part of the 32 is applied to the power supply. Therefore, the TG 14 remains closed, and the contents of the PROM 5 cannot be output to the outside.

The operating characteristics of a commonly used sense amplifier are designed in consideration of the operating speed and the margin for the power supply voltage. Therefore, if the operation speed can be arbitrarily determined at a power supply voltage of 5 V as in the present embodiment, the P in the verify mode control information storage area is
Even if the characteristics of the ROM cell are set to make it easier to output “0” than the PROM cell in the program storage area, the sense amplifier will operate with the unwritten PROM cell and the written PR
Normal operation can be performed for either of the OM cells. Therefore, if the power supply voltage is 5 V and the operation speed is appropriate, the unwritten data “1” of the VCD 26 becomes
There is no possibility that “0” is erroneously output. Thus, the single-chip microcomputer 32 sets the gate oxide film 69 so that the characteristics of the PROM cells in the verify mode control information storage area 34 for program protection can be easily output as "0" as compared with the PROM cells in the program storage area 33. , The protection of the program can be executed substantially completely.

In this embodiment, in order to make the PROM cell in the verify mode control information storage area 34 easy to output "0", the gate oxide film thickness 69 of the cell transistor is set.
Are thicker than the PROM cells in the program storage area 33. In addition, the verify mode control information may use an output formed by using a plurality of bits of data instead of 1-bit data as input data of the D-type flip-flop 57.

[0028]

As described above, according to the present invention, in addition to the program memory, a memory cell for storing at least one bit of control data having a characteristic different from that of the program memory is provided, and the memory cell is set to "0". "Is easy to output, so that the control data is not erroneously output, so that the program protection is substantially completely executed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram showing the sense amplifier of FIG. 1;

FIG. 3 is a circuit diagram showing VEDET2 of FIG. 1;

FIG. 4 is an address map of PROM5.

FIG. 5 is an equivalent circuit diagram (A) of a PROM cell transistor MC63, and a PROM before and after writing;
The VGS-IDS characteristic diagram of the cell transistor MC63 (B).

FIG. 6 is a circuit diagram of ACC4 in FIG. 1;

[Explanation of symbols]

1 PROM controller 2 Verify enable detection circuit (VEDET) 3 Program counter (PC) 4 Address control circuit (ACC) 5 Program memory (PROM) 6 Central processing unit (CPU) 7 Internal bus 8 Data memory (RAM) 9, 10 Input Output port 11, 12, 13, 14 Transfer gate (T
G) 15, 16, 17 Data bus 18 Sense amplifier 19 PROM output data 20 VPP terminal 21 Address control signal (ADRE) 22 PROM mode signal (PRMM) 23 PROM mode inversion signal (bar PRMM) 24 VEDET output signal (VE) 25 TG14 control signal (PWVC) 26 Program mode control signal (VCD) 27 VEDET clock signal (VDR) 28 Read control signal (PVC) 29 Reset signal (RS) 30 Write control signal (PWC) 31 Peripheral I / O unit 32 Single chip Microcomputer 33 Program storage area 34 Verify mode control information storage area 35 VCD 26 storage cell 36 Instruction bus 37 VDD 38 GND 39 First Pch transistor 40 Second Pch transistor 41 first Nch transistor 42 first inverter 43 second Nch transistor 44 first PROM cell 45 third inverter 46 fourth inverter 47 third Pch transistor 48 third Nch transistor 49 fourth Pch Transistor 50 Fourth Nch transistor 51 Second inverter 52 Second PROM cell 53 Reference voltage generation circuit 54 First address signal 55 Sense amplifier output 56 AND gate 57 D-type flip-flop 58 Sense amplifier output inversion current (IT) 59 Control gate (CG) 60 Floating gate (FG) 61 Drain (D) 62 Source (S) 63 PROM cell transistor (MC) 64 Program storage cell unwritten threshold voltage (VT1) 65 Program RAM memory cell write threshold voltage (V
T2) 66 Read voltage (VRD) 67 Control information storage cell unwritten threshold voltage (V
T1 ′) 68 Control information storage cell write threshold voltage (VT
2 ') 69 Gate oxide thickness 70 Address from PC3 71-76 OR gate 77 Address to PROM5

Claims (1)

(57) [Claims] 1. An information processing apparatus having an electrically programmable read-only memory as a program memory, wherein the gate insulating film is thicker than the program memory.
Storage means for storing control information for at least one bit different from the characteristics and the program memory by having a sense amplifier for reading the contents of said program memory said storage means, said storage means said sense amplifier is read An information processing apparatus having an electric circuit for permitting or prohibiting output of the contents of the program memory to the outside of the information processing apparatus depending on the contents.