JP2915720B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an input buffer having a high response and an output buffer having a high driving capability.

[0002]

2. Description of the Related Art Semiconductor memory devices have been increasingly integrated at higher densities and storage capacity has been increased due to recent improvements in semiconductor manufacturing technology. However, when the storage capacity is increased in this way, it takes time to read information, and it is necessary to reduce the delay time of the input / output unit in order to increase the speed of the semiconductor memory device.

FIG. 7 shows a general circuit configuration of a conventional semiconductor memory device.

An address signal input via a bus or the like is transmitted to an X decoder 2 and an Y decoder via an address input buffer 1.
The data is sent to the decoder 3 and specifies specific data on the memory cell array 4. Data on the memory cell array 4 specified by the address signal is read by the sense amplifier 5 and output to the outside via the output buffer 6.

[0005] The address signal input by the address input buffer 1 is also sent to an address input detection circuit 7. The address input detection circuit 7 is a circuit for detecting that the input address signal has changed. When the address signal changes, the address signal detection circuit 7 operates the timing signal generation circuit 8 based on this timing, and outputs the precharge signal φ1 and the output buffer. A stop signal φ2 and the like are generated. The precharge signal φ1 is
The output buffer stop signal φ2 is a signal for precharging the bit lines of the memory cell array 4 before the data is read out, and the output buffer stop signal φ2 is used for a predetermined period until the sense amplifier 5 reads out the data of the memory cell array 4. This is a signal for stopping the operation. An output enable signal for externally controlling the output buffer 6 is input to the output buffer control circuit 10 via the output enable input buffer 9. Output buffer control circuit 1
0 indicates that the output enable signal is inactive or the output buffer stop signal φ2 is active,
This is a circuit that outputs an inactive output buffer operation signal OE. The output buffer 6 outputs the data read by the sense amplifier 5 only when the output buffer operation signal OE is active, and stops the output when the output buffer operation signal OE is inactive. .

In this semiconductor memory device, when the address signal changes, as shown in FIG. 8, the output signals Ai and Aj of the address input buffer 1 change, and the X decoder 2 and the Y decoder 3 respond to the change. At the same time, the address input detection circuit 7 operates the timing signal generation circuit 8. Then, the precharge signal φ1 once becomes H level (active), and the bit lines of the memory cell array 4 are precharged. Thereafter, the sense amplifier 5 reads the designated data. Also, the output buffer stop signal φ2 becomes H level (active) for a certain period,
When the output buffer operation signal OE bar goes high (inactive), the output buffer stop signal φ2 goes low (inactive), and the output buffer operation signal OE bar goes low (active), the output buffer 6
Starts outputting the data read by the sense amplifier 5.

When the output enable signal changes from H level to L level (active), the output buffer operation signal OE goes to L level (active) as shown in FIG. Starts outputting the data read by the sense amplifier 5.

[0008]

Incidentally, the address input buffer 1 and the output enable input buffer 9 described above are used.
Is constituted by a CMOS-FET inverter circuit as shown in FIG. For example, when the external interface is at the TTL level, as shown in FIG. 11, when the input signal VIN is 0.8 V (VIL) or less, the output signal VOUT becomes H level, and the input signal VIN becomes 2.2 V (VI
H) The inversion voltage VINV is set so that the output signal VOUT becomes L level as described above.

However, in the address input buffer 1 and the output enable input buffer 9, as shown in FIG. 12, when the power supply voltage VCC increases, the inversion voltage VINV also increases, so that the noise margin (VIH-VINV) decreases. . If the internal ground potential becomes unstable while the noise margin is small, the input signal level may be erroneously determined.

For example, as shown in FIGS. 8 and 9, when the output buffer 6 starts operating, the internal ground potential GND becomes temporarily unstable due to generation of a large transient current. Thus, the output signal A of the address input buffer 1 is
When i and Aj change, the address input detecting circuit 7 erroneously detects that the change is the address signal, and the data read operation is erroneously executed as shown by the dashed line in the figure.

Therefore, in the conventional semiconductor memory device, the driving capability of the output buffer 6 is limited to reduce the instantaneous current, and the responsiveness of the address input buffer 1 is reduced.
Even if the internal ground potential GND becomes somewhat unstable, a change in the address signal is not erroneously detected. That is, the conventional semiconductor memory device has a problem that it is necessary to sacrifice the high speed in order to secure the operation stability.

The present invention has been made in view of such a situation, and temporarily reduces the responsiveness of an input buffer only during the operation of an output buffer to improve the operation stability without impairing the high-speed operation. It is an object of the present invention to provide a semiconductor memory device that can be secured.

[0013]

A semiconductor memory device according to the present invention includes an input buffer for inputting an address signal and an output enable signal, and an output buffer operation signal for a predetermined period when the address signal input to the input buffer changes. A timing control circuit that deactivates the output buffer operation signal even when the output enable signal input to the input buffer is deactivated; and a timing control circuit that deactivates the output buffer operation signal in other cases. An output buffer that externally outputs data read internally from the memory cell, an output buffer operation detection circuit that issues an operation start signal that becomes active only for a certain period when the output buffer operation signal changes from inactive to active, The operation start signal of the output buffer operation detection circuit is activated. When becomes, the response characteristic drop circuit to reduce the response characteristics of the input buffer, the power supply voltage is predetermined
And a power supply detection circuit for detecting that the voltage is equal to or less than the voltage.
The power supply detection circuit detects that the power supply voltage is lower than a predetermined voltage.
When the operation start signal is detected,
Even if the input buffer is
The operation is performed so as not to lower the response characteristics, and thereby the above object is achieved.

[0014]

[0015]

When the address signal changes while the output enable signal is in the active state, the output buffer operation signal changes from the inactive state to the active state after the data of the new address is read out internally, and the output buffer changes. Starts the output operation of this data. Also, when the output enable signal changes from the inactive state to the active state, the output buffer operation signal changes from the inactive state to the active state, and the output buffer starts operating. If an output buffer having a high driving capability is used, a large current transiently flows at the start of operation, and the internal ground potential becomes unstable.

However, the output buffer operation detection circuit activates the operation start signal only for a certain period of time when the output buffer starts operating by monitoring the output buffer operation signal changing to active. Then, while this operation start signal is active,
A response characteristic lowering circuit lowers the response characteristics of the input buffer. This increases the noise margin of the input buffer, so that even if the ground potential becomes unstable,
This eliminates the possibility of erroneous determination that the input address signal or output enable signal has changed.

Therefore, according to the semiconductor memory device of the present invention, even if the ground potential becomes unstable at the start of the operation of the output buffer, a change in the address signal or the output enable signal is not erroneously detected, so that the output buffer can be prevented. As the input buffer, a driver having a high driving capability can be used, and an input buffer having a high response characteristic can be used in normal times.

Furthermore, the provision of the power supply detection circuit allows the input buffer to secure a sufficient noise margin when the power supply voltage is lower than the predetermined voltage.
Even when the operation of the output buffer is started, the response characteristics of the input buffer are not reduced.

[0019]

The present invention will be described below with reference to examples.

FIGS. 1 to 6 show one embodiment of the present invention. FIG. 1 is a block diagram showing a configuration of a semiconductor memory device, FIG. 2 is a circuit diagram showing a configuration of an address input buffer, and FIG. FIG. 4 is a circuit diagram showing the configuration of the output enable input buffer, FIG. 4 is a time chart showing the operation when the address signal changes, FIG. 5 is a time chart showing the operation when the output enable signal changes, and FIG. FIG. 14 is a circuit diagram illustrating another configuration example of the output enable input buffer.

The same reference numerals are given to constituent members having the same functions as those of the conventional example shown in FIG.

An address signal input via a bus or the like is supplied to an X decoder 2 via an address input buffer 1 and a Y signal.
The data is sent to the decoder 3 and specifies specific data on the memory cell array 4. Data on the memory cell array 4 specified by the address signal is read by the sense amplifier 5 and output to the outside via the output buffer 6.

The address signal input by the address input buffer 1 is also sent to an address input detection circuit 7. The address input detection circuit 7 is a circuit for detecting that the input address signal has changed. When the address signal changes, the address signal detection circuit 7 operates the timing signal generation circuit 8 based on this timing, and outputs the precharge signal φ1 and the output buffer. A stop signal φ2 and the like are generated.

An output enable signal for externally controlling the output buffer 6 is input to an output buffer control circuit 10 via an output enable input buffer 9. The output buffer control circuit 10 is a logic circuit that outputs the output buffer operation signals OE and OE bar. The output buffer operation signal OE bar is output when the output enable signal is inactive or the output buffer stop signal φ2 is active. Becomes inactive. The output buffer 6
Only when the output buffer operation signal OE is active, the data read by the sense amplifier 5 is output to the outside. When the output buffer operation signal OE is inactive, the output is stopped.

The output buffer operation signal OE output from the output buffer control circuit 10 is also sent to the output enable input detection circuit 11. Output enable input detection circuit 1
Reference numeral 1 denotes a circuit for detecting that the output buffer operation signal OE has changed and becomes active. When the output buffer operation signal OE becomes active, the timing signal generation circuit 12 is operated based on this timing, and the operation starts. This will generate the signal φ0. The operation start signal φ0 is
When the output buffer operation signal OE becomes active, it is a signal that becomes active only for a certain period. The output signal of the power supply voltage detection circuit 13 that monitors whether the power supply voltage is equal to or lower than a predetermined voltage is also input to the timing signal generation circuit 12. When the power supply voltage detection circuit 13 determines that the power supply voltage is equal to or lower than the predetermined voltage, the timing signal generation circuit 12 does not activate the operation start signal φ0 even when the output buffer operation signal OE is activated. It has become.

The operation start signal φ0 output from the timing signal generation circuit 12 is input to the address input buffer 1 and the output enable input buffer 9. These address input buffer 1 and output enable input buffer 9
Means that the operation start signal φ0 is high as shown in FIGS.
When the level (active) is reached, the P-channel MOS
The FETs 1a and 9a are turned off, and the inverted voltage VIN
Reduce V temporarily. That is, by reducing the responsiveness of the address input buffer 1 and the output enable input buffer 9, the noise margin can be expanded.

In this semiconductor memory device, when the address signal changes, the output signals Ai and Aj of the address input buffer 1 change as shown in FIG.
While the decoder 2 and the Y decoder 3 operate, the address input detection circuit 7 operates the timing signal generation circuit 8. Then, the precharge signal φ1 temporarily becomes H level (active) to precharge the bit lines of the memory cell array 4, and thereafter, the precharge signal φ1
When 1 returns to the L level, the sense amplifier 5 reads the designated data. Further, the output buffer stop signal φ2 is at H level (active) for a certain period of time, and after the output buffer operation signal OE bar is at H level (inactive), when this output buffer operation signal OE bar returns to L level, The output buffer 6 starts outputting the data read by the sense amplifier 5.

When the output enable signal changes from H level to L level (active), the output buffer operation signal OE goes to L level (active) as shown in FIG. Starts outputting the data read by the sense amplifier 5.

In FIGS. 4 and 5, when the output buffer operation signal OE goes low and the output buffer 6 starts operating, the operation start signal φ0 goes high for a certain period, and the address input buffer 1 and the output enable signal are output. The response of the input buffer 9 is reduced. Therefore, even if the internal ground potential GND becomes temporarily unstable with the start of the operation of the output buffer 6, the output signals Ai and Aj of the address input buffer 1 and the output signal of the output enable input buffer 9 are erroneously obtained. It will not change.

As a result, according to the semiconductor memory device of this embodiment, even if the internal ground potential GND becomes unstable with the start of the operation of the output buffer 6, the address input buffer 1 and the output enable input buffer 9 Since the responsiveness is temporarily reduced, the operation becomes unstable even if the driving capability of the output buffer 6 is improved and the normal response characteristics of the address input buffer 1 and the output enable input buffer 9 are improved. Disappears.

However, when the power supply voltage detection circuit 13 detects that the power supply voltage is equal to or lower than the predetermined voltage, the timing signal generation circuit 12 operates even if the output buffer operation signal OE goes low. φ0 is not set to H level. If the power supply voltage is lower than the predetermined voltage,
This is because the noise margins of the address input buffer 1 and the output enable input buffer 9 become sufficiently large, so that there is no fear of malfunction even if the response is not reduced.

The address input buffer 1 and the output enable input buffer 9 shown in FIGS.
As shown in the figure, a circuit configuration in which a normal inverter circuit 101 and an inverter circuit 102 controlled by an operation start signal φ0 are connected in parallel, and when the operation start signal φ0 becomes H level, the response speed is temporarily reduced. May be reduced.

[0033]

As described above, according to the present invention,
Since the malfunction of the input buffer is prevented by lowering the response characteristic of the input buffer only at the start of the operation of the output buffer, the drive capability of the output buffer is improved, and the response characteristic of the input buffer in the normal state is improved to increase the speed of the semiconductor memory device. Will be able to do it.

[Brief description of the drawings]

FIG. 1, showing an embodiment of the present invention, is a block diagram illustrating a configuration of a semiconductor memory device.

FIG. 2, showing one embodiment of the present invention, is a circuit diagram illustrating a configuration of an address input buffer.

FIG. 3, showing an embodiment of the present invention, is a circuit diagram illustrating a configuration of an output enable input buffer.

FIG. 4 is a time chart illustrating an operation when an address signal changes according to an embodiment of the present invention.

FIG. 5, showing an embodiment of the present invention, is a time chart illustrating an operation when an output enable signal changes.

FIG. 6, showing an embodiment of the present invention, is a circuit diagram illustrating another configuration of an address input buffer and an output enable input buffer.

FIG. 7 shows a conventional example and is a block diagram showing a configuration of a semiconductor memory device.

FIG. 8 shows a conventional example, and is a time chart illustrating an operation when an address signal changes.

FIG. 9 shows a conventional example, and is a time chart illustrating an operation when an output enable signal changes.

FIG. 10 is a circuit diagram showing a general configuration of an address input buffer and an output enable input buffer.

11 is a diagram showing input / output characteristics of the address input buffer and the output enable input buffer shown in FIG.

12 is a diagram showing characteristics of an inverted voltage VINV with respect to a power supply voltage VCC of the address input buffer and the output enable input buffer shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address input buffer 6 Output buffer 10 Output buffer control circuit 12 Timing signal generation circuit 13 Power supply voltage detection circuit

Claims (1)

(57) [Claims] An input buffer for inputting an address signal and an output enable signal; an output buffer operation signal being inactive for a predetermined period when an address signal input to the input buffer changes; A timing control circuit that inactivates the output buffer operation signal even when the output enable signal is inactive, and outputs the data internally read from the memory cell to the outside when the output buffer operation signal becomes active otherwise. An output buffer that operates, an output buffer operation detection circuit that issues an operation start signal that becomes active only for a fixed period when the output buffer operation signal changes from inactive to active, and an output buffer operation detection circuit that activates the operation start signal of the output buffer operation detection circuit. Degrades the response characteristics of the input buffer A response characteristic drop circuit for a power supply detection power supply voltage is detected to be the predetermined voltage or less
A power supply voltage is equal to or lower than a predetermined voltage.
Is detected, the operation start signal is active.
However, the response characteristic degrading circuit can reduce the response characteristic of the input buffer.
A semiconductor memory device configured to operate so as not to lower the performance .