JP2911241B2 - Manufacturing method of hybrid integrated circuit - Google Patents
Manufacturing method of hybrid integrated circuitInfo
- Publication number
- JP2911241B2 JP2911241B2 JP5367391A JP5367391A JP2911241B2 JP 2911241 B2 JP2911241 B2 JP 2911241B2 JP 5367391 A JP5367391 A JP 5367391A JP 5367391 A JP5367391 A JP 5367391A JP 2911241 B2 JP2911241 B2 JP 2911241B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- lead
- manufacturing
- slit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は回路パターンの一部を外
部リードとする混成集積回路の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a hybrid integrated circuit in which a part of a circuit pattern is used as an external lead.
【0002】[0002]
【従来の技術】図13は従来の混成集積回路として、折
曲基板型の混成集積回路を断面図で例示する。同図を参
照すると、絶縁金属基板(60)(62)には表面を陽極酸化処
理した、厚さ0.5mm〜2.0mmのアルミニウムが
使用され、アルミニウム基板に形成したスリット(図示
されていない)のブリッジを切断して2枚の絶縁金属基
板(60)(62)とされる。2. Description of the Related Art FIG. 13 is a cross-sectional view illustrating a folded board type hybrid integrated circuit as a conventional hybrid integrated circuit. Referring to the figure, the insulating metal substrates (60) and (62) are made of aluminum having a thickness of 0.5 mm to 2.0 mm with anodized surfaces, and slits formed in the aluminum substrate (not shown). ) Are cut to form two insulating metal substrates (60) and (62).
【0003】絶縁層(64)の膜厚は数十μm〜数百μmで
あり、この絶縁層(64)を介して、膜厚が数十μmであっ
て、後続のホトエッチングプロセスにより導電路、各種
パッド等が所定形状に形成されて導電層(66)となる銅箔
がホットプレスで熱圧着される。従って、折曲基板型の
混成集積回路の絶縁層(64)にはフレキシブルであって、
かつ接着性を有するポリイミド樹脂が使用される。The thickness of the insulating layer (64) is several tens μm to several hundreds of μm. Through this insulating layer (64), the thickness of the insulating layer (64) is several tens μm, and the conductive path is formed by a subsequent photo-etching process. Then, a copper foil having various pads and the like formed in a predetermined shape and serving as a conductive layer (66) is thermocompression-bonded by a hot press. Therefore, the insulating layer (64) of the bent board type hybrid integrated circuit is flexible,
A polyimide resin having adhesiveness is used.
【0004】前記銅箔はアルミニウム基板の分割の前に
ホトエッチングされ、それぞれの絶縁金属基板(60)(62)
上に半導体素子を搭載するためのダイボンドパッド、外
部リード(70)を半田固着するためのパッド等の各種のパ
ッドおよび導電路が所定の形状に形成されて導電層(66)
を構成する。また、アルミニウム基板のスリット部には
それぞれの絶縁金属基板(60)(62)上の回路を接続する導
電路が形成される。この導電層(66)の回路パターンの線
幅は数十μm〜数百μmである。[0004] The copper foil is photo-etched before dividing the aluminum substrate, and the respective insulated metal substrates (60), (62)
Various pads and conductive paths such as a die bond pad for mounting a semiconductor element thereon, a pad for fixing an external lead (70) by soldering, and a conductive path are formed in a predetermined shape and a conductive layer (66).
Is configured. Further, conductive paths for connecting circuits on the respective insulating metal substrates (60) and (62) are formed in the slit portions of the aluminum substrate. The line width of the circuit pattern of the conductive layer (66) is several tens μm to several hundred μm.
【0005】外部リード(70)はフレーム形状で導電層(6
6)のパッドに半田固着され、混成集積回路をモールドし
た後に、あるいはケースに封入した後にフレームを切断
して個々の外部リード(70)とされる。The external leads (70) are frame-shaped and have conductive layers (6).
After the hybrid integrated circuit is molded or encapsulated in a case, the frame is cut off to form individual external leads (70) by soldering to the pad of 6).
【0006】[0006]
【発明が解決しようとする課題】上記した従来の混成集
積回路の外部リード(70)の固着作業は、外部リード端子
(70)とパッドとの相対位置および角度の全てを一致させ
なければならないため、極めて煩雑である。また、この
外部リード(70)は、固着強度維持のため導電層(66)のパ
ッドに半田固着される部分が他の部分に比較して大サイ
ズにされており、そのために、さらに大きなマージンを
必要として、他の回路パターンがファイン化されてきて
いるにもかかわらず、導電層(66)のパッド面積を低減で
きない問題を有している。The above-mentioned operation of fixing the external lead (70) of the conventional hybrid integrated circuit is performed by using an external lead terminal.
Since all the relative positions and angles of (70) and the pad must be matched, it is extremely complicated. Further, in the external lead (70), a portion to be solder-fixed to the pad of the conductive layer (66) is made larger in size than other portions in order to maintain the fixing strength, so that a larger margin is provided. As a necessity, there is a problem that the pad area of the conductive layer (66) cannot be reduced despite other circuit patterns being finer.
【0007】さらには、絶縁層(64)としてのポリイミド
樹脂の銅箔との接着性能が完全でないため、フレームの
残留応力等により外部リード(70)固着直後にそのパッド
の剥離のおそれがある。このため、折曲基板型の混成集
積回路の絶縁層(64)にはポリイミド樹脂の他、ポリイミ
ド樹脂と銅箔間に接着性が良好なエポキシ樹脂を使用し
なければならない問題を有している。さらにまた、折曲
基板型の混成集積回路では、外部リード(70)が固着され
ない側の導電層(66)に形成された回路が外部リード(70)
への接続を必要とする場合、そのための導電路を導電層
(66)を縦断するように引き回さねばならず、有効基板面
積が低下する問題も有している。Furthermore, since the bonding performance of the polyimide resin as the insulating layer (64) to the copper foil is not perfect, the pad may be peeled off immediately after the external lead (70) is fixed due to residual stress of the frame or the like. Therefore, the insulating layer (64) of the bent board type hybrid integrated circuit has a problem that, in addition to the polyimide resin, an epoxy resin having good adhesiveness between the polyimide resin and the copper foil must be used. . Furthermore, in the bent board type hybrid integrated circuit, the circuit formed on the conductive layer (66) on the side to which the external lead (70) is not fixed is connected to the external lead (70).
If a connection to the
(66) must be routed in a longitudinal direction, and there is a problem that the effective substrate area is reduced.
【0008】[0008]
【課題を解決するための手段】本発明は、リード状にパ
ターン形成された導電路の絶縁樹脂層をエキシマレーザ
の選択照射により除去して、この導電路を外部リードと
することを主要な特徴とする。The main feature of the present invention is to remove an insulating resin layer of a conductive path patterned in a lead shape by selective irradiation of an excimer laser, and to use the conductive path as an external lead. And
【0009】[0009]
【作用】リード状導電路下の絶縁樹脂層をエキシマレー
ザにより除去するため、絶縁樹脂層の除去が完全であ
り、リード状導電路の破損、変形がない。また、外部リ
ード形状がシンプルであるため小型、安価な混成集積回
路が得られると共に外部リードの他の基板への半田固着
を混成集積回路の直近で行うことができて実装効率が向
上する。Since the insulating resin layer under the lead-shaped conductive path is removed by an excimer laser, the removal of the insulating resin layer is complete and the lead-shaped conductive path is not damaged or deformed. In addition, since the external leads have a simple shape, a small-sized and inexpensive hybrid integrated circuit can be obtained, and soldering of the external leads to another substrate can be performed in close proximity to the hybrid integrated circuit, so that mounting efficiency is improved.
【0010】[0010]
【実施例】以下、図1乃至図8を参照して本発明の一実
施例を説明する。図1および図2を参照すると、絶縁金
属基板(10)には放熱特性および加工性を考慮して0.5
mm〜2.0mm厚のアルミニウム(12)が使用され、表
面を陽極酸化して3μm〜30μm厚の酸化膜(14)が形
成される。この絶縁金属基板(10)は数10単位の混成集
積回路の大きさを有し、単位混成集積回路の境界部に絶
縁金属基板(10)の厚さの少なくとも倍幅のスリット(16)
がパンチング形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. Referring to FIGS. 1 and 2, the insulating metal substrate (10) has a thickness of 0.5 in consideration of heat radiation characteristics and workability.
Aluminum (12) having a thickness of 2.0 mm to 2.0 mm is used, and the surface is anodized to form an oxide film (14) having a thickness of 3 μm to 30 μm. The insulating metal substrate (10) has a size of several tens of units of the hybrid integrated circuit, and a slit (16) having a width at least twice as large as the thickness of the insulating metal substrate (10) is formed at the boundary of the unit hybrid integrated circuit.
Are formed by punching.
【0011】図2を参照すると、銅箔(20)は約50μm
の膜厚であり、その表面に流動性に富むAステージのエ
ポキシ樹脂をローラコータを使用して塗布し、さらにこ
のエポキシ樹脂を半硬化してBステージとした接着剤層
(22)が形成されている。なお、銅箔(20)の膜厚は混成集
積回路のサイズ、コスト、パターンルールを考慮して適
宜変更される。Referring to FIG. 2, the copper foil (20) has a thickness of about 50 μm.
An A-stage epoxy resin having a high fluidity is applied to the surface thereof using a roller coater, and the epoxy resin is semi-cured to form a B-stage adhesive layer.
(22) is formed. The thickness of the copper foil (20) is appropriately changed in consideration of the size, cost, and pattern rules of the hybrid integrated circuit.
【0012】この工程では絶縁金属基板(10)上に接着剤
層(22)を形成した銅箔(20)がホットプレスを使用して、
温度130℃〜150℃、単位平方cm当り10Kg〜
50Kgの圧力で熱圧着される。接着剤層(22)はこの熱
圧着工程により完全硬化して膜厚が約20μmとなる。
そして、接着剤層(22)により熱圧着された絶縁金属基板
(10)と銅箔(20)を5時間〜10時間の間、温度130℃
〜150℃に保って、接着剤層(22)をキュアした後、次
の工程に送られる。In this step, a copper foil (20) having an adhesive layer (22) formed on an insulating metal substrate (10) is hot-pressed,
Temperature 130 ° C-150 ° C, 10Kg / cm2
Thermocompression bonding is performed at a pressure of 50 kg. The adhesive layer (22) is completely cured by this thermocompression bonding step to have a film thickness of about 20 μm.
Then, the insulating metal substrate thermocompressed by the adhesive layer (22)
(10) and copper foil (20) for 5 hours to 10 hours at a temperature of 130 ° C.
After the adhesive layer (22) is cured while being kept at ~ 150 ° C, it is sent to the next step.
【0013】図3およびそのA−A線断面図である図4
を参照すると、ローラコータを使用して塗布したホトレ
ジスト(図示されていない)を回路パターンに従って選
択露光してマスクを形成し、このホトレジストをマスク
として、銅箔(20)を塩化第2鉄溶液で選択エッチングし
て銅箔(20)に図3および図4に例示するリード状導電路
(24)、ダイボンドパッド(26)、ワイアボンディングパッ
ド(28)等の全ての回路パターンがスリット(16)で分割さ
れる単位混成集積回路毎に形成される。この回路パター
ン内の導電路の線幅は通常、数十μm〜数百μmであ
り、スリット(16)上部に形成するリード状導電路(24)は
数百μm以上の線幅に形成される。FIG. 3 and FIG. 4 which is a sectional view taken along line AA of FIG.
Referring to, a photoresist (not shown) applied using a roller coater is selectively exposed in accordance with a circuit pattern to form a mask, and the copper foil (20) is selected with a ferric chloride solution using the photoresist as a mask. Etched to form a lead-like conductive path as shown in FIGS. 3 and 4 on a copper foil (20).
(24), all the circuit patterns such as the die bond pad (26) and the wire bonding pad (28) are formed for each unit hybrid integrated circuit divided by the slit (16). The line width of the conductive path in this circuit pattern is usually several tens μm to several hundred μm, and the lead-shaped conductive path (24) formed above the slit (16) is formed with a line width of several hundred μm or more. .
【0014】図5を参照すると、絶縁金属基板(10)のス
リット(16)よりKrF、XeClあるいはArFをレー
ザガスとするエキシマレーザ(矢印で示されている)を
選択照射して、絶縁金属基板(10)のスリット(16)により
露出される接着剤層(22)が、絶縁部(30)を残して除去さ
れる。Referring to FIG. 5, an excimer laser (indicated by an arrow) using KrF, XeCl, or ArF as a laser gas is selectively irradiated from a slit (16) of the insulating metal substrate (10) to thereby irradiate the insulating metal substrate ( The adhesive layer (22) exposed by the slit (16) of (10) is removed leaving the insulating portion (30).
【0015】ここで図12を参照してエキシマレーザ加
工を説明する。この図12はログスケールの横軸をエキ
シマレーザのエネルギ密度(Fluence mJ)と
して、縦軸にポリマと金属それぞれのレーザ1ショット
当りの加工量(Etch Depth μm)をプロッ
トしたものである。The excimer laser processing will now be described with reference to FIG. In FIG. 12, the abscissa of the log scale is the energy density of the excimer laser (Fluence mJ), and the ordinate is the processing amount (Etch Depth μm) of each polymer and metal per laser shot.
【0016】従来から産業界で使用されているYAG、
CO2等の赤外レーザ加工においてはレーザビームをレ
ンズで集光し、その焦点近傍の高エネルギ密度領域にあ
る加工対象を溶融、蒸発する熱的なメカニズムが利用さ
れている。従って、赤外レーザ加工は加工対象の材質を
選択しない特性を有すると共に加工部周辺への連続的な
熱影響が避けられない性質を有している。YAG, which has been conventionally used in the industry,
In infrared laser processing such as CO2, a thermal mechanism is used in which a laser beam is condensed by a lens, and a processing object in a high energy density region near the focal point is melted and evaporated. Therefore, the infrared laser processing has a characteristic that the material to be processed is not selected, and also has a property that continuous thermal influence on the periphery of the processing portion is unavoidable.
【0017】これに対して、エキシマレーザ加工ではエ
キシマレーザは加工対象にデホーカス状態で照射され、
エキシマレーザの光子が分子化学的に加工対象表面の分
子結合を切断するアブレーションプロセスにより加工が
行われる。従って、エキシマレーザ加工は非熱的加工で
あり、加工対象が分子結合であるか金属結合であるかに
よって加工が開始されるエネルギ密度(スレショール
ド)が大きく異なる。このスレショールドは全てのポリ
マにおいて1平方cm当り約100mJ、金属では約1
Jである。また、エキシマレーザ加工は分子化学的に加
工が行われるため除去物質による加工部周辺の熱影響、
汚染がない特質を有している。On the other hand, in excimer laser processing, an excimer laser is irradiated to a processing object in a defocused state,
Processing is performed by an ablation process in which photons of an excimer laser molecularly break molecular bonds on the surface to be processed. Therefore, the excimer laser processing is a non-thermal processing, and the energy density (threshold) at which the processing is started differs greatly depending on whether the processing target is a molecular bond or a metal bond. This threshold is about 100 mJ / cm 2 for all polymers and about 1 for metals.
J. In addition, excimer laser processing is performed by molecular chemistry.
It has the characteristics of no pollution.
【0018】再び図5を参照すると、絶縁金属基板(10)
のスリット(16)にポリマのスレショールド以上であり、
金属のスレショールド以下である単位面積当り100m
J〜1Jのエネルギ密度のエキシマレーザを照射する
と、スリット(16)により露出される接着剤層(22)の一部
が除去され、スリット(16)内にリード状導電路(24)のみ
が残される。なお、実施例の約20μm厚の接着剤層(2
2)は1平方cm当り500mJのエキシマレーザの10
0ショットによって完全に除去される。Referring again to FIG. 5, the insulating metal substrate (10)
The slit (16) is above the polymer threshold,
100m per unit area below the metal threshold
When an excimer laser having an energy density of J to 1J is irradiated, a part of the adhesive layer (22) exposed by the slit (16) is removed, leaving only the lead-shaped conductive path (24) in the slit (16). It is. Note that the adhesive layer (2
2) is 10 excimer lasers of 500 mJ per square cm.
Completely removed by 0 shots.
【0019】図6およびそのB−B線断面図である図7
を参照すると、ここで、後続のダイボンド工程、ワイア
ボンド工程での位置精度を向上させるために、絶縁金属
基板(10)に形成したスリット(16)部をパンチング加工し
て、より高精度の形状の単位混成集積回路に分割され
る。なお、本実施例ではリード状導電路(24)の一端を自
由端としたが、回路パターン形成時にリード状導電路(2
4)の一端を相互連絡するブリッジを形成しておくことに
より、あるいは接着剤層(22)のエキシマレーザ加工時に
リード状導電路(24)の一端に接着剤層(22)をブリッジ状
に残すことによってリード状導電路(24)の変形が防止さ
れる。FIG. 6 and FIG. 7 which is a sectional view taken along the line BB of FIG.
Here, here, in order to improve the positional accuracy in the subsequent die bonding process and the wire bonding process, the slit (16) formed in the insulating metal substrate (10) is punched to form a more accurate shape. It is divided into unit hybrid integrated circuits. In this embodiment, one end of the lead-shaped conductive path (24) is a free end.
By forming a bridge interconnecting one end of 4), or leaving the adhesive layer (22) in a bridge shape at one end of the lead-shaped conductive path (24) during excimer laser processing of the adhesive layer (22). This prevents the lead-shaped conductive path (24) from being deformed.
【0020】図8を参照すると、ダイボンドパッド(26)
に集積回路素子(32)を銀ペースト等のロウ材を使用して
固着し、さらに図示しないチップ抵抗、チップコンデン
サ等の異型部品を所定のパッドに半田固着した後、前記
集積回路素子(32)の電極とワイアボンディングパッド(2
8)をボンディングワイア(34)で接続して図示の混成集積
回路が完成する。Referring to FIG. 8, the die bond pad (26)
After fixing the integrated circuit element (32) using a brazing material such as silver paste, and further fixing an odd-shaped component such as a chip resistor (not shown) and a chip capacitor to predetermined pads by soldering, the integrated circuit element (32) Electrodes and wire bonding pads (2
8) are connected by a bonding wire (34) to complete the illustrated hybrid integrated circuit.
【0021】ここで、図9を参照して本発明による混成
集積回路のアセンブリを説明する。本発明による混成集
積回路は絶縁金属基板(10)をマザー基板(40)の所定位置
に接着等により固着した後、リード状導電路(24)を外部
リードとして、マザー基板(40)の所定のパッド(42)に接
続して使用される。このとき、先の接着剤層(22)のエキ
シマレーザ加工工程において残された絶縁部(30)がリー
ド状導電路(24)と絶縁金属基板(10)との接触を防止す
る。The assembly of the hybrid integrated circuit according to the present invention will now be described with reference to FIG. In the hybrid integrated circuit according to the present invention, after the insulated metal substrate (10) is fixed to a predetermined position of the mother substrate (40) by bonding or the like, the lead-like conductive path (24) is used as an external lead, and the predetermined position of the mother substrate (40) is Used by connecting to the pad (42). At this time, the insulating portion (30) left in the excimer laser processing step of the adhesive layer (22) prevents contact between the lead-shaped conductive path (24) and the insulating metal substrate (10).
【0022】次に、図10および図11を参照して本発
明の他の実施例を説明する。先の実施例では、図1のス
リット(16)により分割される各領域に同一の混成集積回
路パターンが形成されたが、図10に示すように、その
2つの領域を単位として混成集積回路パターン(50)(52)
を分割形成することが可能である。本実施例では混成集
積回路パターン(50)(52)面の反対面を対向させ、リード
状導電路(54)を折り曲げて外部リードとして使用され
る。本実施例によれば、外部リードが2つの混成集積回
路パターン(50)(52)の中間に形成されるため、外部リー
ドを2つの混成集積回路パターンの何れかの端部に形成
する従来の混成集積回路に比較して、外部リードまでの
導電路の引き回しが短くなる利点を有する。Next, another embodiment of the present invention will be described with reference to FIGS. In the previous embodiment, the same hybrid integrated circuit pattern was formed in each area divided by the slit (16) in FIG. 1. However, as shown in FIG. (50) (52)
Can be divided and formed. In this embodiment, the surfaces opposite to the surfaces of the hybrid integrated circuit patterns (50) and (52) are opposed to each other, and the lead-like conductive paths (54) are bent and used as external leads. According to the present embodiment, since the external leads are formed in the middle of the two hybrid integrated circuit patterns (50) and (52), the conventional external leads are formed at either end of the two hybrid integrated circuit patterns. Compared with the hybrid integrated circuit, there is an advantage that the routing of the conductive path to the external lead is shortened.
【0023】以上、本発明を説明したが、本発明は上記
実施例に限定されるものではなく、例えば集積回路素子
等の固着工程と単位混成集積回路への分割工程の順序は
自由である。また、単一の混成集積回路毎に本発明の各
工程を実施することも可能であり、その場合にはスリッ
ト(16)に代えて、絶縁金属基板(10)の4辺に切り欠きを
設けることができる。Although the present invention has been described above, the present invention is not limited to the above-described embodiment. For example, the order of the step of fixing an integrated circuit element or the like and the step of dividing it into unit hybrid integrated circuits are arbitrary. It is also possible to carry out each step of the present invention for each single hybrid integrated circuit. In this case, notches are provided on four sides of the insulating metal substrate (10) instead of the slit (16). be able to.
【0024】[0024]
【発明の効果】以上述べたように本発明によれば、エキ
シマレーザ加工を行うため、化学エッチングが困難なエ
ポキシ樹脂が絶縁樹脂層として使用される場合でもリー
ド状導電路の絶縁樹脂層を完全、清浄に除去して外部リ
ードを形成することができる。また、外部リード構造が
シンプルであるため小型、安価な混成集積回路が得られ
ると共に外部リードの他の基板への半田固着を混成集積
回路の直近で行うことができて実装効率が向上する。As described above, according to the present invention, since the excimer laser processing is performed, even when an epoxy resin which is difficult to chemically etch is used as the insulating resin layer, the insulating resin layer of the lead-shaped conductive path is completely formed. , And can be removed cleanly to form external leads. In addition, since the external lead structure is simple, a small-sized and inexpensive hybrid integrated circuit can be obtained, and soldering of the external leads to another substrate can be performed in close proximity to the hybrid integrated circuit, so that mounting efficiency is improved.
【0025】[0025]
【図1】本発明の一実施例の製造工程を説明する図であ
って、絶縁金属基板の平面図。FIG. 1 is a diagram illustrating a manufacturing process according to an embodiment of the present invention, and is a plan view of an insulated metal substrate.
【図2】本発明の製造工程の断面図。FIG. 2 is a sectional view of a manufacturing process according to the present invention.
【図3】本発明の製造工程の平面図。FIG. 3 is a plan view of the manufacturing process of the present invention.
【図4】本発明の製造工程を説明する図であって、図3
のA−A線断面図。FIG. 4 is a view for explaining a manufacturing process of the present invention, and FIG.
Sectional view on the AA line of FIG.
【図5】本発明の製造工程の断面図。FIG. 5 is a sectional view of the manufacturing process of the present invention.
【図6】本発明の製造工程の平面図。FIG. 6 is a plan view of the manufacturing process of the present invention.
【図7】本発明の製造工程を説明する図であって、図6
のB−B線断面図。FIG. 7 is a view for explaining the manufacturing process of the present invention, and FIG.
BB sectional drawing of FIG.
【図8】本発明の製造工程の断面図。FIG. 8 is a sectional view of the manufacturing process of the present invention.
【図9】本発明の製造工程の断面図。FIG. 9 is a cross-sectional view of the manufacturing process of the present invention.
【図10】本発明の他の実施例の製造工程の平面図。FIG. 10 is a plan view of a manufacturing process according to another embodiment of the present invention.
【図11】本発明の他の実施例の製造工程の断面図。FIG. 11 is a sectional view of a manufacturing process according to another embodiment of the present invention.
【図12】エキシマレーザの加工特性を説明する特性
図。FIG. 12 is a characteristic diagram illustrating processing characteristics of an excimer laser.
【図13】従来の混成集積回路の断面図。FIG. 13 is a sectional view of a conventional hybrid integrated circuit.
10 絶縁金属基板 22 接着剤層 24 リード状導電路 26 ダイボンドパッド 30 絶縁部 32 集積回路素子 34 ボンディングワイア DESCRIPTION OF SYMBOLS 10 Insulated metal substrate 22 Adhesive layer 24 Lead-shaped conductive path 26 Die bond pad 30 Insulating part 32 Integrated circuit element 34 Bonding wire
Claims (5)
を有し、スリット上部にリード状導電路を有する基板を
用意し、 前記基板の前記スリットに位置する前記絶縁層をレーザ
加工して前記リード下の絶縁層を除去する事を特徴とす
る混成集積回路の製造方法。 1. A copper foil pattern attached via an insulating layer
Having a lead-shaped conductive path above the slit.
Prepare and laser the insulating layer located in the slit of the substrate
Processing to remove the insulating layer under the lead.
Manufacturing method of a hybrid integrated circuit.
ット部に位置する前記絶縁層が前記金属基板より突出す
るように前記リード状導電路下の前記絶縁層を除去する
ことを特徴とする請求項1の混成集積回路の製造方法。Wherein said substrate is a metal substrate, removing the insulating layer of the lower lead-shaped conductive path such that the insulating layer positioned on the ground <br/> Tsu isolation portion is projected from the metal substrate 2. The method for manufacturing a hybrid integrated circuit according to claim 1, wherein:
て単位混成集積回路を形成することを特徴とする請求項
1の混成集積回路の製造方法。3. The method for manufacturing a hybrid integrated circuit according to claim 1, wherein said substrate is divided at said slit to form a unit hybrid integrated circuit.
記リード状導電路を形成することを特徴とする請求項3
の混成集積回路の製造方法。4. Before 2 or more sides of the unit hybrid integrated circuits
Claim 3, characterized in that to form a serial lead-shaped conductor path
Of manufacturing a hybrid integrated circuit.
り合う2つの領域に前記回路パターンを分割形成するこ
とを特徴とする請求項1記載の混成集積回路の製造方
法。 5. The method of manufacturing a hybrid integrated circuit according to claim 1, wherein said circuit pattern is divided and formed in two adjacent regions of the copper foil divided by said slit.
Law.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5367391A JP2911241B2 (en) | 1991-02-27 | 1991-02-27 | Manufacturing method of hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5367391A JP2911241B2 (en) | 1991-02-27 | 1991-02-27 | Manufacturing method of hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04273157A JPH04273157A (en) | 1992-09-29 |
JP2911241B2 true JP2911241B2 (en) | 1999-06-23 |
Family
ID=12949349
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5367391A Expired - Fee Related JP2911241B2 (en) | 1991-02-27 | 1991-02-27 | Manufacturing method of hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2911241B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004146526A (en) | 2002-10-23 | 2004-05-20 | Tomoegawa Paper Co Ltd | Electronic member and method of manufacturing the same, and semiconductor device |
-
1991
- 1991-02-27 JP JP5367391A patent/JP2911241B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH04273157A (en) | 1992-09-29 |
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