JP2910458B2 - Field effect transistor - Google Patents

Field effect transistor

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Publication number
JP2910458B2
JP2910458B2 JP30105792A JP30105792A JP2910458B2 JP 2910458 B2 JP2910458 B2 JP 2910458B2 JP 30105792 A JP30105792 A JP 30105792A JP 30105792 A JP30105792 A JP 30105792A JP 2910458 B2 JP2910458 B2 JP 2910458B2
Authority
JP
Japan
Prior art keywords
gate
mosfet
threshold voltage
effect transistor
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP30105792A
Other languages
Japanese (ja)
Other versions
JPH06151844A (en
Inventor
直道 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP30105792A priority Critical patent/JP2910458B2/en
Publication of JPH06151844A publication Critical patent/JPH06151844A/en
Application granted granted Critical
Publication of JP2910458B2 publication Critical patent/JP2910458B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は個別半導体素子のMOS
型電界効果トランジスタに関し、特に、実質的に低ゲー
ト閾値電圧をもつMOS型電界効果トランジスタに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an individual semiconductor device MOS.
Field-effect transistor, and more particularly, to a MOS field-effect transistor having a substantially low gate threshold voltage.

【0002】[0002]

【従来の技術】従来の個別半導体素子としてのMOS型
電界効果トラジスタ(以下MOSFETとする)では、
MOSFET自体のゲート電極に外部端子を接続してゲ
ート電圧を入力し上記MOSFETを駆動する。このM
OSFETの駆動能力は上記MOSFETが有するゲー
ト閾値電圧に依存している。すなわちゲート閾値電圧が
大きいとMOSFETの駆動能力が下り、MOSFET
の性能を十分活用できない。したがってゲート閾値電圧
の低いMOSFETを実現する必要があり、このゲート
閾値電圧を低くするためにMOSFETの製造上のプロ
セスパラメータ等の工夫がなされている。たとえば上記
MOSFETのゲート酸化膜の膜厚を薄くしたり、チャ
ンネル部の基板不純物濃度を低く抑えるなどの製造プロ
セスによりゲート閾値電圧の低い駆動能力のあるMOS
FETが得られる。
2. Description of the Related Art In a conventional MOS type field effect transistor (hereinafter referred to as a MOSFET) as an individual semiconductor element,
An external terminal is connected to the gate electrode of the MOSFET itself to input a gate voltage to drive the MOSFET. This M
The driving capability of the OSFET depends on the gate threshold voltage of the MOSFET. In other words, if the gate threshold voltage is large, the driving capability of the MOSFET decreases,
Cannot fully utilize the performance of Therefore, it is necessary to realize a MOSFET having a low gate threshold voltage, and in order to reduce the gate threshold voltage, various measures such as process parameters in manufacturing the MOSFET have been devised. For example, a MOS transistor having a low gate threshold voltage can be driven by a manufacturing process such as reducing the thickness of the gate oxide film of the MOSFET or suppressing the substrate impurity concentration in the channel portion.
An FET is obtained.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
個別半導体素子としてのMOSFETでは、ゲート閾値
電圧を低くすると、ゲート閾値電圧自体の負の温度係数
のため、高温で十分なノイズマージンが確保できなくな
るため、動作温度範囲が狭く制限されるという問題があ
った。
However, in a conventional MOSFET as a discrete semiconductor device, if the gate threshold voltage is lowered, a sufficient noise margin cannot be secured at high temperatures due to the negative temperature coefficient of the gate threshold voltage itself. Therefore, there is a problem that the operating temperature range is narrowly limited.

【0004】図2(b)に、現在得られるMOSFET
のゲート閾値電圧VGS(th)の温度特性の一例を示す。V
GS(th)は25℃で1.0Vであり、その温度係数kが−
5mV/℃の場合のノイズマージンを0.5Vに確保す
るためには、最高チャネル温度Tchmaxを125℃
以下に動作温度範囲が制限される。更に、VGS(th)の製
造ばらつきを考慮すると、実用動作温度範囲は100℃
以下に制限しなくてはならない。この動作温度は上記最
高チャンネル温度Tchmaxのスペック150℃を満
足しない。
FIG. 2 (b) shows a currently obtained MOSFET.
An example of a temperature characteristic of the gate threshold voltage V GS (th) of FIG. V
GS (th) is 1.0 V at 25 ° C., and its temperature coefficient k is −
In order to secure a noise margin of 0.5 V at 5 mV / ° C., the maximum channel temperature Tchmax is set to 125 ° C.
The operating temperature range is limited below. Further, considering the manufacturing variation of V GS (th) , the practical operating temperature range is 100 ° C.
Must be restricted to: This operating temperature does not satisfy the above-mentioned maximum channel temperature Tchmax specification of 150 ° C.

【0005】一方、MOSFETのゲート部と外部ゲー
ト端子との間に、ゲートサージ電圧保護回路を接続する
MOSFETでは、このMOSFETのゲート閾値電圧
を能動的に変化させる機能を有しておらず、MOSFE
Tの駆動能力の低下を防止できなかった。
On the other hand, a MOSFET connecting a gate surge voltage protection circuit between a gate portion of the MOSFET and an external gate terminal does not have a function of actively changing the gate threshold voltage of the MOSFET, and has a MOSFET.
The drive capability of T could not be prevented from lowering.

【0006】本発明の目的は、実質的に閾値電圧の低い
駆動能力のあるMOSFETを提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a MOSFET having a driving capability with a substantially low threshold voltage.

【0007】[0007]

【課題を解決するための手段】本発明の電界効果トラン
ジスタは、ツェナーダイオードの電圧により順バイアス
され直列接続されたダイオードと前記ダイオードに並列
接続された抵抗とからなるゲート閾値電圧補償用回路を
ゲート端子と外部ゲート端子との間に接続する構成を備
える。
The field effect transistor of the present invention has a gate threshold voltage compensating circuit comprising a diode connected in series, which is forward-biased by the voltage of a Zener diode, and a resistor connected in parallel with the diode. A configuration is provided for connection between the terminal and an external gate terminal.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0009】図1は本発明の電界効果トランジスタの第
1の実施例である。この実施例の基本構成を示す図1
(d)を参照すると、MOSFET1は、MOSFET
1のゲート3と外端ゲート端子2との間に補償回路12
を配置する構成である。
FIG. 1 shows a first embodiment of a field effect transistor according to the present invention. FIG. 1 shows a basic configuration of this embodiment.
Referring to (d), MOSFET 1 is a MOSFET
1 between the gate 3 and the outer end gate terminal 2
Are arranged.

【0010】図1(a)に、補償回路を含めたMOSF
ETの構成を示す。すなわち、MOSFET1のゲート
3と外部ゲート端子2との間に、サブ端子4を介して外
部よりバイアスされたツェナーダイオード8により、順
方向にバイアスされた2本の直列ダイオード6及び抵抗
R15を接続する。
FIG. 1A shows a MOSF including a compensation circuit.
2 shows the configuration of ET. In other words, two series-biased forward-biased diodes 6 and a resistor R15 are connected between the gate 3 of the MOSFET 1 and the external gate terminal 2 by a Zener diode 8 externally biased via the sub-terminal 4. .

【0011】次に、本発明の第1の実施例のMOSFE
Tの特性値について説明する。
Next, the MOSFE according to the first embodiment of the present invention will be described.
The characteristic value of T will be described.

【0012】MOSFET固有のゲート閾値電圧はTh
=25℃でVGS(th)=2.4V,その温度係数はk
VG(th)=−5mV/℃、ツェナーダイオード8はMOS
FETの酸化膜上にポリシリコンで構成し、そのツェナ
電圧Vzは3Vである。
The gate threshold voltage inherent to the MOSFET is Th
= 25 ° C., V GS (th) = 2.4 V, and its temperature coefficient is k
VG (th) = − 5 mV / ° C., Zener diode 8 is MOS
The FET is made of polysilicon on an oxide film, and its zener voltage Vz is 3V.

【0013】2本直列のダイオード6は、MOSFET
の酸化膜上にポリシリコンで構成しその準電圧は25℃
で2・VF =1.4Vであり、その温度係数2・kVF
−2mV/℃である。
The two series diodes 6 are MOSFETs
Composed of polysilicon on an oxide film having a reference voltage of 25 ° C.
In a 2 · V F = 1.4V, its temperature coefficient 2 · k VF =
−2 mV / ° C.

【0014】ゲート3と外部ゲート端子2との間に接続
される抵抗(R1)5はMOSFETの酸化膜上に付け
たポリシリコン抵抗で構成し、その抵抗値は、1〜10
0Ωとする。
A resistor (R1) 5 connected between the gate 3 and the external gate terminal 2 is composed of a polysilicon resistor provided on an oxide film of a MOSFET, and has a resistance value of 1 to 10.
It is assumed to be 0Ω.

【0015】また、抵抗(R2)7は、同じくポリシリ
コン抵抗で構成するが、ツェナー電圧Vzで、ダイオー
ド6を順バイアスするため(1)式を満す抵抗値とす
る。すなわち R2<R1(Vz−2・VF )/2・VF …(1) 上述の説明のとおり、この補償回路12を有すること
で、図1(b)にMOSFETのゲート閾値電圧V
GS(th)の特性を、図1(c)に示す実効ゲート閾値電圧
GS(th)effの温度特性に改善できる。
The resistor (R2) 7 is also made of a polysilicon resistor, but has a resistance value that satisfies the expression (1) in order to forward bias the diode 6 with the Zener voltage Vz. That is, R2 <R1 (Vz−2 · V F ) / 2 · V F (1) As described above, the provision of the compensation circuit 12 allows the gate threshold voltage V of the MOSFET to be shown in FIG.
The characteristics of the GS (th), can be improved in temperature characteristics of the effective gate threshold voltage V GS (th) eff shown in Figure 1 (c).

【0016】次に、本発明の第2実施例を示す図3を参
照すると、MOSFET1のゲート閾値電圧補償回路3
0は、ゲート外部端子32とソース端子Sとの間に並列
に配置した4組以上のLED11と光結合で光励起され
る直列接続されたフォトダイオード10により、バイア
スされたツェナーダイオード38のツェナー電圧により
順バイアスされる2本直列のダイオード36及び抵抗3
5をゲート外部端子32とゲート33との間に配置する
構成とする。フォトダイオードアレイ10ツェダーダイ
オード38、ダイオード36ならびに抵抗35,37お
よび39はMOSFETの酸化膜上にポリシリコンで構
成する。
Next, referring to FIG. 3 showing a second embodiment of the present invention, the gate threshold voltage compensating circuit 3 of the MOSFET 1 will be described.
0 is caused by a Zener voltage of a Zener diode 38 biased by a series-connected photodiode 10 optically excited by optical coupling with four or more sets of LEDs 11 arranged in parallel between a gate external terminal 32 and a source terminal S. Forward-biased two-series diode 36 and resistor 3
5 is arranged between the gate external terminal 32 and the gate 33. Photodiode array 10 Zeder diode 38, diode 36 and resistors 35, 37 and 39 are formed of polysilicon on the oxide film of the MOSFET.

【0017】この第2実施例の構成とすることで、サブ
端子及び別電源を用いることなく、単一のゲート信号源
により、ゲート駆動が可能となる。
With the configuration of the second embodiment, the gate can be driven by a single gate signal source without using a sub terminal and a separate power supply.

【0018】[0018]

【発明の効果】以上説明したように本発明は、MOSF
ET1のゲート2と外部ゲート端子3の間に、ゲート閾
値電圧補償回路を配置することで、Tch=25℃での
実効ゲート閾値電圧VGS(th)eff(Tch=25℃)
=VGS(th)−2・VF =2.4−1.4=1.0
(V),その温度係数kVGS(th) eff=kVGS(th)
2・kVF =−5−(−4)=−1(mV/℃),なる
特性を有する電界効果トランジスタを与える。
As described above, according to the present invention, the MOSF
By disposing a gate threshold voltage compensating circuit between the gate 2 of the ET1 and the external gate terminal 3, the effective gate threshold voltage V GS (th) eff at Tch = 25 ° C. (Tch = 25 ° C.)
= V GS (th) -2 · V F = 2.4-1.4 = 1.0
(V), its temperature coefficient k VGS (th) eff = k VGS (th)
A field effect transistor having the characteristic of 2 · kV F = −5 − (− 4) = − 1 (mV / ° C.) is provided.

【0019】本発明により、上記特性例の場合、実効ゲ
ート閾値電圧は、 Tch=150℃でVGS(th)eff(Tch=150
℃)=0.875V, Tch=−55℃でVGS(th)eff(Tch=−55
℃)=1.080V とすることができ、MOSFETのチャネル温度全域を
実効動作温度範囲とすることが可能となる。
According to the present invention, in the case of the above characteristic example, the effective gate threshold voltage is V GS (th) eff (Tch = 150 ° C. ) at Tch = 150 ° C.
° C) = 0.875 V, Tch = −55 ° C., and V GS (th) eff (Tch = −55
° C) = 1.080 V, and the entire channel temperature of the MOSFET can be set to the effective operating temperature range.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例の電界効果トランジスタ
を示す図であり、(a)は本発明の第1の実施例の電界
効果トランジスタの構成を示す図で、(b)は(a)に
示すトランジスタのゲート閾値電圧特性図及びダイオー
ド順電圧の温度特性図で、(c)は(a)に示すトラン
ジスタの実効ゲート閾値電圧の温度特性図で、(d)は
本発明の第1の実施例の電界効果トランジスタの基本構
成を示す図である。
FIGS. 1A and 1B are diagrams showing a field effect transistor according to a first embodiment of the present invention; FIG. 1A is a diagram showing a configuration of the field effect transistor according to the first embodiment of the present invention; FIG. 3A is a graph showing a gate threshold voltage characteristic of a transistor and FIG. 4C is a graph showing a temperature characteristic of a diode forward voltage. FIG. 3C is a graph showing a temperature characteristic of an effective gate threshold voltage of the transistor shown in FIG. FIG. 2 is a diagram illustrating a basic configuration of a field-effect transistor according to one embodiment.

【図2】従来の電界効果トランジスタを示す図であり、
(a)は構成図で、(b)はゲート閾値電圧の温度特性
図である。
FIG. 2 is a view showing a conventional field effect transistor;
(A) is a configuration diagram, and (b) is a temperature characteristic diagram of a gate threshold voltage.

【図3】本発明の第2の実施例の電界効果トンランジス
タの構成を示す図である。
FIG. 3 is a diagram illustrating a configuration of a field effect transistor according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1,31 MOSFET 3,33 ゲート 2,32 外部ゲート端子 4 サブ端子 5,7,35,37,39 抵抗 6 ダイオード 8 ツェナーダイオード 10 フォトダイオードアレイ 11 LED 12,30 補償回路 1,31 MOSFET 3,33 Gate 2,32 External gate terminal 4 Sub terminal 5,7,35,37,39 Resistance 6 Diode 8 Zener diode 10 Photodiode array 11 LED 12,30 Compensation circuit

フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 29/78 H01L 27/088 H03K 17/687 Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 29/78 H01L 27/088 H03K 17/687

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ツェナーダイオードの電圧により順バイ
アスされ直列接続されたダイオードと前記ダイオードに
並列接続された抵抗とからなるゲート閾値電圧補償用回
路をゲート端子と外部ゲート端子との間に接続する電界
効果トランジスタ。
An electric field for connecting a gate threshold voltage compensating circuit comprising a diode connected in series and serially connected by a voltage of a Zener diode and a resistor connected in parallel to the diode between a gate terminal and an external gate terminal. Effect transistor.
JP30105792A 1992-11-11 1992-11-11 Field effect transistor Expired - Lifetime JP2910458B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30105792A JP2910458B2 (en) 1992-11-11 1992-11-11 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30105792A JP2910458B2 (en) 1992-11-11 1992-11-11 Field effect transistor

Publications (2)

Publication Number Publication Date
JPH06151844A JPH06151844A (en) 1994-05-31
JP2910458B2 true JP2910458B2 (en) 1999-06-23

Family

ID=17892348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30105792A Expired - Lifetime JP2910458B2 (en) 1992-11-11 1992-11-11 Field effect transistor

Country Status (1)

Country Link
JP (1) JP2910458B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4846106B2 (en) * 2001-02-16 2011-12-28 三菱電機株式会社 Field effect semiconductor device and method for manufacturing the same
JP2015177591A (en) 2014-03-13 2015-10-05 富士電機株式会社 Semiconductor device and semiconductor system

Also Published As

Publication number Publication date
JPH06151844A (en) 1994-05-31

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