JP2909109B2 - Memory controller - Google Patents

Description

Description: Object of the Invention (Industrial Field) The present invention relates to a memory control device particularly suitable for use in a personal computer.

(Prior art) In recent years, with advances in semiconductor technology, microcomputers and memory LS
I. Peripheral control LSIs have been supplied at low cost, and a relatively high-performance personal computer can be constructed simply by combining them appropriately. In the field of personal computers, small-sized, light-weight, and portable laptop-type personal computers have replaced the conventional desktop type and have become popular.

By the way, this kind of personal computer supports so-called resume processing as a standard, in which even when the power is turned off, the system is returned to the state immediately before the power is turned off when the power is turned on again. That is, there is a case where system data other than VRAM data is backed up in advance in a power supply section.
To this end, conventionally, a backup power supply or a backup logic is provided in each memory for data requiring backup.

(Problems to be Solved by the Invention) According to the above-mentioned conventional example, there is a problem that data to be backed up is specified and lacks versatility. Further, when it is desired to commonly use a backed-up memory area for a plurality of purposes. In addition, there is a problem that it takes time to perform processing such as allocation of each area.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory control device having a versatile data backup and easily manageable backup environment by adding a small amount of hardware. And

[Configuration of the Invention] (Means for Solving the Problems) A memory control device of the present invention includes a system memory at least partially backed up by a battery, a decoder for recognizing an address space to be converted, and A base register in which an address value indicating a part backed up by a battery is set as a leading address after address conversion, a page register in which a page address for performing bank switching is set, an address value set in the base register, and the page A selector for obtaining a value obtained by adding an address value set in a register and unconverted raw address information as inputs, and supplying one of them as a part of a memory address to the system memory by an output of the decoder; Address that specifies a predetermined area in the system memory. The scan values, configured to convert the address values belonging to battery backup portion in said system memory.

(Operation) The present invention stores arbitrary data (for example, the contents of VRAM) in a backup memory via a specific address space indicated by the above-described decoder, and performs backup when power is turned off. In addition, even if the system memory is used for backup, for example, for a hard RAM, etc., the free space is reallocated to another use by the address conversion logic consisting of the page register, base register, and addition circuit to perform other data backup. Can be easily used. Thus, all of the system memory,
Alternatively, backup of data is realized by providing a bank switching circuit capable of arbitrarily setting a conversion destination address in a personal computer partially supported by backup.

This makes it easy to store different types of data in a continuous memory space to be backed up.

(Example) Hereinafter, an example of the present invention is described in detail using drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 denotes a base register, in which a head address value for address conversion is set. Sign 2
Is a page register, which facilitates address conversion by bank switching. Reference numeral 3 denotes an adder, which generates a conversion address by adding address information stored in the page register 2 to the base value set in the base register 1. Reference numeral 4 denotes a decoder, which determines whether the address is a conversion target address. Reference numeral 5 denotes an address line to which the converted address is transferred. Reference numeral 6 denotes an address line to which an unconverted address is transferred. Reference numeral 7 denotes a selector, which is selected from the address lines 5 or 6 by the information of the decoder 4 and is used as memory address information.

FIG. 2 is a diagram showing the operation of the embodiment of the present invention on a memory. In the figure, (a) is a frame for address conversion, (b) is a first data backup area, (c)
Is a base address specified by the base register 1. (D) is an area page 0 set by the page register 2; (e) is an area page 1 set by the page register 2;
Is the area page 2 set by. The number of pages can be set by the maximum value that the page register 2 can take, that is, by the capacity.

Hereinafter, the operation of the embodiment of the present invention will be described in detail.
As shown in FIG. 2, a personal computer having a system memory (including an extended memory and the like) in an area which is not set as a backed-up area will be described below. FIG. 2 (b) of the backed up area is an area used for the first purpose. If it is attempted to use the backed-up memory area for the second purpose, the area other than the area (b) becomes a usable area. Therefore, the address value shown in FIG. 2C is set in the base register 1.

In order to store data in the area (d), a value “0” is set in the page register 2 and the area (a) in FIG. 2 is accessed. As a result, an absolute address is obtained from the upper information of the memory address generated by the adder 3 and the selector 6 and the lower information of the address obtained by accessing the area of FIG. 2A, and the access to the area of FIG. Is performed. Similarly, in order to store data in the areas shown in FIGS. 2E and 2F, values "1" and "2" are set in the page register 2 and the area (a) is accessed.

In other words, the backup data is accessed by switching the bank by the page register 2 to the area starting from the address set in the base register 1 with the area shown in FIG.

By having the address conversion circuit as described above, backup of unspecified data becomes possible. In addition, since backup can be performed regardless of the type of data, it is used for data retention unique to the system and a data retention area opened to the user. The resume function can be realized by holding the VRAM data.

[Effects of the Invention] As described above, according to the present invention, the following effects can be obtained.

(1) Different types of data can be easily stored in a continuous memory space to be backed up.

(2) The backup area can be easily increased and decreased.

(3) Regardless of the type of data to be backed up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram cited for explaining the operation of the embodiment of the present invention. 1 ... base register, 2 ... page register, 3 ...
Adder, 4... Decoder, 7.

Claims (1)

(57) [Claims] 1. A system memory at least partially backed up by a battery, a decoder for recognizing an address space to be converted, and an address value indicating a battery backed up portion in the system memory is used as a head address after the address conversion. A base register to be set; a page register to set a page address for bank switching; a value obtained by adding the address value set to the base register to the address value set to the page register; A selector which receives address information as an input, and supplies one of them as a part of a memory address to the system memory by an output of the decoder, wherein an address value designating a predetermined area in the system memory is Battery backup in system memory A memory control device for converting the address value into an address value belonging to the portion.