JP2001175463A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system for providing a boot program area, without suppressing program area by using a relatively smaller-scaled microcomputer, and validly utilizing a memory space. SOLUTION: This computer system is provided with a control means 1 for executing an instruction according to program data, a rewritable first memory means 8 for storing a boot program, a rewritable second memory means 9 for storing an operation program, a mode switching means 7 for selecting either a boot mode or an operation mode, and a memory map converting means 5 for switching the address of the first and second memory means according to the mode selected by the mode switching means. The memory map converting means sets the address of the first and second memory means, so that the operation program can be written in the second memory means according to the boot program in the boot mode, and sets the address of the first and second memory means, so that a prescribed instruction can be executed by a control means according to the operation program in the operation mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device capable of rewriting an operation program according to a built-in boot program.

[0002]

2. Description of the Related Art Conventionally, as a control means incorporated in a single device, a microcomputer of a relatively small scale has been often incorporated mainly for cost reasons. In addition, in order to inherit software assets, it is often necessary to continue using a microcomputer with limited functions.

[0003]

Under such conditions, naturally, the conditions for using the memory are strict, and it is difficult to expand the program area, and the memory space cannot be expanded freely. Was.

In recent years, rewritable nonvolatile memories such as flash memories have become widespread.
When there is any change in the operation program (basic program, application program), it is an essential condition that the program is freely rewritten later without changing the hardware.

However, in order to implement such a mechanism, it is necessary to store a boot program in a program area, and the control means rewrites the program according to the boot program. Under conditions where it is difficult to expand the area, it is difficult to implement this mechanism because of the large restrictions on memory usage.

[0006] In addition, since the reading of the boot program and the writing of the operation program cannot be performed simultaneously on the same memory device, it is necessary to use different memory devices. However, the boot program has an extremely small capacity as compared with the operation program, so that the use efficiency of the memory device is significantly deteriorated.

The present invention has been made to solve such a conventional problem, and it is possible to provide a boot program area without using an operation program area while using a relatively small microcomputer. It is another object of the present invention to provide a computer device capable of effectively utilizing a memory device.

[0008]

According to the present invention, there is provided a computer apparatus comprising: a control unit for executing an instruction according to program data; and a rewritable first storage unit for storing a boot program.
Memory means, a rewritable second memory means for storing an operation program, a mode switching means for selecting one of a boot mode and an operation mode, and a first and a second means in accordance with the mode selected by the mode switching means. Second
Memory map conversion means for switching the address of the memory means, wherein the memory map conversion means writes the operation program from the outside to the second memory means in accordance with the boot program in the boot mode.
In the operation mode, the addresses of the first and second memory units are set so that the control unit executes a predetermined command according to the operation program.

With this configuration, the memory map conversion means changes the addresses of the first and second memory means which can be controlled by the control means in accordance with the mode selected by the mode switching means. The operating program can be written in the second memory means in accordance with the boot program stored in the means, and in the operation mode, predetermined instructions can be executed according to the operating program written in the second memory means. it can.

[0010] Further, the computer device of the present invention comprises:
Has a plurality of bank memory areas including a boot program area, and has a bank memory switching means for selecting an arbitrary bank memory area from the plurality of bank memory areas.

With this configuration, the control means selects the boot program stored in the first memory means in the boot mode, and selects an arbitrary bank memory area from the plurality of bank memory areas of the first memory means in the operation mode. Can be selected and referred to as a parameter, and the use efficiency of the first memory means can be increased.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a computer device according to the present invention. In this computer device, a relatively small-scale microcomputer is mounted as a control means 1. The control means 1 has a data transfer (I / O) input / output port 3 via a data bus 2, and a bank memory switch. The section 4, the memory map conversion section 5, the bank register 6, and the boot switch 7 are connected. It is assumed that a control target (not shown) is also connected to the data bus 2.

The boot switch 7 is a memory switching means for selecting one of an operation mode for realizing a predetermined function of the device and a boot mode for externally writing a program.

The computer device includes a first flash memory 8 connected to the bank memory switching unit 4 and the memory map conversion unit 5, a second flash memory 9 connected to the memory map conversion unit 5, and a static memory. And a work memory 10 having a form RAM (SRAM) configuration. The flash memories 8 and 9 are rewritable nonvolatile memories.

FIG. 2 is a memory map of the first flash memory 8, showing the internal addresses and the data to be stored. The first flash memory 8 stores the internal address “7FFFFH to 00000H” in units of 64 KB.
BNK1 to BNK7 store predetermined parameters, respectively, and BNK8 stores a boot program. Note that “H” means hexadecimal display.

FIG. 3 is a memory map diagram of the second flash memory 9, showing an internal address and data to be stored. In the second flash memory 9, 384 KB of the internal address “7FFFFH to 20000H” is a program area, and the internal address “1FFFF to H” is used.
“00000H” is access prohibited.

In this configuration, when the boot switch 7 is set to the boot mode, the relationship between the address of the control means 1 and each of the memories 8 to 10 is controlled by the memory map conversion unit 5 to control the memory map shown in FIG. The relationship is as shown in FIG.

That is, the addresses "FFFFFH to F0"
"000H" indicates the boot program of the first flash memory 8, and the address "7FFFFH to 20000H"
Indicates a program writing area of the second flash memory 9 to which a program is externally written, and an address “1FFFFH to 00000H” indicates the work memory 10.

In this example, the control means 1 sets the address "FFF
FFH ”side, the first in boot mode
In accordance with the boot program stored in the flash memory 8, the operation program (basic program, application program, etc.) stored in the external memory is transferred to the second flash memory 9 via the memory transfer I / O port 2. Will write.

Next, when the boot switch 7 is set to the operation mode, the address of the control means 1 and each of the memories 8 to 10 are set.
Is controlled by the memory map conversion unit 5 as shown in FIG.
Are obtained as shown in the memory map of FIG.

That is, the address "FFFFFFH to A0"
"000H" indicates the program area of the second flash memory 9, address "9FFFFH to 90000H" indicates the parameter area of the first flash memory 8, and address "7FFFFH to 00000H" indicates the work memory 10.

Since the control means 1 is started from the address "FFFFFH", it operates according to the operation program stored in the second flash memory 9 in the operation mode. At this time, the address “9FFFFH-90000”
In the parameter area “H”, B stored in the first flash memory 8 under the control of the bank memory switching unit 4 is stored.
Any one of NK1 to BNK8 will be assigned. At this time, the contents of BNK1 to BNK8 can be rewritten.

Next, the operation of the memory map conversion unit 5 will be described with reference to the processing flow charts shown in FIGS.

First, it is determined whether the boot switch 7 is set to the normal operation mode or the boot mode (step S1). When the boot mode is set, the most significant bit (M
SB) It is determined whether An is 0 or 1 (step S2).

If bit An is 0, then bit An-
It is determined whether 1 is 0 or 1 (step S3), and the bit An-1 is determined.
Is 0, it is determined whether the bit An-2 is 0 or 1 (step S4).

As a result, if the bit An-2 is 0, the address points to the work memory 10; if the bit An-2 is 1, the address points to the second flash memory 9;
If the bit An-1 is 1, the address also points to the second flash memory 9.

On the other hand, if the bit An is 1, then it is determined whether the bit An-1 is 0 or 1 (step S5). If the bit An-1 is 0, then the bit An-2 is 0. It is determined whether the bit An-2 is 0 (step S6).
Next, it is determined whether bit An-3 is 0 or 1 (step S3).
7).

As a result, if the bit An-3 is 0, the address indicates the extension area, if the bit An-3 is 1, the address indicates the unmounted part, and if the bit An-2 is 1, the address indicates the extension area. Similarly, it indicates an unmounted part.

If bit An-1 is 1, it is next determined whether bit An-2 is 0 or 1 (step S8). If bit An-2 is 1, then bit An-3 is next determined. Is determined to be 0 or 1 (step S9).

As a result, if the bit An-2 is 0, the address indicates the unmounted part, if the bit An-3 is 0, the address indicates the unmounted part, and if the bit An-3 is 1, the address indicates the unmounted part. The address points to the first flash memory 8.

In step S1, the boot switch 7
Is set to the normal operation mode, the memory map conversion means 4 determines whether the most significant bit (MSB) An of the address of the control means 1 is 0 or 1 (step S11).
If the bit An is 0, the address is
Point to.

If bit An is 1, then bit An-
It is determined whether 1 is 0 or 1 (step S12), and the bit An-
If 1 is 0, it is next determined whether bit An-2 is 0 or 1 (step S13). If bit An-2 is 0, it is next determined whether bit An-3 is 0 or 1. (Step S1
4).

As a result, if the bit An-3 is 0, the address points to the extended area, and if the bit An-3 is 1, the address points to the first flash memory 8 and the bit An-2
Is 1, the address points to the second flash memory 9, and if the bit An-1 is 1, the address points to the second flash memory 9.

FIG. 8 shows an address when the memory space is divided into 16 by the upper 4 bits (highest digit of hexadecimal notation) of the address of the control means 1 and each of the memories 8 to 1.
It is a figure showing the relation with 0. In this example, since there are 20 address bits (A1 to A20), n = 2
0, and An = A20, An-1 = A19, An-2 =
A18, An-3 = 17.

Next, the operation of the bank memory switching section 4 will be described with reference to the processing flow chart shown in FIG.

When the address of the control means 1 points to the first flash memory 8 in the normal operation mode, that is, when the address bits An to An-3 are "1001", the data is stored in the bank register 6. According to the contents of bits BD1 to BD3 of the 3-bit bank data, bank memory switching unit 4 operates as follows.

First, it is determined whether the bit BD1 is 0 or 1 (step S21). If bit BD1 is 0, it is next determined whether bit BD2 is 0 or 1 (step S22).
If bit BD2 is 0, then bit BD3 is 0 or 1
(Step S23), if the bit BD3 is 0, specify BNK8, that is, the boot program; if the bit BD3 is 1, specify BNK1.

If bit BD2 is 1, it is next determined whether bit BD3 is 0 or 1 (step S24). If bit BD3 is 0, BNK2 is designated and bit BD3 is set.
If 3 is 1, BNK3 is designated.

On the other hand, if bit BD1 is 1, it is next determined whether bit BD2 is 0 or 1 (step S25). If bit BD2 is 0, it is next determined whether bit BD3 is 0 or 1 (step S26). If bit BD3 is 0, BNK4 is specified; if bit BD3 is 1, BNK4 is specified.
Specify NK5.

If bit BD2 is 1, it is next determined whether bit BD3 is 0 or 1 (step S27). If bit BD3 is 0, BNK6 is designated and bit BD3 is set.
If 3 is 1, BNK7 is specified.

In this way, one of BNK1 to BNK8 is selected according to the bank data of the bank register 6, and the selected bank is directly accessed by the control means 1 via the memory map conversion unit 5.

[0043]

As described above, according to the present invention, the addresses of the first and second memory means controlled by the control means are switched between the boot mode and the operation mode, and the first memory means is switched in the boot mode. The operation program is written in the second memory means in accordance with the boot program stored in the second memory means, and in the operation mode, a predetermined command is executed in accordance with the operation program written in the second memory means. This can be realized without using a control means having a relatively small scale and limited functions.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a computer device according to the present invention.

FIG. 2 is a memory map diagram of a first flash memory.

FIG. 3 is a memory map diagram of a second flash memory.

FIG. 4 is a memory map diagram showing a relationship between addresses and respective memories in a boot mode.

FIG. 5 is a memory map diagram showing a relationship between an address and each memory in an operation mode.

FIG. 6 is a processing flowchart showing the operation of a memory map conversion unit (1).

FIG. 7 is a processing flowchart showing the operation of the memory map conversion unit (2).

FIG. 8 is a memory map diagram showing a relationship between addresses and respective memories in a boot mode and an operation mode.

FIG. 9 is a processing flowchart showing the operation of the bank memory switching unit.

[Explanation of symbols]

 Reference Signs List 1 control means 2 data bus 3 memory transfer I / O port 4 bank memory switching unit 5 memory map conversion unit 6 bank register 7 boot switch 8 first flash memory 9 second flash memory 10 work memory

Claims (2)

[Claims] Control means for executing an instruction in accordance with program data; rewritable first memory means for storing a boot program; rewritable second memory means for storing an operation program; A mode switching unit for selecting one of the modes; and a memory map conversion unit for switching addresses of the first and second memory units according to the mode selected by the mode switching unit. Sets the addresses of the first and second memory means so that the operation program is written in the second memory means according to the boot program in the boot mode, and the control means according to the operation program in the operation mode The first and second instructions are executed to execute a predetermined instruction. Computer device and sets the address of the memory means. 2. The first memory means has a plurality of bank memory areas including the boot program area, and has a bank memory switching means for selecting an arbitrary bank memory area from the plurality of bank memory areas. The computer device according to claim 1, wherein: