JPH11234491A - Communications terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communications terminal that rewrites a control program at a low cost with easy operation. SOLUTION: In the communications terminal, a control program is stored in a flush memory 13 and a socket 16 is provided, in/from which an EPROM 21 storing a write program to rewrite the control program stored in the flush memory 13 and storing a control program written in the flush memory by the write program is loaded/unloaded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication terminal for a facsimile machine, and more particularly to a communication terminal for easily rewriting a control program.

[0002]

2. Description of the Related Art In recent years, facsimile apparatuses as communication terminal apparatuses have become widespread in many offices, educational institutions, and homes.
When rewriting is performed to fix a bug, a lot of trouble and expense are required.

More specifically, the control program is a mask RO
If it is stored in non-rewritable nonvolatile storage means such as M, it is necessary to replace the nonvolatile storage means itself or replace the entire main board on which it is mounted. When a rewritable nonvolatile storage means such as an EEPROM or a flash memory is used, it is necessary to store a rewriting program (update program) in another portion.

[0004]

The former requires a great deal of expense and labor to replace the ROM or main board, while the latter requires a specially trained worker.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a communication terminal device that can rewrite a control program at a low cost and with a simple operation.

[0006]

A communication terminal device according to the present invention is capable of writing a control program to a flash memory in a communication terminal device storing its own control program in a flash memory mounted on a board. Characterized in that a socket on which a recording medium recorded in a proper state can be attached and detached is provided on a substrate.

In such a communication terminal device of the present invention, the recording medium on which the control program is recorded in a state in which the control program can be written into the flash memory is mounted on the socket provided on the substrate, thereby mounting the control program on the substrate. The contents of the flash memory are rewritten. Therefore, the control program can be rewritten at low cost and easily.

In the communication terminal device according to the present invention, the recording medium stores a writing program capable of writing a control program into the flash memory, and the flash memory is executed by executing the writing program. In which a control program is written.

In such a communication terminal device of the present invention, a write program capable of writing a control program in the flash memory is stored in the recording medium. Therefore, the write program can be executed while the recording medium is mounted in the socket. When executed, the control program is written to the flash memory. Therefore, the control program can be rewritten at low cost and easily.

[0010] Further, the communication terminal device of the present invention, in the above-described configuration, includes a storage means for storing a startup program, and reads and executes the control program from the flash memory after the execution of the startup program, or is mounted on the socket. Switching means capable of selecting either operation of reading and executing a write program from a recording medium is provided.

In the communication terminal device of the present invention, the control program is read out from the flash memory and executed after the execution of the start-up program stored in the storage means, or the control program is written from the recording medium attached to the socket. Since it is possible to select either the operation of reading the program and rewriting the contents of the flash memory, the control program can be rewritten inexpensively and easily.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a configuration example of a first embodiment in which a communication terminal device according to the present invention (hereinafter, referred to as the present device) is applied to a facsimile machine.

The following hardware components are connected to the CPU 11 and normally operate in accordance with a control software program and various data stored in a flash memory 13 described later. But plug socket 16
EPROM 21 as a recording medium is mounted on the
By changing the setting of 5, the CPU 11 performs an operation of rewriting the contents of the flash memory 13 in accordance with the program stored in the EPROM 21.

The reading section 2 reads an original with a scanner using a CCD or the like, and outputs dot image data converted into black and white binary.

The recording unit 3 functions as a recording unit. In the apparatus of the present invention, a digital electrophotographic apparatus is used. The image data received by facsimile communication from another communication terminal device and the original read by the reading unit 2 Can be printed out as a hard copy and recorded.

The display unit 4 is a liquid crystal display (LCD) or C
A display device such as an RT display, which displays the operation state of the present invention device, displays image data of a document to be transmitted by facsimile communication, received image data, and furthermore, a transmission destination at the time of broadcast communication. List display.

The operation unit 5 includes character keys, numeric keys (numerical keys), speed dial keys, one-touch dial keys, various function keys, and the like necessary for operating the apparatus of the present invention. In addition, by using the touch panel type as the display unit 4, some or all of the various keys of the operation unit 5 can be substituted.

The modem 6 modulates the facsimile signal to N
The demodulated facsimile signal supplied from the NCU 7 is output to the CPU 11. NCU (Netw
ork Control Unit) 7 is controlled by the CPU 11 to close and open the line L, transmits a modulated facsimile signal output from the modem 6 to the line L, and receives a modulated facsimile signal received from the line L. Signal is given to NCU7. Note that a handset 8 is connected to the NCU 7 so that a normal voice call is possible.

The CPU 11 is mounted on a main board 10, and various circuits such as a RAM 12, a flash memory 13 and the like are mounted on the main board 10. Further, the main board 10 is provided with a plug-in socket 16 to which an EPROM 21 described later can be attached and detached, and also provided with jumpers indicated by reference numerals 14 and 15.

Jumper 14 is a flash memory from CPU 11
13 is the chip select signal CS0 or chip select signal
Provided to give CS1. Normally, this jumper 14 is the chip select signal CS0 of the chip select signal CS0 and the chip select signal CS1 output from the CPU 11.
It is set so that 0 is output and given to the flash memory 13. Further, the jumper 15 is provided for supplying the chip select signal CS0 or the chip select signal CS1 from the CPU 11 to the EPROM 21. Normally this jumper 15 is CPU
It is set so as to output the chip select signal CS1 out of the chip select signal CS0 and the chip select signal CS1 output from 11.

An EPROM 21 is detachable from the insertion socket 16. Therefore, the EPROM 21
Is mounted, a chip select signal CS0 or a chip select signal CS1 output from the CPU 11 is provided.

AB indicates an address bus, DB indicates a data bus, and the CPU 11, the flash memory 13 and the E
An address signal Add and data Data are exchanged with the PROM 21. The above-mentioned insertion socket 16 connects the address bus AD and the data bus DB to the CPU 11 and the EPROM.
Connect with 21.

The flash memory 13 is a rewritable non-volatile memory, which stores the write software program of the device of the present invention and various data necessary at the time of operation, as described above. They are stored in order. On the other hand, the EPROM 21 is a memory in which new data can be written after erasing its stored contents. A write program for rewriting the contents of the flash memory 13 starts from the top address, and is newly written to the flash memory 13 by this write program. The control software program to be stored in the control program is previously written as data from an address next to the last address of the control program by appropriate means.

FIG. 2 is a schematic diagram showing an address map of the CPU 11. Address "00000000h" to "003FFFFFh"
Up to 4 Mbytes are allocated to the chip select signal CS0, and the addresses “00400000h” to “007FFFFFh”
Up to 4 Mbytes are allocated to the chip select signal CS1. Therefore, normally, 4 MB from the address “00000000h” to “003FFFFFh” is stored in the flash memory 13.
The address "00400000h" to "007FFFFFh"
4 Mbytes are allocated to EPROM 21 respectively. Note that “h” indicates a hexadecimal number.

However, when the jumpers 14 and 15 are set in the opposite direction, the addresses "00000000h" to "003F
The 4 Mbytes up to “FFFFh” are allocated to the chip select signal CS0, so the EPROM 21 stores the address “00400000h
The 4M bytes from "" to "007FFFFFh" are allocated to the chip select signal CS1 so that the flash memory
13 respectively. Therefore, when rewriting the contents of the flash memory 13, the jumper 14
May be set so that the chip select signal CS1 is supplied to the flash memory 13 and the jumper 15 is set so that the chip select signal CS0 is supplied to the EPROM 21.

Next, the operation of the first embodiment of the present invention as described above will be described. Normally, the EPROM 21 is not mounted on the insertion socket 16, and the jumper 14 outputs the chip select signal CS0.
Are set to output the chip select signal CS1. Thereby, when starting the present invention device,
The program is read in order from the address “00000000h” and operation starts. In this case, the address “00000000”
h ”is the start address of the flash memory 13, so
The operation is performed by a normal control software program stored in the flash memory 13 from the start address.

However, when it is necessary to rewrite the contents of the flash memory 13, the setting is made so that the chip select signal CS1 is output from the jumper 14 and the chip select signal CS0 is output from the jumper 15. Is changed, and the EPROM 21 is attached to the insertion socket 16. Then, when the device of the present invention is started, the address “00”
The operation is started by reading the program in order from 000000h. In this case, the address “00000000h” is
Since the start address is 21, the EPROM 21 is started and operated by the rewriting program stored from the start address in the EPROM 21.

Since a new control software program for writing to the flash memory 13 is stored in the EPROM 21 in addition to the write program, the EPROM 21
From the start address of the flash memory 13 (in this case, “
00400000h ") Thereafter, a new control software program is written.

As described above, when a new control software program is written from the EPROM 21 to the flash memory 13, the power supply of the present invention is once turned off.
Then, the chip select signal CS0 is output from the jumper 14, and the chip select signal CS1 is output from the jumper 15.
Is changed, and the EPROM 21 is removed from the insertion socket 16. When the apparatus of the present invention is restarted, the program is read in order from address "00000000h" to start the operation. In this case, since the address "00000000h" is allocated to the flash memory 13, this flash memory 13 Is started and operated by a new control software program written and stored in advance.

Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration example of the second embodiment of the present invention. The same components as those in the first embodiment are denoted by the same reference numerals.

The hardware difference between the second embodiment shown in FIG. 3 and the first embodiment shown in FIG. 1 is that a boot program is stored in the CPU 11. The internal ROM 17 is provided, the jumpers 14 and 15 are not provided, and the insertion socket 16 is configured to be able to connect the chip select signal in addition to the address bus AB and the data bus DB. That is.

The built-in ROM 17 is provided with a mode terminal MT. In the present embodiment, when a signal "0" is input to the mode terminal MT, the normal mode (built-in RO) is set.
When the signal “1” is input to the mode terminal MT in the M valid mode, the mode can be switched between the two modes so as to be in the rewrite mode (internal ROM invalid mode).

In the present embodiment, the chip select signal output from the CPU 11 is a chip select signal.
Only CS0 is used, and the address map of the CPU 11 is as shown in the schematic diagram of FIG.

As shown in FIG. 4A, in the normal mode of the built-in ROM 17 in which the signal "0" is input to the mode terminal MT, the addresses "00000000h" to "0001FF" are set.
The 128K bytes up to FFh are allocated to the internal ROM 17, and the addresses from "00020000h" to "001FFFFFh" are reserved (reserved) and are prohibited from being used. Are assigned to the chip select signal CS0.

Therefore, in the normal mode, since only the chip select signal CS0 is output from the CPU 11,
From the address “00200000h” to the flash memory 13
2M bytes up to 003FFFFFh "are allocated, and no address is allocated to the EPROM 21.

On the other hand, as shown in FIG. 4B, in the rewrite mode of the built-in ROM 17 in which the signal "1" is input to the mode terminal MT, the addresses from "00000000h" to "0001FFFFh" are stored. 128 Kbytes are allocated to the chip select signal CSEXROM, and the address “00020000”
4M bytes from "h" to "003FFFFFh" are allocated to the chip select signal CS0.

Therefore, in the rewrite mode, the CPU 11
Since only the chip select signal CSEXROM is output from, the EPROM 21 has addresses "00000000h" to "00
128K bytes up to 1FFFFFh ”will be allocated, and the flash memory 13 will be assigned from“ 00200000h ”to“ 003F
4M bytes up to FFFFh "will be allocated.

Next, the operation of the above-described second embodiment of the present invention will be described. Normally, the EPROM 21 is not installed in the socket 16 and the internal ROM
The signal "0" is input to the mode terminal MT of the seventeenth mode, and the mode is the normal mode. For this reason, when starting the apparatus of the present invention, the CPU 11 reads the program sequentially from the address “00000000h” and starts the operation. In this case, since the address “00000000h” is the head address of the internal ROM 17, The boot program stored in the ROM 17 from the start address is executed. After that, the CPU 11 reads out the operation program allocated to the flash memory 13 after the address “00200000h” and operates.

However, if it becomes necessary to rewrite the contents of the flash memory 13,
By mounting the PROM 21 and inputting the signal “1” to the mode terminal MT of the built-in ROM 17 to start the apparatus of the present invention in the rewrite mode, the CPU 11 sets the address “00000000h”.
The program is read in order from "" and the operation starts. In this case, since the address "00000000h" is the start address of the EPROM 21, the program is started by the rewriting program stored in the EPROM 21 from the start address. Operate.

Since a new control software program for writing to the flash memory 13 is stored in the EPROM 21 in addition to the write program, the EPROM 21
From the start address of the flash memory 13 (in this case, “
00200000h ”) Thereafter, a new control software program is written.

As described above, when a new control software program is written from the EPROM 21 to the flash memory 13, the power of the device of the present invention is once turned off.
Then, a signal “0” is input to the mode terminal MT of the internal ROM 17 to set the normal mode. Then, when the apparatus of the present invention is restarted, the program is read in order from the address “00000000h” to start the operation.
Since "0000h" is allocated to the flash memory 13, it is started and operated by a new control software program previously written and stored in the flash memory 13.

As described above, according to the apparatus of the present invention, when it is necessary to rewrite a control software program for version upgrade or bug correction, a new software program and a new software program are written to the flash memory 13. One of the programs storing the writing program
It is only necessary to visit each business office, educational institution, home, etc. with the EPROM 21 carried, and the rewriting operation of the control software program itself is extremely easy.

In the above embodiment, the EPROM is used as the recording medium. However, it is needless to say that the recording medium may be an EEPROM, or another recording medium such as a memory card may be used. A socket corresponding to the recording medium may be provided on the substrate.

In the above-described embodiment, the embodiment in which the communication terminal apparatus of the present invention is applied to a facsimile apparatus is shown. However, the present invention is not limited to the facsimile apparatus, and other examples include facsimile communication. Needless to say, the present invention can be applied to a personal computer having a function.

[0045]

As described in detail above, according to the communication terminal apparatus of the present invention, even if it becomes necessary to rewrite the control program for version upgrade, bug correction, etc., a new program can be used. It is only necessary to visit each office, educational institution, home, etc. with one EPROM carrying the program and a writing program for writing the program, and the cost is low. The rewriting operation itself is extremely easy.

In such a communication terminal device of the present invention, the recording medium on which the control program is recorded in a state in which the control program can be written in the flash memory is mounted on the socket provided on the substrate, thereby mounting the control program on the substrate. The contents of the flash memory are rewritten. Therefore, the control program can be rewritten at low cost and easily.

In such a communication terminal device of the present invention, a write program capable of writing the control program in the flash memory is stored in the recording medium, so that the write program can be executed while the recording medium is mounted in the socket. When executed, the control program is written to the flash memory. Therefore, the control program can be rewritten at low cost and easily.

In such a communication terminal device of the present invention, the control program can be read from the flash memory and executed after the execution of the start-up program stored in the storage means, or can be written from the recording medium attached to the socket. Since it is possible to select either the operation of reading the program and rewriting the contents of the flash memory, the control program can be rewritten inexpensively and easily.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a first embodiment when a communication terminal device according to the present invention is applied to a facsimile device.

FIG. 2 is a schematic diagram showing an address map of a CPU according to the first embodiment when the communication terminal device according to the present invention is applied to a facsimile device.

FIG. 3 is a block diagram illustrating a configuration example of a second embodiment when a communication terminal device according to the present invention is applied to a facsimile device.

FIG. 4 is a schematic diagram showing an address map of a CPU according to a second embodiment when the communication terminal device according to the present invention is applied to a facsimile device.

[Explanation of symbols]

10 Main board, 11 CPU, 13 Flash memory, 14
Jumper, 15 Jumper, 16 socket, 17
Internal ROM, 21 EPROM, MT mode pins.

Claims (3)

[Claims] 1. A communication terminal device for storing its control program in a flash memory mounted on a substrate, wherein a recording medium in which the control program is recorded in such a manner that the control program can be written in the flash memory is detachable. A communication terminal device comprising a simple socket on the substrate. 2. The recording medium stores a write program capable of writing the control program in the flash memory, and executes the control program from the recording medium to the flash memory by executing the write program. The communication terminal device according to claim 1, wherein the communication terminal device is written. 3. A storage means for storing a start-up program, wherein the control program is read out from the flash memory and executed after the execution of the start-up program, or the writing program is read out from a recording medium mounted on the socket. 3. The communication terminal device according to claim 2, further comprising a switching unit capable of selecting one of the operations to be executed.